xref: /linux/tools/perf/pmu-events/arch/x86/bonnell/cache.json (revision fd7d598270724cc787982ea48bbe17ad383a8b7f) 
1[
2    {
3        "BriefDescription": "L1 Data Cacheable reads and writes",
4        "EventCode": "0x40",
5        "EventName": "L1D_CACHE.ALL_CACHE_REF",
6        "SampleAfterValue": "2000000",
7        "UMask": "0xa3"
8    },
9    {
10        "BriefDescription": "L1 Data reads and writes",
11        "EventCode": "0x40",
12        "EventName": "L1D_CACHE.ALL_REF",
13        "SampleAfterValue": "2000000",
14        "UMask": "0x83"
15    },
16    {
17        "BriefDescription": "Modified cache lines evicted from the L1 data cache",
18        "EventCode": "0x40",
19        "EventName": "L1D_CACHE.EVICT",
20        "SampleAfterValue": "200000",
21        "UMask": "0x10"
22    },
23    {
24        "BriefDescription": "L1 Cacheable Data Reads",
25        "EventCode": "0x40",
26        "EventName": "L1D_CACHE.LD",
27        "SampleAfterValue": "2000000",
28        "UMask": "0xa1"
29    },
30    {
31        "BriefDescription": "L1 Data line replacements",
32        "EventCode": "0x40",
33        "EventName": "L1D_CACHE.REPL",
34        "SampleAfterValue": "200000",
35        "UMask": "0x8"
36    },
37    {
38        "BriefDescription": "Modified cache lines allocated in the L1 data cache",
39        "EventCode": "0x40",
40        "EventName": "L1D_CACHE.REPLM",
41        "SampleAfterValue": "200000",
42        "UMask": "0x48"
43    },
44    {
45        "BriefDescription": "L1 Cacheable Data Writes",
46        "EventCode": "0x40",
47        "EventName": "L1D_CACHE.ST",
48        "SampleAfterValue": "2000000",
49        "UMask": "0xa2"
50    },
51    {
52        "BriefDescription": "Cycles L2 address bus is in use.",
53        "EventCode": "0x21",
54        "EventName": "L2_ADS.SELF",
55        "SampleAfterValue": "200000",
56        "UMask": "0x40"
57    },
58    {
59        "BriefDescription": "All data requests from the L1 data cache",
60        "EventCode": "0x2C",
61        "EventName": "L2_DATA_RQSTS.SELF.E_STATE",
62        "SampleAfterValue": "200000",
63        "UMask": "0x44"
64    },
65    {
66        "BriefDescription": "All data requests from the L1 data cache",
67        "EventCode": "0x2C",
68        "EventName": "L2_DATA_RQSTS.SELF.I_STATE",
69        "SampleAfterValue": "200000",
70        "UMask": "0x41"
71    },
72    {
73        "BriefDescription": "All data requests from the L1 data cache",
74        "EventCode": "0x2C",
75        "EventName": "L2_DATA_RQSTS.SELF.MESI",
76        "SampleAfterValue": "200000",
77        "UMask": "0x4f"
78    },
79    {
80        "BriefDescription": "All data requests from the L1 data cache",
81        "EventCode": "0x2C",
82        "EventName": "L2_DATA_RQSTS.SELF.M_STATE",
83        "SampleAfterValue": "200000",
84        "UMask": "0x48"
85    },
86    {
87        "BriefDescription": "All data requests from the L1 data cache",
88        "EventCode": "0x2C",
89        "EventName": "L2_DATA_RQSTS.SELF.S_STATE",
90        "SampleAfterValue": "200000",
91        "UMask": "0x42"
92    },
93    {
94        "BriefDescription": "Cycles the L2 cache data bus is busy.",
95        "EventCode": "0x22",
96        "EventName": "L2_DBUS_BUSY.SELF",
97        "SampleAfterValue": "200000",
98        "UMask": "0x40"
99    },
100    {
101        "BriefDescription": "Cycles the L2 transfers data to the core.",
102        "EventCode": "0x23",
103        "EventName": "L2_DBUS_BUSY_RD.SELF",
104        "SampleAfterValue": "200000",
105        "UMask": "0x40"
106    },
107    {
108        "BriefDescription": "L2 cacheable instruction fetch requests",
109        "EventCode": "0x28",
110        "EventName": "L2_IFETCH.SELF.E_STATE",
111        "SampleAfterValue": "200000",
112        "UMask": "0x44"
113    },
114    {
115        "BriefDescription": "L2 cacheable instruction fetch requests",
116        "EventCode": "0x28",
117        "EventName": "L2_IFETCH.SELF.I_STATE",
118        "SampleAfterValue": "200000",
119        "UMask": "0x41"
120    },
121    {
122        "BriefDescription": "L2 cacheable instruction fetch requests",
123        "EventCode": "0x28",
124        "EventName": "L2_IFETCH.SELF.MESI",
125        "SampleAfterValue": "200000",
126        "UMask": "0x4f"
127    },
128    {
129        "BriefDescription": "L2 cacheable instruction fetch requests",
130        "EventCode": "0x28",
131        "EventName": "L2_IFETCH.SELF.M_STATE",
132        "SampleAfterValue": "200000",
133        "UMask": "0x48"
134    },
135    {
136        "BriefDescription": "L2 cacheable instruction fetch requests",
137        "EventCode": "0x28",
138        "EventName": "L2_IFETCH.SELF.S_STATE",
139        "SampleAfterValue": "200000",
140        "UMask": "0x42"
141    },
142    {
143        "BriefDescription": "L2 cache reads",
144        "EventCode": "0x29",
145        "EventName": "L2_LD.SELF.ANY.E_STATE",
146        "SampleAfterValue": "200000",
147        "UMask": "0x74"
148    },
149    {
150        "BriefDescription": "L2 cache reads",
151        "EventCode": "0x29",
152        "EventName": "L2_LD.SELF.ANY.I_STATE",
153        "SampleAfterValue": "200000",
154        "UMask": "0x71"
155    },
156    {
157        "BriefDescription": "L2 cache reads",
158        "EventCode": "0x29",
159        "EventName": "L2_LD.SELF.ANY.MESI",
160        "SampleAfterValue": "200000",
161        "UMask": "0x7f"
162    },
163    {
164        "BriefDescription": "L2 cache reads",
165        "EventCode": "0x29",
166        "EventName": "L2_LD.SELF.ANY.M_STATE",
167        "SampleAfterValue": "200000",
168        "UMask": "0x78"
169    },
170    {
171        "BriefDescription": "L2 cache reads",
172        "EventCode": "0x29",
173        "EventName": "L2_LD.SELF.ANY.S_STATE",
174        "SampleAfterValue": "200000",
175        "UMask": "0x72"
176    },
177    {
178        "BriefDescription": "L2 cache reads",
179        "EventCode": "0x29",
180        "EventName": "L2_LD.SELF.DEMAND.E_STATE",
181        "SampleAfterValue": "200000",
182        "UMask": "0x44"
183    },
184    {
185        "BriefDescription": "L2 cache reads",
186        "EventCode": "0x29",
187        "EventName": "L2_LD.SELF.DEMAND.I_STATE",
188        "SampleAfterValue": "200000",
189        "UMask": "0x41"
190    },
191    {
192        "BriefDescription": "L2 cache reads",
193        "EventCode": "0x29",
194        "EventName": "L2_LD.SELF.DEMAND.MESI",
195        "SampleAfterValue": "200000",
196        "UMask": "0x4f"
197    },
198    {
199        "BriefDescription": "L2 cache reads",
200        "EventCode": "0x29",
201        "EventName": "L2_LD.SELF.DEMAND.M_STATE",
202        "SampleAfterValue": "200000",
203        "UMask": "0x48"
204    },
205    {
206        "BriefDescription": "L2 cache reads",
207        "EventCode": "0x29",
208        "EventName": "L2_LD.SELF.DEMAND.S_STATE",
209        "SampleAfterValue": "200000",
210        "UMask": "0x42"
211    },
212    {
213        "BriefDescription": "L2 cache reads",
214        "EventCode": "0x29",
215        "EventName": "L2_LD.SELF.PREFETCH.E_STATE",
216        "SampleAfterValue": "200000",
217        "UMask": "0x54"
218    },
219    {
220        "BriefDescription": "L2 cache reads",
221        "EventCode": "0x29",
222        "EventName": "L2_LD.SELF.PREFETCH.I_STATE",
223        "SampleAfterValue": "200000",
224        "UMask": "0x51"
225    },
226    {
227        "BriefDescription": "L2 cache reads",
228        "EventCode": "0x29",
229        "EventName": "L2_LD.SELF.PREFETCH.MESI",
230        "SampleAfterValue": "200000",
231        "UMask": "0x5f"
232    },
233    {
234        "BriefDescription": "L2 cache reads",
235        "EventCode": "0x29",
236        "EventName": "L2_LD.SELF.PREFETCH.M_STATE",
237        "SampleAfterValue": "200000",
238        "UMask": "0x58"
239    },
240    {
241        "BriefDescription": "L2 cache reads",
242        "EventCode": "0x29",
243        "EventName": "L2_LD.SELF.PREFETCH.S_STATE",
244        "SampleAfterValue": "200000",
245        "UMask": "0x52"
246    },
247    {
248        "BriefDescription": "All read requests from L1 instruction and data caches",
249        "EventCode": "0x2D",
250        "EventName": "L2_LD_IFETCH.SELF.E_STATE",
251        "SampleAfterValue": "200000",
252        "UMask": "0x44"
253    },
254    {
255        "BriefDescription": "All read requests from L1 instruction and data caches",
256        "EventCode": "0x2D",
257        "EventName": "L2_LD_IFETCH.SELF.I_STATE",
258        "SampleAfterValue": "200000",
259        "UMask": "0x41"
260    },
261    {
262        "BriefDescription": "All read requests from L1 instruction and data caches",
263        "EventCode": "0x2D",
264        "EventName": "L2_LD_IFETCH.SELF.MESI",
265        "SampleAfterValue": "200000",
266        "UMask": "0x4f"
267    },
268    {
269        "BriefDescription": "All read requests from L1 instruction and data caches",
270        "EventCode": "0x2D",
271        "EventName": "L2_LD_IFETCH.SELF.M_STATE",
272        "SampleAfterValue": "200000",
273        "UMask": "0x48"
274    },
275    {
276        "BriefDescription": "All read requests from L1 instruction and data caches",
277        "EventCode": "0x2D",
278        "EventName": "L2_LD_IFETCH.SELF.S_STATE",
279        "SampleAfterValue": "200000",
280        "UMask": "0x42"
281    },
282    {
283        "BriefDescription": "L2 cache misses.",
284        "EventCode": "0x24",
285        "EventName": "L2_LINES_IN.SELF.ANY",
286        "SampleAfterValue": "200000",
287        "UMask": "0x70"
288    },
289    {
290        "BriefDescription": "L2 cache misses.",
291        "EventCode": "0x24",
292        "EventName": "L2_LINES_IN.SELF.DEMAND",
293        "SampleAfterValue": "200000",
294        "UMask": "0x40"
295    },
296    {
297        "BriefDescription": "L2 cache misses.",
298        "EventCode": "0x24",
299        "EventName": "L2_LINES_IN.SELF.PREFETCH",
300        "SampleAfterValue": "200000",
301        "UMask": "0x50"
302    },
303    {
304        "BriefDescription": "L2 cache lines evicted.",
305        "EventCode": "0x26",
306        "EventName": "L2_LINES_OUT.SELF.ANY",
307        "SampleAfterValue": "200000",
308        "UMask": "0x70"
309    },
310    {
311        "BriefDescription": "L2 cache lines evicted.",
312        "EventCode": "0x26",
313        "EventName": "L2_LINES_OUT.SELF.DEMAND",
314        "SampleAfterValue": "200000",
315        "UMask": "0x40"
316    },
317    {
318        "BriefDescription": "L2 cache lines evicted.",
319        "EventCode": "0x26",
320        "EventName": "L2_LINES_OUT.SELF.PREFETCH",
321        "SampleAfterValue": "200000",
322        "UMask": "0x50"
323    },
324    {
325        "BriefDescription": "L2 locked accesses",
326        "EventCode": "0x2B",
327        "EventName": "L2_LOCK.SELF.E_STATE",
328        "SampleAfterValue": "200000",
329        "UMask": "0x44"
330    },
331    {
332        "BriefDescription": "L2 locked accesses",
333        "EventCode": "0x2B",
334        "EventName": "L2_LOCK.SELF.I_STATE",
335        "SampleAfterValue": "200000",
336        "UMask": "0x41"
337    },
338    {
339        "BriefDescription": "L2 locked accesses",
340        "EventCode": "0x2B",
341        "EventName": "L2_LOCK.SELF.MESI",
342        "SampleAfterValue": "200000",
343        "UMask": "0x4f"
344    },
345    {
346        "BriefDescription": "L2 locked accesses",
347        "EventCode": "0x2B",
348        "EventName": "L2_LOCK.SELF.M_STATE",
349        "SampleAfterValue": "200000",
350        "UMask": "0x48"
351    },
352    {
353        "BriefDescription": "L2 locked accesses",
354        "EventCode": "0x2B",
355        "EventName": "L2_LOCK.SELF.S_STATE",
356        "SampleAfterValue": "200000",
357        "UMask": "0x42"
358    },
359    {
360        "BriefDescription": "L2 cache line modifications.",
361        "EventCode": "0x25",
362        "EventName": "L2_M_LINES_IN.SELF",
363        "SampleAfterValue": "200000",
364        "UMask": "0x40"
365    },
366    {
367        "BriefDescription": "Modified lines evicted from the L2 cache",
368        "EventCode": "0x27",
369        "EventName": "L2_M_LINES_OUT.SELF.ANY",
370        "SampleAfterValue": "200000",
371        "UMask": "0x70"
372    },
373    {
374        "BriefDescription": "Modified lines evicted from the L2 cache",
375        "EventCode": "0x27",
376        "EventName": "L2_M_LINES_OUT.SELF.DEMAND",
377        "SampleAfterValue": "200000",
378        "UMask": "0x40"
379    },
380    {
381        "BriefDescription": "Modified lines evicted from the L2 cache",
382        "EventCode": "0x27",
383        "EventName": "L2_M_LINES_OUT.SELF.PREFETCH",
384        "SampleAfterValue": "200000",
385        "UMask": "0x50"
386    },
387    {
388        "BriefDescription": "Cycles no L2 cache requests are pending",
389        "EventCode": "0x32",
390        "EventName": "L2_NO_REQ.SELF",
391        "SampleAfterValue": "200000",
392        "UMask": "0x40"
393    },
394    {
395        "BriefDescription": "Rejected L2 cache requests",
396        "EventCode": "0x30",
397        "EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE",
398        "SampleAfterValue": "200000",
399        "UMask": "0x74"
400    },
401    {
402        "BriefDescription": "Rejected L2 cache requests",
403        "EventCode": "0x30",
404        "EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE",
405        "SampleAfterValue": "200000",
406        "UMask": "0x71"
407    },
408    {
409        "BriefDescription": "Rejected L2 cache requests",
410        "EventCode": "0x30",
411        "EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI",
412        "SampleAfterValue": "200000",
413        "UMask": "0x7f"
414    },
415    {
416        "BriefDescription": "Rejected L2 cache requests",
417        "EventCode": "0x30",
418        "EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE",
419        "SampleAfterValue": "200000",
420        "UMask": "0x78"
421    },
422    {
423        "BriefDescription": "Rejected L2 cache requests",
424        "EventCode": "0x30",
425        "EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE",
426        "SampleAfterValue": "200000",
427        "UMask": "0x72"
428    },
429    {
430        "BriefDescription": "Rejected L2 cache requests",
431        "EventCode": "0x30",
432        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE",
433        "SampleAfterValue": "200000",
434        "UMask": "0x44"
435    },
436    {
437        "BriefDescription": "Rejected L2 cache requests",
438        "EventCode": "0x30",
439        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE",
440        "SampleAfterValue": "200000",
441        "UMask": "0x41"
442    },
443    {
444        "BriefDescription": "Rejected L2 cache requests",
445        "EventCode": "0x30",
446        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI",
447        "SampleAfterValue": "200000",
448        "UMask": "0x4f"
449    },
450    {
451        "BriefDescription": "Rejected L2 cache requests",
452        "EventCode": "0x30",
453        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE",
454        "SampleAfterValue": "200000",
455        "UMask": "0x48"
456    },
457    {
458        "BriefDescription": "Rejected L2 cache requests",
459        "EventCode": "0x30",
460        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE",
461        "SampleAfterValue": "200000",
462        "UMask": "0x42"
463    },
464    {
465        "BriefDescription": "Rejected L2 cache requests",
466        "EventCode": "0x30",
467        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE",
468        "SampleAfterValue": "200000",
469        "UMask": "0x54"
470    },
471    {
472        "BriefDescription": "Rejected L2 cache requests",
473        "EventCode": "0x30",
474        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE",
475        "SampleAfterValue": "200000",
476        "UMask": "0x51"
477    },
478    {
479        "BriefDescription": "Rejected L2 cache requests",
480        "EventCode": "0x30",
481        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI",
482        "SampleAfterValue": "200000",
483        "UMask": "0x5f"
484    },
485    {
486        "BriefDescription": "Rejected L2 cache requests",
487        "EventCode": "0x30",
488        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE",
489        "SampleAfterValue": "200000",
490        "UMask": "0x58"
491    },
492    {
493        "BriefDescription": "Rejected L2 cache requests",
494        "EventCode": "0x30",
495        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE",
496        "SampleAfterValue": "200000",
497        "UMask": "0x52"
498    },
499    {
500        "BriefDescription": "L2 cache requests",
501        "EventCode": "0x2E",
502        "EventName": "L2_RQSTS.SELF.ANY.E_STATE",
503        "SampleAfterValue": "200000",
504        "UMask": "0x74"
505    },
506    {
507        "BriefDescription": "L2 cache requests",
508        "EventCode": "0x2E",
509        "EventName": "L2_RQSTS.SELF.ANY.I_STATE",
510        "SampleAfterValue": "200000",
511        "UMask": "0x71"
512    },
513    {
514        "BriefDescription": "L2 cache requests",
515        "EventCode": "0x2E",
516        "EventName": "L2_RQSTS.SELF.ANY.MESI",
517        "SampleAfterValue": "200000",
518        "UMask": "0x7f"
519    },
520    {
521        "BriefDescription": "L2 cache requests",
522        "EventCode": "0x2E",
523        "EventName": "L2_RQSTS.SELF.ANY.M_STATE",
524        "SampleAfterValue": "200000",
525        "UMask": "0x78"
526    },
527    {
528        "BriefDescription": "L2 cache requests",
529        "EventCode": "0x2E",
530        "EventName": "L2_RQSTS.SELF.ANY.S_STATE",
531        "SampleAfterValue": "200000",
532        "UMask": "0x72"
533    },
534    {
535        "BriefDescription": "L2 cache requests",
536        "EventCode": "0x2E",
537        "EventName": "L2_RQSTS.SELF.DEMAND.E_STATE",
538        "SampleAfterValue": "200000",
539        "UMask": "0x44"
540    },
541    {
542        "BriefDescription": "L2 cache demand requests from this core that missed the L2",
543        "EventCode": "0x2E",
544        "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE",
545        "SampleAfterValue": "200000",
546        "UMask": "0x41"
547    },
548    {
549        "BriefDescription": "L2 cache demand requests from this core",
550        "EventCode": "0x2E",
551        "EventName": "L2_RQSTS.SELF.DEMAND.MESI",
552        "SampleAfterValue": "200000",
553        "UMask": "0x4f"
554    },
555    {
556        "BriefDescription": "L2 cache requests",
557        "EventCode": "0x2E",
558        "EventName": "L2_RQSTS.SELF.DEMAND.M_STATE",
559        "SampleAfterValue": "200000",
560        "UMask": "0x48"
561    },
562    {
563        "BriefDescription": "L2 cache requests",
564        "EventCode": "0x2E",
565        "EventName": "L2_RQSTS.SELF.DEMAND.S_STATE",
566        "SampleAfterValue": "200000",
567        "UMask": "0x42"
568    },
569    {
570        "BriefDescription": "L2 cache requests",
571        "EventCode": "0x2E",
572        "EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE",
573        "SampleAfterValue": "200000",
574        "UMask": "0x54"
575    },
576    {
577        "BriefDescription": "L2 cache requests",
578        "EventCode": "0x2E",
579        "EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE",
580        "SampleAfterValue": "200000",
581        "UMask": "0x51"
582    },
583    {
584        "BriefDescription": "L2 cache requests",
585        "EventCode": "0x2E",
586        "EventName": "L2_RQSTS.SELF.PREFETCH.MESI",
587        "SampleAfterValue": "200000",
588        "UMask": "0x5f"
589    },
590    {
591        "BriefDescription": "L2 cache requests",
592        "EventCode": "0x2E",
593        "EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE",
594        "SampleAfterValue": "200000",
595        "UMask": "0x58"
596    },
597    {
598        "BriefDescription": "L2 cache requests",
599        "EventCode": "0x2E",
600        "EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE",
601        "SampleAfterValue": "200000",
602        "UMask": "0x52"
603    },
604    {
605        "BriefDescription": "L2 store requests",
606        "EventCode": "0x2A",
607        "EventName": "L2_ST.SELF.E_STATE",
608        "SampleAfterValue": "200000",
609        "UMask": "0x44"
610    },
611    {
612        "BriefDescription": "L2 store requests",
613        "EventCode": "0x2A",
614        "EventName": "L2_ST.SELF.I_STATE",
615        "SampleAfterValue": "200000",
616        "UMask": "0x41"
617    },
618    {
619        "BriefDescription": "L2 store requests",
620        "EventCode": "0x2A",
621        "EventName": "L2_ST.SELF.MESI",
622        "SampleAfterValue": "200000",
623        "UMask": "0x4f"
624    },
625    {
626        "BriefDescription": "L2 store requests",
627        "EventCode": "0x2A",
628        "EventName": "L2_ST.SELF.M_STATE",
629        "SampleAfterValue": "200000",
630        "UMask": "0x48"
631    },
632    {
633        "BriefDescription": "L2 store requests",
634        "EventCode": "0x2A",
635        "EventName": "L2_ST.SELF.S_STATE",
636        "SampleAfterValue": "200000",
637        "UMask": "0x42"
638    },
639    {
640        "BriefDescription": "Retired loads that hit the L2 cache (precise event).",
641        "EventCode": "0xCB",
642        "EventName": "MEM_LOAD_RETIRED.L2_HIT",
643        "SampleAfterValue": "200000",
644        "UMask": "0x1"
645    },
646    {
647        "BriefDescription": "Retired loads that miss the L2 cache",
648        "EventCode": "0xCB",
649        "EventName": "MEM_LOAD_RETIRED.L2_MISS",
650        "SampleAfterValue": "10000",
651        "UMask": "0x2"
652    }
653]
654