xref: /linux/tools/perf/pmu-events/arch/x86/bonnell/cache.json (revision 4359a011e259a4608afc7fb3635370c9d4ba5943) 
1[
2    {
3        "BriefDescription": "L1 Data Cacheable reads and writes",
4        "Counter": "0,1",
5        "EventCode": "0x40",
6        "EventName": "L1D_CACHE.ALL_CACHE_REF",
7        "SampleAfterValue": "2000000",
8        "UMask": "0xa3"
9    },
10    {
11        "BriefDescription": "L1 Data reads and writes",
12        "Counter": "0,1",
13        "EventCode": "0x40",
14        "EventName": "L1D_CACHE.ALL_REF",
15        "SampleAfterValue": "2000000",
16        "UMask": "0x83"
17    },
18    {
19        "BriefDescription": "Modified cache lines evicted from the L1 data cache",
20        "Counter": "0,1",
21        "EventCode": "0x40",
22        "EventName": "L1D_CACHE.EVICT",
23        "SampleAfterValue": "200000",
24        "UMask": "0x10"
25    },
26    {
27        "BriefDescription": "L1 Cacheable Data Reads",
28        "Counter": "0,1",
29        "EventCode": "0x40",
30        "EventName": "L1D_CACHE.LD",
31        "SampleAfterValue": "2000000",
32        "UMask": "0xa1"
33    },
34    {
35        "BriefDescription": "L1 Data line replacements",
36        "Counter": "0,1",
37        "EventCode": "0x40",
38        "EventName": "L1D_CACHE.REPL",
39        "SampleAfterValue": "200000",
40        "UMask": "0x8"
41    },
42    {
43        "BriefDescription": "Modified cache lines allocated in the L1 data cache",
44        "Counter": "0,1",
45        "EventCode": "0x40",
46        "EventName": "L1D_CACHE.REPLM",
47        "SampleAfterValue": "200000",
48        "UMask": "0x48"
49    },
50    {
51        "BriefDescription": "L1 Cacheable Data Writes",
52        "Counter": "0,1",
53        "EventCode": "0x40",
54        "EventName": "L1D_CACHE.ST",
55        "SampleAfterValue": "2000000",
56        "UMask": "0xa2"
57    },
58    {
59        "BriefDescription": "Cycles L2 address bus is in use.",
60        "Counter": "0,1",
61        "EventCode": "0x21",
62        "EventName": "L2_ADS.SELF",
63        "SampleAfterValue": "200000",
64        "UMask": "0x40"
65    },
66    {
67        "BriefDescription": "All data requests from the L1 data cache",
68        "Counter": "0,1",
69        "EventCode": "0x2C",
70        "EventName": "L2_DATA_RQSTS.SELF.E_STATE",
71        "SampleAfterValue": "200000",
72        "UMask": "0x44"
73    },
74    {
75        "BriefDescription": "All data requests from the L1 data cache",
76        "Counter": "0,1",
77        "EventCode": "0x2C",
78        "EventName": "L2_DATA_RQSTS.SELF.I_STATE",
79        "SampleAfterValue": "200000",
80        "UMask": "0x41"
81    },
82    {
83        "BriefDescription": "All data requests from the L1 data cache",
84        "Counter": "0,1",
85        "EventCode": "0x2C",
86        "EventName": "L2_DATA_RQSTS.SELF.MESI",
87        "SampleAfterValue": "200000",
88        "UMask": "0x4f"
89    },
90    {
91        "BriefDescription": "All data requests from the L1 data cache",
92        "Counter": "0,1",
93        "EventCode": "0x2C",
94        "EventName": "L2_DATA_RQSTS.SELF.M_STATE",
95        "SampleAfterValue": "200000",
96        "UMask": "0x48"
97    },
98    {
99        "BriefDescription": "All data requests from the L1 data cache",
100        "Counter": "0,1",
101        "EventCode": "0x2C",
102        "EventName": "L2_DATA_RQSTS.SELF.S_STATE",
103        "SampleAfterValue": "200000",
104        "UMask": "0x42"
105    },
106    {
107        "BriefDescription": "Cycles the L2 cache data bus is busy.",
108        "Counter": "0,1",
109        "EventCode": "0x22",
110        "EventName": "L2_DBUS_BUSY.SELF",
111        "SampleAfterValue": "200000",
112        "UMask": "0x40"
113    },
114    {
115        "BriefDescription": "Cycles the L2 transfers data to the core.",
116        "Counter": "0,1",
117        "EventCode": "0x23",
118        "EventName": "L2_DBUS_BUSY_RD.SELF",
119        "SampleAfterValue": "200000",
120        "UMask": "0x40"
121    },
122    {
123        "BriefDescription": "L2 cacheable instruction fetch requests",
124        "Counter": "0,1",
125        "EventCode": "0x28",
126        "EventName": "L2_IFETCH.SELF.E_STATE",
127        "SampleAfterValue": "200000",
128        "UMask": "0x44"
129    },
130    {
131        "BriefDescription": "L2 cacheable instruction fetch requests",
132        "Counter": "0,1",
133        "EventCode": "0x28",
134        "EventName": "L2_IFETCH.SELF.I_STATE",
135        "SampleAfterValue": "200000",
136        "UMask": "0x41"
137    },
138    {
139        "BriefDescription": "L2 cacheable instruction fetch requests",
140        "Counter": "0,1",
141        "EventCode": "0x28",
142        "EventName": "L2_IFETCH.SELF.MESI",
143        "SampleAfterValue": "200000",
144        "UMask": "0x4f"
145    },
146    {
147        "BriefDescription": "L2 cacheable instruction fetch requests",
148        "Counter": "0,1",
149        "EventCode": "0x28",
150        "EventName": "L2_IFETCH.SELF.M_STATE",
151        "SampleAfterValue": "200000",
152        "UMask": "0x48"
153    },
154    {
155        "BriefDescription": "L2 cacheable instruction fetch requests",
156        "Counter": "0,1",
157        "EventCode": "0x28",
158        "EventName": "L2_IFETCH.SELF.S_STATE",
159        "SampleAfterValue": "200000",
160        "UMask": "0x42"
161    },
162    {
163        "BriefDescription": "L2 cache reads",
164        "Counter": "0,1",
165        "EventCode": "0x29",
166        "EventName": "L2_LD.SELF.ANY.E_STATE",
167        "SampleAfterValue": "200000",
168        "UMask": "0x74"
169    },
170    {
171        "BriefDescription": "L2 cache reads",
172        "Counter": "0,1",
173        "EventCode": "0x29",
174        "EventName": "L2_LD.SELF.ANY.I_STATE",
175        "SampleAfterValue": "200000",
176        "UMask": "0x71"
177    },
178    {
179        "BriefDescription": "L2 cache reads",
180        "Counter": "0,1",
181        "EventCode": "0x29",
182        "EventName": "L2_LD.SELF.ANY.MESI",
183        "SampleAfterValue": "200000",
184        "UMask": "0x7f"
185    },
186    {
187        "BriefDescription": "L2 cache reads",
188        "Counter": "0,1",
189        "EventCode": "0x29",
190        "EventName": "L2_LD.SELF.ANY.M_STATE",
191        "SampleAfterValue": "200000",
192        "UMask": "0x78"
193    },
194    {
195        "BriefDescription": "L2 cache reads",
196        "Counter": "0,1",
197        "EventCode": "0x29",
198        "EventName": "L2_LD.SELF.ANY.S_STATE",
199        "SampleAfterValue": "200000",
200        "UMask": "0x72"
201    },
202    {
203        "BriefDescription": "L2 cache reads",
204        "Counter": "0,1",
205        "EventCode": "0x29",
206        "EventName": "L2_LD.SELF.DEMAND.E_STATE",
207        "SampleAfterValue": "200000",
208        "UMask": "0x44"
209    },
210    {
211        "BriefDescription": "L2 cache reads",
212        "Counter": "0,1",
213        "EventCode": "0x29",
214        "EventName": "L2_LD.SELF.DEMAND.I_STATE",
215        "SampleAfterValue": "200000",
216        "UMask": "0x41"
217    },
218    {
219        "BriefDescription": "L2 cache reads",
220        "Counter": "0,1",
221        "EventCode": "0x29",
222        "EventName": "L2_LD.SELF.DEMAND.MESI",
223        "SampleAfterValue": "200000",
224        "UMask": "0x4f"
225    },
226    {
227        "BriefDescription": "L2 cache reads",
228        "Counter": "0,1",
229        "EventCode": "0x29",
230        "EventName": "L2_LD.SELF.DEMAND.M_STATE",
231        "SampleAfterValue": "200000",
232        "UMask": "0x48"
233    },
234    {
235        "BriefDescription": "L2 cache reads",
236        "Counter": "0,1",
237        "EventCode": "0x29",
238        "EventName": "L2_LD.SELF.DEMAND.S_STATE",
239        "SampleAfterValue": "200000",
240        "UMask": "0x42"
241    },
242    {
243        "BriefDescription": "L2 cache reads",
244        "Counter": "0,1",
245        "EventCode": "0x29",
246        "EventName": "L2_LD.SELF.PREFETCH.E_STATE",
247        "SampleAfterValue": "200000",
248        "UMask": "0x54"
249    },
250    {
251        "BriefDescription": "L2 cache reads",
252        "Counter": "0,1",
253        "EventCode": "0x29",
254        "EventName": "L2_LD.SELF.PREFETCH.I_STATE",
255        "SampleAfterValue": "200000",
256        "UMask": "0x51"
257    },
258    {
259        "BriefDescription": "L2 cache reads",
260        "Counter": "0,1",
261        "EventCode": "0x29",
262        "EventName": "L2_LD.SELF.PREFETCH.MESI",
263        "SampleAfterValue": "200000",
264        "UMask": "0x5f"
265    },
266    {
267        "BriefDescription": "L2 cache reads",
268        "Counter": "0,1",
269        "EventCode": "0x29",
270        "EventName": "L2_LD.SELF.PREFETCH.M_STATE",
271        "SampleAfterValue": "200000",
272        "UMask": "0x58"
273    },
274    {
275        "BriefDescription": "L2 cache reads",
276        "Counter": "0,1",
277        "EventCode": "0x29",
278        "EventName": "L2_LD.SELF.PREFETCH.S_STATE",
279        "SampleAfterValue": "200000",
280        "UMask": "0x52"
281    },
282    {
283        "BriefDescription": "All read requests from L1 instruction and data caches",
284        "Counter": "0,1",
285        "EventCode": "0x2D",
286        "EventName": "L2_LD_IFETCH.SELF.E_STATE",
287        "SampleAfterValue": "200000",
288        "UMask": "0x44"
289    },
290    {
291        "BriefDescription": "All read requests from L1 instruction and data caches",
292        "Counter": "0,1",
293        "EventCode": "0x2D",
294        "EventName": "L2_LD_IFETCH.SELF.I_STATE",
295        "SampleAfterValue": "200000",
296        "UMask": "0x41"
297    },
298    {
299        "BriefDescription": "All read requests from L1 instruction and data caches",
300        "Counter": "0,1",
301        "EventCode": "0x2D",
302        "EventName": "L2_LD_IFETCH.SELF.MESI",
303        "SampleAfterValue": "200000",
304        "UMask": "0x4f"
305    },
306    {
307        "BriefDescription": "All read requests from L1 instruction and data caches",
308        "Counter": "0,1",
309        "EventCode": "0x2D",
310        "EventName": "L2_LD_IFETCH.SELF.M_STATE",
311        "SampleAfterValue": "200000",
312        "UMask": "0x48"
313    },
314    {
315        "BriefDescription": "All read requests from L1 instruction and data caches",
316        "Counter": "0,1",
317        "EventCode": "0x2D",
318        "EventName": "L2_LD_IFETCH.SELF.S_STATE",
319        "SampleAfterValue": "200000",
320        "UMask": "0x42"
321    },
322    {
323        "BriefDescription": "L2 cache misses.",
324        "Counter": "0,1",
325        "EventCode": "0x24",
326        "EventName": "L2_LINES_IN.SELF.ANY",
327        "SampleAfterValue": "200000",
328        "UMask": "0x70"
329    },
330    {
331        "BriefDescription": "L2 cache misses.",
332        "Counter": "0,1",
333        "EventCode": "0x24",
334        "EventName": "L2_LINES_IN.SELF.DEMAND",
335        "SampleAfterValue": "200000",
336        "UMask": "0x40"
337    },
338    {
339        "BriefDescription": "L2 cache misses.",
340        "Counter": "0,1",
341        "EventCode": "0x24",
342        "EventName": "L2_LINES_IN.SELF.PREFETCH",
343        "SampleAfterValue": "200000",
344        "UMask": "0x50"
345    },
346    {
347        "BriefDescription": "L2 cache lines evicted.",
348        "Counter": "0,1",
349        "EventCode": "0x26",
350        "EventName": "L2_LINES_OUT.SELF.ANY",
351        "SampleAfterValue": "200000",
352        "UMask": "0x70"
353    },
354    {
355        "BriefDescription": "L2 cache lines evicted.",
356        "Counter": "0,1",
357        "EventCode": "0x26",
358        "EventName": "L2_LINES_OUT.SELF.DEMAND",
359        "SampleAfterValue": "200000",
360        "UMask": "0x40"
361    },
362    {
363        "BriefDescription": "L2 cache lines evicted.",
364        "Counter": "0,1",
365        "EventCode": "0x26",
366        "EventName": "L2_LINES_OUT.SELF.PREFETCH",
367        "SampleAfterValue": "200000",
368        "UMask": "0x50"
369    },
370    {
371        "BriefDescription": "L2 locked accesses",
372        "Counter": "0,1",
373        "EventCode": "0x2B",
374        "EventName": "L2_LOCK.SELF.E_STATE",
375        "SampleAfterValue": "200000",
376        "UMask": "0x44"
377    },
378    {
379        "BriefDescription": "L2 locked accesses",
380        "Counter": "0,1",
381        "EventCode": "0x2B",
382        "EventName": "L2_LOCK.SELF.I_STATE",
383        "SampleAfterValue": "200000",
384        "UMask": "0x41"
385    },
386    {
387        "BriefDescription": "L2 locked accesses",
388        "Counter": "0,1",
389        "EventCode": "0x2B",
390        "EventName": "L2_LOCK.SELF.MESI",
391        "SampleAfterValue": "200000",
392        "UMask": "0x4f"
393    },
394    {
395        "BriefDescription": "L2 locked accesses",
396        "Counter": "0,1",
397        "EventCode": "0x2B",
398        "EventName": "L2_LOCK.SELF.M_STATE",
399        "SampleAfterValue": "200000",
400        "UMask": "0x48"
401    },
402    {
403        "BriefDescription": "L2 locked accesses",
404        "Counter": "0,1",
405        "EventCode": "0x2B",
406        "EventName": "L2_LOCK.SELF.S_STATE",
407        "SampleAfterValue": "200000",
408        "UMask": "0x42"
409    },
410    {
411        "BriefDescription": "L2 cache line modifications.",
412        "Counter": "0,1",
413        "EventCode": "0x25",
414        "EventName": "L2_M_LINES_IN.SELF",
415        "SampleAfterValue": "200000",
416        "UMask": "0x40"
417    },
418    {
419        "BriefDescription": "Modified lines evicted from the L2 cache",
420        "Counter": "0,1",
421        "EventCode": "0x27",
422        "EventName": "L2_M_LINES_OUT.SELF.ANY",
423        "SampleAfterValue": "200000",
424        "UMask": "0x70"
425    },
426    {
427        "BriefDescription": "Modified lines evicted from the L2 cache",
428        "Counter": "0,1",
429        "EventCode": "0x27",
430        "EventName": "L2_M_LINES_OUT.SELF.DEMAND",
431        "SampleAfterValue": "200000",
432        "UMask": "0x40"
433    },
434    {
435        "BriefDescription": "Modified lines evicted from the L2 cache",
436        "Counter": "0,1",
437        "EventCode": "0x27",
438        "EventName": "L2_M_LINES_OUT.SELF.PREFETCH",
439        "SampleAfterValue": "200000",
440        "UMask": "0x50"
441    },
442    {
443        "BriefDescription": "Cycles no L2 cache requests are pending",
444        "Counter": "0,1",
445        "EventCode": "0x32",
446        "EventName": "L2_NO_REQ.SELF",
447        "SampleAfterValue": "200000",
448        "UMask": "0x40"
449    },
450    {
451        "BriefDescription": "Rejected L2 cache requests",
452        "Counter": "0,1",
453        "EventCode": "0x30",
454        "EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE",
455        "SampleAfterValue": "200000",
456        "UMask": "0x74"
457    },
458    {
459        "BriefDescription": "Rejected L2 cache requests",
460        "Counter": "0,1",
461        "EventCode": "0x30",
462        "EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE",
463        "SampleAfterValue": "200000",
464        "UMask": "0x71"
465    },
466    {
467        "BriefDescription": "Rejected L2 cache requests",
468        "Counter": "0,1",
469        "EventCode": "0x30",
470        "EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI",
471        "SampleAfterValue": "200000",
472        "UMask": "0x7f"
473    },
474    {
475        "BriefDescription": "Rejected L2 cache requests",
476        "Counter": "0,1",
477        "EventCode": "0x30",
478        "EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE",
479        "SampleAfterValue": "200000",
480        "UMask": "0x78"
481    },
482    {
483        "BriefDescription": "Rejected L2 cache requests",
484        "Counter": "0,1",
485        "EventCode": "0x30",
486        "EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE",
487        "SampleAfterValue": "200000",
488        "UMask": "0x72"
489    },
490    {
491        "BriefDescription": "Rejected L2 cache requests",
492        "Counter": "0,1",
493        "EventCode": "0x30",
494        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE",
495        "SampleAfterValue": "200000",
496        "UMask": "0x44"
497    },
498    {
499        "BriefDescription": "Rejected L2 cache requests",
500        "Counter": "0,1",
501        "EventCode": "0x30",
502        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE",
503        "SampleAfterValue": "200000",
504        "UMask": "0x41"
505    },
506    {
507        "BriefDescription": "Rejected L2 cache requests",
508        "Counter": "0,1",
509        "EventCode": "0x30",
510        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI",
511        "SampleAfterValue": "200000",
512        "UMask": "0x4f"
513    },
514    {
515        "BriefDescription": "Rejected L2 cache requests",
516        "Counter": "0,1",
517        "EventCode": "0x30",
518        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE",
519        "SampleAfterValue": "200000",
520        "UMask": "0x48"
521    },
522    {
523        "BriefDescription": "Rejected L2 cache requests",
524        "Counter": "0,1",
525        "EventCode": "0x30",
526        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE",
527        "SampleAfterValue": "200000",
528        "UMask": "0x42"
529    },
530    {
531        "BriefDescription": "Rejected L2 cache requests",
532        "Counter": "0,1",
533        "EventCode": "0x30",
534        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE",
535        "SampleAfterValue": "200000",
536        "UMask": "0x54"
537    },
538    {
539        "BriefDescription": "Rejected L2 cache requests",
540        "Counter": "0,1",
541        "EventCode": "0x30",
542        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE",
543        "SampleAfterValue": "200000",
544        "UMask": "0x51"
545    },
546    {
547        "BriefDescription": "Rejected L2 cache requests",
548        "Counter": "0,1",
549        "EventCode": "0x30",
550        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI",
551        "SampleAfterValue": "200000",
552        "UMask": "0x5f"
553    },
554    {
555        "BriefDescription": "Rejected L2 cache requests",
556        "Counter": "0,1",
557        "EventCode": "0x30",
558        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE",
559        "SampleAfterValue": "200000",
560        "UMask": "0x58"
561    },
562    {
563        "BriefDescription": "Rejected L2 cache requests",
564        "Counter": "0,1",
565        "EventCode": "0x30",
566        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE",
567        "SampleAfterValue": "200000",
568        "UMask": "0x52"
569    },
570    {
571        "BriefDescription": "L2 cache requests",
572        "Counter": "0,1",
573        "EventCode": "0x2E",
574        "EventName": "L2_RQSTS.SELF.ANY.E_STATE",
575        "SampleAfterValue": "200000",
576        "UMask": "0x74"
577    },
578    {
579        "BriefDescription": "L2 cache requests",
580        "Counter": "0,1",
581        "EventCode": "0x2E",
582        "EventName": "L2_RQSTS.SELF.ANY.I_STATE",
583        "SampleAfterValue": "200000",
584        "UMask": "0x71"
585    },
586    {
587        "BriefDescription": "L2 cache requests",
588        "Counter": "0,1",
589        "EventCode": "0x2E",
590        "EventName": "L2_RQSTS.SELF.ANY.MESI",
591        "SampleAfterValue": "200000",
592        "UMask": "0x7f"
593    },
594    {
595        "BriefDescription": "L2 cache requests",
596        "Counter": "0,1",
597        "EventCode": "0x2E",
598        "EventName": "L2_RQSTS.SELF.ANY.M_STATE",
599        "SampleAfterValue": "200000",
600        "UMask": "0x78"
601    },
602    {
603        "BriefDescription": "L2 cache requests",
604        "Counter": "0,1",
605        "EventCode": "0x2E",
606        "EventName": "L2_RQSTS.SELF.ANY.S_STATE",
607        "SampleAfterValue": "200000",
608        "UMask": "0x72"
609    },
610    {
611        "BriefDescription": "L2 cache requests",
612        "Counter": "0,1",
613        "EventCode": "0x2E",
614        "EventName": "L2_RQSTS.SELF.DEMAND.E_STATE",
615        "SampleAfterValue": "200000",
616        "UMask": "0x44"
617    },
618    {
619        "BriefDescription": "L2 cache demand requests from this core that missed the L2",
620        "Counter": "0,1",
621        "EventCode": "0x2E",
622        "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE",
623        "SampleAfterValue": "200000",
624        "UMask": "0x41"
625    },
626    {
627        "BriefDescription": "L2 cache demand requests from this core",
628        "Counter": "0,1",
629        "EventCode": "0x2E",
630        "EventName": "L2_RQSTS.SELF.DEMAND.MESI",
631        "SampleAfterValue": "200000",
632        "UMask": "0x4f"
633    },
634    {
635        "BriefDescription": "L2 cache requests",
636        "Counter": "0,1",
637        "EventCode": "0x2E",
638        "EventName": "L2_RQSTS.SELF.DEMAND.M_STATE",
639        "SampleAfterValue": "200000",
640        "UMask": "0x48"
641    },
642    {
643        "BriefDescription": "L2 cache requests",
644        "Counter": "0,1",
645        "EventCode": "0x2E",
646        "EventName": "L2_RQSTS.SELF.DEMAND.S_STATE",
647        "SampleAfterValue": "200000",
648        "UMask": "0x42"
649    },
650    {
651        "BriefDescription": "L2 cache requests",
652        "Counter": "0,1",
653        "EventCode": "0x2E",
654        "EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE",
655        "SampleAfterValue": "200000",
656        "UMask": "0x54"
657    },
658    {
659        "BriefDescription": "L2 cache requests",
660        "Counter": "0,1",
661        "EventCode": "0x2E",
662        "EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE",
663        "SampleAfterValue": "200000",
664        "UMask": "0x51"
665    },
666    {
667        "BriefDescription": "L2 cache requests",
668        "Counter": "0,1",
669        "EventCode": "0x2E",
670        "EventName": "L2_RQSTS.SELF.PREFETCH.MESI",
671        "SampleAfterValue": "200000",
672        "UMask": "0x5f"
673    },
674    {
675        "BriefDescription": "L2 cache requests",
676        "Counter": "0,1",
677        "EventCode": "0x2E",
678        "EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE",
679        "SampleAfterValue": "200000",
680        "UMask": "0x58"
681    },
682    {
683        "BriefDescription": "L2 cache requests",
684        "Counter": "0,1",
685        "EventCode": "0x2E",
686        "EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE",
687        "SampleAfterValue": "200000",
688        "UMask": "0x52"
689    },
690    {
691        "BriefDescription": "L2 store requests",
692        "Counter": "0,1",
693        "EventCode": "0x2A",
694        "EventName": "L2_ST.SELF.E_STATE",
695        "SampleAfterValue": "200000",
696        "UMask": "0x44"
697    },
698    {
699        "BriefDescription": "L2 store requests",
700        "Counter": "0,1",
701        "EventCode": "0x2A",
702        "EventName": "L2_ST.SELF.I_STATE",
703        "SampleAfterValue": "200000",
704        "UMask": "0x41"
705    },
706    {
707        "BriefDescription": "L2 store requests",
708        "Counter": "0,1",
709        "EventCode": "0x2A",
710        "EventName": "L2_ST.SELF.MESI",
711        "SampleAfterValue": "200000",
712        "UMask": "0x4f"
713    },
714    {
715        "BriefDescription": "L2 store requests",
716        "Counter": "0,1",
717        "EventCode": "0x2A",
718        "EventName": "L2_ST.SELF.M_STATE",
719        "SampleAfterValue": "200000",
720        "UMask": "0x48"
721    },
722    {
723        "BriefDescription": "L2 store requests",
724        "Counter": "0,1",
725        "EventCode": "0x2A",
726        "EventName": "L2_ST.SELF.S_STATE",
727        "SampleAfterValue": "200000",
728        "UMask": "0x42"
729    },
730    {
731        "BriefDescription": "Retired loads that hit the L2 cache (precise event).",
732        "Counter": "0,1",
733        "EventCode": "0xCB",
734        "EventName": "MEM_LOAD_RETIRED.L2_HIT",
735        "SampleAfterValue": "200000",
736        "UMask": "0x1"
737    },
738    {
739        "BriefDescription": "Retired loads that miss the L2 cache",
740        "Counter": "0,1",
741        "EventCode": "0xCB",
742        "EventName": "MEM_LOAD_RETIRED.L2_MISS",
743        "SampleAfterValue": "10000",
744        "UMask": "0x2"
745    }
746]
747