xref: /linux/tools/perf/pmu-events/arch/x86/bonnell/cache.json (revision 26fbb4c8c7c3ee9a4c3b4de555a8587b5a19154e) 
1[
2    {
3        "EventCode": "0x21",
4        "Counter": "0,1",
5        "UMask": "0x40",
6        "EventName": "L2_ADS.SELF",
7        "SampleAfterValue": "200000",
8        "BriefDescription": "Cycles L2 address bus is in use."
9    },
10    {
11        "EventCode": "0x22",
12        "Counter": "0,1",
13        "UMask": "0x40",
14        "EventName": "L2_DBUS_BUSY.SELF",
15        "SampleAfterValue": "200000",
16        "BriefDescription": "Cycles the L2 cache data bus is busy."
17    },
18    {
19        "EventCode": "0x23",
20        "Counter": "0,1",
21        "UMask": "0x40",
22        "EventName": "L2_DBUS_BUSY_RD.SELF",
23        "SampleAfterValue": "200000",
24        "BriefDescription": "Cycles the L2 transfers data to the core."
25    },
26    {
27        "EventCode": "0x24",
28        "Counter": "0,1",
29        "UMask": "0x70",
30        "EventName": "L2_LINES_IN.SELF.ANY",
31        "SampleAfterValue": "200000",
32        "BriefDescription": "L2 cache misses."
33    },
34    {
35        "EventCode": "0x24",
36        "Counter": "0,1",
37        "UMask": "0x40",
38        "EventName": "L2_LINES_IN.SELF.DEMAND",
39        "SampleAfterValue": "200000",
40        "BriefDescription": "L2 cache misses."
41    },
42    {
43        "EventCode": "0x24",
44        "Counter": "0,1",
45        "UMask": "0x50",
46        "EventName": "L2_LINES_IN.SELF.PREFETCH",
47        "SampleAfterValue": "200000",
48        "BriefDescription": "L2 cache misses."
49    },
50    {
51        "EventCode": "0x25",
52        "Counter": "0,1",
53        "UMask": "0x40",
54        "EventName": "L2_M_LINES_IN.SELF",
55        "SampleAfterValue": "200000",
56        "BriefDescription": "L2 cache line modifications."
57    },
58    {
59        "EventCode": "0x26",
60        "Counter": "0,1",
61        "UMask": "0x70",
62        "EventName": "L2_LINES_OUT.SELF.ANY",
63        "SampleAfterValue": "200000",
64        "BriefDescription": "L2 cache lines evicted."
65    },
66    {
67        "EventCode": "0x26",
68        "Counter": "0,1",
69        "UMask": "0x40",
70        "EventName": "L2_LINES_OUT.SELF.DEMAND",
71        "SampleAfterValue": "200000",
72        "BriefDescription": "L2 cache lines evicted."
73    },
74    {
75        "EventCode": "0x26",
76        "Counter": "0,1",
77        "UMask": "0x50",
78        "EventName": "L2_LINES_OUT.SELF.PREFETCH",
79        "SampleAfterValue": "200000",
80        "BriefDescription": "L2 cache lines evicted."
81    },
82    {
83        "EventCode": "0x27",
84        "Counter": "0,1",
85        "UMask": "0x70",
86        "EventName": "L2_M_LINES_OUT.SELF.ANY",
87        "SampleAfterValue": "200000",
88        "BriefDescription": "Modified lines evicted from the L2 cache"
89    },
90    {
91        "EventCode": "0x27",
92        "Counter": "0,1",
93        "UMask": "0x40",
94        "EventName": "L2_M_LINES_OUT.SELF.DEMAND",
95        "SampleAfterValue": "200000",
96        "BriefDescription": "Modified lines evicted from the L2 cache"
97    },
98    {
99        "EventCode": "0x27",
100        "Counter": "0,1",
101        "UMask": "0x50",
102        "EventName": "L2_M_LINES_OUT.SELF.PREFETCH",
103        "SampleAfterValue": "200000",
104        "BriefDescription": "Modified lines evicted from the L2 cache"
105    },
106    {
107        "EventCode": "0x28",
108        "Counter": "0,1",
109        "UMask": "0x44",
110        "EventName": "L2_IFETCH.SELF.E_STATE",
111        "SampleAfterValue": "200000",
112        "BriefDescription": "L2 cacheable instruction fetch requests"
113    },
114    {
115        "EventCode": "0x28",
116        "Counter": "0,1",
117        "UMask": "0x41",
118        "EventName": "L2_IFETCH.SELF.I_STATE",
119        "SampleAfterValue": "200000",
120        "BriefDescription": "L2 cacheable instruction fetch requests"
121    },
122    {
123        "EventCode": "0x28",
124        "Counter": "0,1",
125        "UMask": "0x48",
126        "EventName": "L2_IFETCH.SELF.M_STATE",
127        "SampleAfterValue": "200000",
128        "BriefDescription": "L2 cacheable instruction fetch requests"
129    },
130    {
131        "EventCode": "0x28",
132        "Counter": "0,1",
133        "UMask": "0x42",
134        "EventName": "L2_IFETCH.SELF.S_STATE",
135        "SampleAfterValue": "200000",
136        "BriefDescription": "L2 cacheable instruction fetch requests"
137    },
138    {
139        "EventCode": "0x28",
140        "Counter": "0,1",
141        "UMask": "0x4f",
142        "EventName": "L2_IFETCH.SELF.MESI",
143        "SampleAfterValue": "200000",
144        "BriefDescription": "L2 cacheable instruction fetch requests"
145    },
146    {
147        "EventCode": "0x29",
148        "Counter": "0,1",
149        "UMask": "0x74",
150        "EventName": "L2_LD.SELF.ANY.E_STATE",
151        "SampleAfterValue": "200000",
152        "BriefDescription": "L2 cache reads"
153    },
154    {
155        "EventCode": "0x29",
156        "Counter": "0,1",
157        "UMask": "0x71",
158        "EventName": "L2_LD.SELF.ANY.I_STATE",
159        "SampleAfterValue": "200000",
160        "BriefDescription": "L2 cache reads"
161    },
162    {
163        "EventCode": "0x29",
164        "Counter": "0,1",
165        "UMask": "0x78",
166        "EventName": "L2_LD.SELF.ANY.M_STATE",
167        "SampleAfterValue": "200000",
168        "BriefDescription": "L2 cache reads"
169    },
170    {
171        "EventCode": "0x29",
172        "Counter": "0,1",
173        "UMask": "0x72",
174        "EventName": "L2_LD.SELF.ANY.S_STATE",
175        "SampleAfterValue": "200000",
176        "BriefDescription": "L2 cache reads"
177    },
178    {
179        "EventCode": "0x29",
180        "Counter": "0,1",
181        "UMask": "0x7f",
182        "EventName": "L2_LD.SELF.ANY.MESI",
183        "SampleAfterValue": "200000",
184        "BriefDescription": "L2 cache reads"
185    },
186    {
187        "EventCode": "0x29",
188        "Counter": "0,1",
189        "UMask": "0x44",
190        "EventName": "L2_LD.SELF.DEMAND.E_STATE",
191        "SampleAfterValue": "200000",
192        "BriefDescription": "L2 cache reads"
193    },
194    {
195        "EventCode": "0x29",
196        "Counter": "0,1",
197        "UMask": "0x41",
198        "EventName": "L2_LD.SELF.DEMAND.I_STATE",
199        "SampleAfterValue": "200000",
200        "BriefDescription": "L2 cache reads"
201    },
202    {
203        "EventCode": "0x29",
204        "Counter": "0,1",
205        "UMask": "0x48",
206        "EventName": "L2_LD.SELF.DEMAND.M_STATE",
207        "SampleAfterValue": "200000",
208        "BriefDescription": "L2 cache reads"
209    },
210    {
211        "EventCode": "0x29",
212        "Counter": "0,1",
213        "UMask": "0x42",
214        "EventName": "L2_LD.SELF.DEMAND.S_STATE",
215        "SampleAfterValue": "200000",
216        "BriefDescription": "L2 cache reads"
217    },
218    {
219        "EventCode": "0x29",
220        "Counter": "0,1",
221        "UMask": "0x4f",
222        "EventName": "L2_LD.SELF.DEMAND.MESI",
223        "SampleAfterValue": "200000",
224        "BriefDescription": "L2 cache reads"
225    },
226    {
227        "EventCode": "0x29",
228        "Counter": "0,1",
229        "UMask": "0x54",
230        "EventName": "L2_LD.SELF.PREFETCH.E_STATE",
231        "SampleAfterValue": "200000",
232        "BriefDescription": "L2 cache reads"
233    },
234    {
235        "EventCode": "0x29",
236        "Counter": "0,1",
237        "UMask": "0x51",
238        "EventName": "L2_LD.SELF.PREFETCH.I_STATE",
239        "SampleAfterValue": "200000",
240        "BriefDescription": "L2 cache reads"
241    },
242    {
243        "EventCode": "0x29",
244        "Counter": "0,1",
245        "UMask": "0x58",
246        "EventName": "L2_LD.SELF.PREFETCH.M_STATE",
247        "SampleAfterValue": "200000",
248        "BriefDescription": "L2 cache reads"
249    },
250    {
251        "EventCode": "0x29",
252        "Counter": "0,1",
253        "UMask": "0x52",
254        "EventName": "L2_LD.SELF.PREFETCH.S_STATE",
255        "SampleAfterValue": "200000",
256        "BriefDescription": "L2 cache reads"
257    },
258    {
259        "EventCode": "0x29",
260        "Counter": "0,1",
261        "UMask": "0x5f",
262        "EventName": "L2_LD.SELF.PREFETCH.MESI",
263        "SampleAfterValue": "200000",
264        "BriefDescription": "L2 cache reads"
265    },
266    {
267        "EventCode": "0x2A",
268        "Counter": "0,1",
269        "UMask": "0x44",
270        "EventName": "L2_ST.SELF.E_STATE",
271        "SampleAfterValue": "200000",
272        "BriefDescription": "L2 store requests"
273    },
274    {
275        "EventCode": "0x2A",
276        "Counter": "0,1",
277        "UMask": "0x41",
278        "EventName": "L2_ST.SELF.I_STATE",
279        "SampleAfterValue": "200000",
280        "BriefDescription": "L2 store requests"
281    },
282    {
283        "EventCode": "0x2A",
284        "Counter": "0,1",
285        "UMask": "0x48",
286        "EventName": "L2_ST.SELF.M_STATE",
287        "SampleAfterValue": "200000",
288        "BriefDescription": "L2 store requests"
289    },
290    {
291        "EventCode": "0x2A",
292        "Counter": "0,1",
293        "UMask": "0x42",
294        "EventName": "L2_ST.SELF.S_STATE",
295        "SampleAfterValue": "200000",
296        "BriefDescription": "L2 store requests"
297    },
298    {
299        "EventCode": "0x2A",
300        "Counter": "0,1",
301        "UMask": "0x4f",
302        "EventName": "L2_ST.SELF.MESI",
303        "SampleAfterValue": "200000",
304        "BriefDescription": "L2 store requests"
305    },
306    {
307        "EventCode": "0x2B",
308        "Counter": "0,1",
309        "UMask": "0x44",
310        "EventName": "L2_LOCK.SELF.E_STATE",
311        "SampleAfterValue": "200000",
312        "BriefDescription": "L2 locked accesses"
313    },
314    {
315        "EventCode": "0x2B",
316        "Counter": "0,1",
317        "UMask": "0x41",
318        "EventName": "L2_LOCK.SELF.I_STATE",
319        "SampleAfterValue": "200000",
320        "BriefDescription": "L2 locked accesses"
321    },
322    {
323        "EventCode": "0x2B",
324        "Counter": "0,1",
325        "UMask": "0x48",
326        "EventName": "L2_LOCK.SELF.M_STATE",
327        "SampleAfterValue": "200000",
328        "BriefDescription": "L2 locked accesses"
329    },
330    {
331        "EventCode": "0x2B",
332        "Counter": "0,1",
333        "UMask": "0x42",
334        "EventName": "L2_LOCK.SELF.S_STATE",
335        "SampleAfterValue": "200000",
336        "BriefDescription": "L2 locked accesses"
337    },
338    {
339        "EventCode": "0x2B",
340        "Counter": "0,1",
341        "UMask": "0x4f",
342        "EventName": "L2_LOCK.SELF.MESI",
343        "SampleAfterValue": "200000",
344        "BriefDescription": "L2 locked accesses"
345    },
346    {
347        "EventCode": "0x2C",
348        "Counter": "0,1",
349        "UMask": "0x44",
350        "EventName": "L2_DATA_RQSTS.SELF.E_STATE",
351        "SampleAfterValue": "200000",
352        "BriefDescription": "All data requests from the L1 data cache"
353    },
354    {
355        "EventCode": "0x2C",
356        "Counter": "0,1",
357        "UMask": "0x41",
358        "EventName": "L2_DATA_RQSTS.SELF.I_STATE",
359        "SampleAfterValue": "200000",
360        "BriefDescription": "All data requests from the L1 data cache"
361    },
362    {
363        "EventCode": "0x2C",
364        "Counter": "0,1",
365        "UMask": "0x48",
366        "EventName": "L2_DATA_RQSTS.SELF.M_STATE",
367        "SampleAfterValue": "200000",
368        "BriefDescription": "All data requests from the L1 data cache"
369    },
370    {
371        "EventCode": "0x2C",
372        "Counter": "0,1",
373        "UMask": "0x42",
374        "EventName": "L2_DATA_RQSTS.SELF.S_STATE",
375        "SampleAfterValue": "200000",
376        "BriefDescription": "All data requests from the L1 data cache"
377    },
378    {
379        "EventCode": "0x2C",
380        "Counter": "0,1",
381        "UMask": "0x4f",
382        "EventName": "L2_DATA_RQSTS.SELF.MESI",
383        "SampleAfterValue": "200000",
384        "BriefDescription": "All data requests from the L1 data cache"
385    },
386    {
387        "EventCode": "0x2D",
388        "Counter": "0,1",
389        "UMask": "0x44",
390        "EventName": "L2_LD_IFETCH.SELF.E_STATE",
391        "SampleAfterValue": "200000",
392        "BriefDescription": "All read requests from L1 instruction and data caches"
393    },
394    {
395        "EventCode": "0x2D",
396        "Counter": "0,1",
397        "UMask": "0x41",
398        "EventName": "L2_LD_IFETCH.SELF.I_STATE",
399        "SampleAfterValue": "200000",
400        "BriefDescription": "All read requests from L1 instruction and data caches"
401    },
402    {
403        "EventCode": "0x2D",
404        "Counter": "0,1",
405        "UMask": "0x48",
406        "EventName": "L2_LD_IFETCH.SELF.M_STATE",
407        "SampleAfterValue": "200000",
408        "BriefDescription": "All read requests from L1 instruction and data caches"
409    },
410    {
411        "EventCode": "0x2D",
412        "Counter": "0,1",
413        "UMask": "0x42",
414        "EventName": "L2_LD_IFETCH.SELF.S_STATE",
415        "SampleAfterValue": "200000",
416        "BriefDescription": "All read requests from L1 instruction and data caches"
417    },
418    {
419        "EventCode": "0x2D",
420        "Counter": "0,1",
421        "UMask": "0x4f",
422        "EventName": "L2_LD_IFETCH.SELF.MESI",
423        "SampleAfterValue": "200000",
424        "BriefDescription": "All read requests from L1 instruction and data caches"
425    },
426    {
427        "EventCode": "0x2E",
428        "Counter": "0,1",
429        "UMask": "0x74",
430        "EventName": "L2_RQSTS.SELF.ANY.E_STATE",
431        "SampleAfterValue": "200000",
432        "BriefDescription": "L2 cache requests"
433    },
434    {
435        "EventCode": "0x2E",
436        "Counter": "0,1",
437        "UMask": "0x71",
438        "EventName": "L2_RQSTS.SELF.ANY.I_STATE",
439        "SampleAfterValue": "200000",
440        "BriefDescription": "L2 cache requests"
441    },
442    {
443        "EventCode": "0x2E",
444        "Counter": "0,1",
445        "UMask": "0x78",
446        "EventName": "L2_RQSTS.SELF.ANY.M_STATE",
447        "SampleAfterValue": "200000",
448        "BriefDescription": "L2 cache requests"
449    },
450    {
451        "EventCode": "0x2E",
452        "Counter": "0,1",
453        "UMask": "0x72",
454        "EventName": "L2_RQSTS.SELF.ANY.S_STATE",
455        "SampleAfterValue": "200000",
456        "BriefDescription": "L2 cache requests"
457    },
458    {
459        "EventCode": "0x2E",
460        "Counter": "0,1",
461        "UMask": "0x7f",
462        "EventName": "L2_RQSTS.SELF.ANY.MESI",
463        "SampleAfterValue": "200000",
464        "BriefDescription": "L2 cache requests"
465    },
466    {
467        "EventCode": "0x2E",
468        "Counter": "0,1",
469        "UMask": "0x44",
470        "EventName": "L2_RQSTS.SELF.DEMAND.E_STATE",
471        "SampleAfterValue": "200000",
472        "BriefDescription": "L2 cache requests"
473    },
474    {
475        "EventCode": "0x2E",
476        "Counter": "0,1",
477        "UMask": "0x48",
478        "EventName": "L2_RQSTS.SELF.DEMAND.M_STATE",
479        "SampleAfterValue": "200000",
480        "BriefDescription": "L2 cache requests"
481    },
482    {
483        "EventCode": "0x2E",
484        "Counter": "0,1",
485        "UMask": "0x42",
486        "EventName": "L2_RQSTS.SELF.DEMAND.S_STATE",
487        "SampleAfterValue": "200000",
488        "BriefDescription": "L2 cache requests"
489    },
490    {
491        "EventCode": "0x2E",
492        "Counter": "0,1",
493        "UMask": "0x54",
494        "EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE",
495        "SampleAfterValue": "200000",
496        "BriefDescription": "L2 cache requests"
497    },
498    {
499        "EventCode": "0x2E",
500        "Counter": "0,1",
501        "UMask": "0x51",
502        "EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE",
503        "SampleAfterValue": "200000",
504        "BriefDescription": "L2 cache requests"
505    },
506    {
507        "EventCode": "0x2E",
508        "Counter": "0,1",
509        "UMask": "0x58",
510        "EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE",
511        "SampleAfterValue": "200000",
512        "BriefDescription": "L2 cache requests"
513    },
514    {
515        "EventCode": "0x2E",
516        "Counter": "0,1",
517        "UMask": "0x52",
518        "EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE",
519        "SampleAfterValue": "200000",
520        "BriefDescription": "L2 cache requests"
521    },
522    {
523        "EventCode": "0x2E",
524        "Counter": "0,1",
525        "UMask": "0x5f",
526        "EventName": "L2_RQSTS.SELF.PREFETCH.MESI",
527        "SampleAfterValue": "200000",
528        "BriefDescription": "L2 cache requests"
529    },
530    {
531        "EventCode": "0x2E",
532        "Counter": "0,1",
533        "UMask": "0x41",
534        "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE",
535        "SampleAfterValue": "200000",
536        "BriefDescription": "L2 cache demand requests from this core that missed the L2"
537    },
538    {
539        "EventCode": "0x2E",
540        "Counter": "0,1",
541        "UMask": "0x4f",
542        "EventName": "L2_RQSTS.SELF.DEMAND.MESI",
543        "SampleAfterValue": "200000",
544        "BriefDescription": "L2 cache demand requests from this core"
545    },
546    {
547        "EventCode": "0x30",
548        "Counter": "0,1",
549        "UMask": "0x74",
550        "EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE",
551        "SampleAfterValue": "200000",
552        "BriefDescription": "Rejected L2 cache requests"
553    },
554    {
555        "EventCode": "0x30",
556        "Counter": "0,1",
557        "UMask": "0x71",
558        "EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE",
559        "SampleAfterValue": "200000",
560        "BriefDescription": "Rejected L2 cache requests"
561    },
562    {
563        "EventCode": "0x30",
564        "Counter": "0,1",
565        "UMask": "0x78",
566        "EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE",
567        "SampleAfterValue": "200000",
568        "BriefDescription": "Rejected L2 cache requests"
569    },
570    {
571        "EventCode": "0x30",
572        "Counter": "0,1",
573        "UMask": "0x72",
574        "EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE",
575        "SampleAfterValue": "200000",
576        "BriefDescription": "Rejected L2 cache requests"
577    },
578    {
579        "EventCode": "0x30",
580        "Counter": "0,1",
581        "UMask": "0x7f",
582        "EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI",
583        "SampleAfterValue": "200000",
584        "BriefDescription": "Rejected L2 cache requests"
585    },
586    {
587        "EventCode": "0x30",
588        "Counter": "0,1",
589        "UMask": "0x44",
590        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE",
591        "SampleAfterValue": "200000",
592        "BriefDescription": "Rejected L2 cache requests"
593    },
594    {
595        "EventCode": "0x30",
596        "Counter": "0,1",
597        "UMask": "0x41",
598        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE",
599        "SampleAfterValue": "200000",
600        "BriefDescription": "Rejected L2 cache requests"
601    },
602    {
603        "EventCode": "0x30",
604        "Counter": "0,1",
605        "UMask": "0x48",
606        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE",
607        "SampleAfterValue": "200000",
608        "BriefDescription": "Rejected L2 cache requests"
609    },
610    {
611        "EventCode": "0x30",
612        "Counter": "0,1",
613        "UMask": "0x42",
614        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE",
615        "SampleAfterValue": "200000",
616        "BriefDescription": "Rejected L2 cache requests"
617    },
618    {
619        "EventCode": "0x30",
620        "Counter": "0,1",
621        "UMask": "0x4f",
622        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI",
623        "SampleAfterValue": "200000",
624        "BriefDescription": "Rejected L2 cache requests"
625    },
626    {
627        "EventCode": "0x30",
628        "Counter": "0,1",
629        "UMask": "0x54",
630        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE",
631        "SampleAfterValue": "200000",
632        "BriefDescription": "Rejected L2 cache requests"
633    },
634    {
635        "EventCode": "0x30",
636        "Counter": "0,1",
637        "UMask": "0x51",
638        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE",
639        "SampleAfterValue": "200000",
640        "BriefDescription": "Rejected L2 cache requests"
641    },
642    {
643        "EventCode": "0x30",
644        "Counter": "0,1",
645        "UMask": "0x58",
646        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE",
647        "SampleAfterValue": "200000",
648        "BriefDescription": "Rejected L2 cache requests"
649    },
650    {
651        "EventCode": "0x30",
652        "Counter": "0,1",
653        "UMask": "0x52",
654        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE",
655        "SampleAfterValue": "200000",
656        "BriefDescription": "Rejected L2 cache requests"
657    },
658    {
659        "EventCode": "0x30",
660        "Counter": "0,1",
661        "UMask": "0x5f",
662        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI",
663        "SampleAfterValue": "200000",
664        "BriefDescription": "Rejected L2 cache requests"
665    },
666    {
667        "EventCode": "0x32",
668        "Counter": "0,1",
669        "UMask": "0x40",
670        "EventName": "L2_NO_REQ.SELF",
671        "SampleAfterValue": "200000",
672        "BriefDescription": "Cycles no L2 cache requests are pending"
673    },
674    {
675        "EventCode": "0x40",
676        "Counter": "0,1",
677        "UMask": "0xa1",
678        "EventName": "L1D_CACHE.LD",
679        "SampleAfterValue": "2000000",
680        "BriefDescription": "L1 Cacheable Data Reads"
681    },
682    {
683        "EventCode": "0x40",
684        "Counter": "0,1",
685        "UMask": "0xa2",
686        "EventName": "L1D_CACHE.ST",
687        "SampleAfterValue": "2000000",
688        "BriefDescription": "L1 Cacheable Data Writes"
689    },
690    {
691        "EventCode": "0x40",
692        "Counter": "0,1",
693        "UMask": "0x83",
694        "EventName": "L1D_CACHE.ALL_REF",
695        "SampleAfterValue": "2000000",
696        "BriefDescription": "L1 Data reads and writes"
697    },
698    {
699        "EventCode": "0x40",
700        "Counter": "0,1",
701        "UMask": "0xa3",
702        "EventName": "L1D_CACHE.ALL_CACHE_REF",
703        "SampleAfterValue": "2000000",
704        "BriefDescription": "L1 Data Cacheable reads and writes"
705    },
706    {
707        "EventCode": "0x40",
708        "Counter": "0,1",
709        "UMask": "0x8",
710        "EventName": "L1D_CACHE.REPL",
711        "SampleAfterValue": "200000",
712        "BriefDescription": "L1 Data line replacements"
713    },
714    {
715        "EventCode": "0x40",
716        "Counter": "0,1",
717        "UMask": "0x48",
718        "EventName": "L1D_CACHE.REPLM",
719        "SampleAfterValue": "200000",
720        "BriefDescription": "Modified cache lines allocated in the L1 data cache"
721    },
722    {
723        "EventCode": "0x40",
724        "Counter": "0,1",
725        "UMask": "0x10",
726        "EventName": "L1D_CACHE.EVICT",
727        "SampleAfterValue": "200000",
728        "BriefDescription": "Modified cache lines evicted from the L1 data cache"
729    },
730    {
731        "EventCode": "0xCB",
732        "Counter": "0,1",
733        "UMask": "0x1",
734        "EventName": "MEM_LOAD_RETIRED.L2_HIT",
735        "SampleAfterValue": "200000",
736        "BriefDescription": "Retired loads that hit the L2 cache (precise event)."
737    },
738    {
739        "EventCode": "0xCB",
740        "Counter": "0,1",
741        "UMask": "0x2",
742        "EventName": "MEM_LOAD_RETIRED.L2_MISS",
743        "SampleAfterValue": "10000",
744        "BriefDescription": "Retired loads that miss the L2 cache"
745    }
746]