xref: /linux/tools/perf/pmu-events/arch/x86/amdzen5/l3-cache.json (revision 230a7a71f92212e723fa435d4ca5922de33ec88a) 
1[
2  {
3    "EventName": "l3_lookup_state.l3_miss",
4    "EventCode": "0x04",
5    "BriefDescription": "L3 cache misses.",
6    "UMask": "0x01",
7    "Unit": "L3PMC"
8  },
9  {
10    "EventName": "l3_lookup_state.l3_hit",
11    "EventCode": "0x04",
12    "BriefDescription": "L3 cache hits.",
13    "UMask": "0xfe",
14    "Unit": "L3PMC"
15  },
16  {
17    "EventName": "l3_lookup_state.all_coherent_accesses_to_l3",
18    "EventCode": "0x04",
19    "BriefDescription": "L3 cache requests for all coherent accesses.",
20    "UMask": "0xff",
21    "Unit": "L3PMC"
22  },
23  {
24    "EventName": "l3_xi_sampled_latency.dram_near",
25    "EventCode": "0xac",
26    "BriefDescription": "Average sampled latency when data is sourced from DRAM in the same NUMA node.",
27    "UMask": "0x01",
28    "EnAllCores": "0x1",
29    "EnAllSlices": "0x1",
30    "SliceId": "0x3",
31    "ThreadMask": "0x3",
32    "Unit": "L3PMC"
33  },
34  {
35    "EventName": "l3_xi_sampled_latency.dram_far",
36    "EventCode": "0xac",
37    "BriefDescription": "Average sampled latency when data is sourced from DRAM in a different NUMA node.",
38    "UMask": "0x02",
39    "EnAllCores": "0x1",
40    "EnAllSlices": "0x1",
41    "SliceId": "0x3",
42    "ThreadMask": "0x3",
43    "Unit": "L3PMC"
44  },
45  {
46    "EventName": "l3_xi_sampled_latency.near_cache",
47    "EventCode": "0xac",
48    "BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in the same NUMA node.",
49    "UMask": "0x04",
50    "EnAllCores": "0x1",
51    "EnAllSlices": "0x1",
52    "SliceId": "0x3",
53    "ThreadMask": "0x3",
54    "Unit": "L3PMC"
55  },
56  {
57    "EventName": "l3_xi_sampled_latency.far_cache",
58    "EventCode": "0xac",
59    "BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in a different NUMA node.",
60    "UMask": "0x08",
61    "EnAllCores": "0x1",
62    "EnAllSlices": "0x1",
63    "SliceId": "0x3",
64    "ThreadMask": "0x3",
65    "Unit": "L3PMC"
66  },
67  {
68    "EventName": "l3_xi_sampled_latency.ext_near",
69    "EventCode": "0xac",
70    "BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in the same NUMA node.",
71    "UMask": "0x10",
72    "EnAllCores": "0x1",
73    "EnAllSlices": "0x1",
74    "SliceId": "0x3",
75    "ThreadMask": "0x3",
76    "Unit": "L3PMC"
77  },
78  {
79    "EventName": "l3_xi_sampled_latency.ext_far",
80    "EventCode": "0xac",
81    "BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in a different NUMA node.",
82    "UMask": "0x20",
83    "EnAllCores": "0x1",
84    "EnAllSlices": "0x1",
85    "SliceId": "0x3",
86    "ThreadMask": "0x3",
87    "Unit": "L3PMC"
88  },
89  {
90    "EventName": "l3_xi_sampled_latency.all",
91    "EventCode": "0xac",
92    "BriefDescription": "Average sampled latency from all data sources.",
93    "UMask": "0x3f",
94    "EnAllCores": "0x1",
95    "EnAllSlices": "0x1",
96    "SliceId": "0x3",
97    "ThreadMask": "0x3",
98    "Unit": "L3PMC"
99  },
100  {
101    "EventName": "l3_xi_sampled_latency_requests.dram_near",
102    "EventCode": "0xad",
103    "BriefDescription": "L3 cache fill requests sourced from DRAM in the same NUMA node.",
104    "UMask": "0x01",
105    "EnAllCores": "0x1",
106    "EnAllSlices": "0x1",
107    "SliceId": "0x3",
108    "ThreadMask": "0x3",
109    "Unit": "L3PMC"
110  },
111  {
112    "EventName": "l3_xi_sampled_latency_requests.dram_far",
113    "EventCode": "0xad",
114    "BriefDescription": "L3 cache fill requests sourced from DRAM in a different NUMA node.",
115    "UMask": "0x02",
116    "EnAllCores": "0x1",
117    "EnAllSlices": "0x1",
118    "SliceId": "0x3",
119    "ThreadMask": "0x3",
120    "Unit": "L3PMC"
121  },
122  {
123    "EventName": "l3_xi_sampled_latency_requests.near_cache",
124    "EventCode": "0xad",
125    "BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in the same NUMA node.",
126    "UMask": "0x04",
127    "EnAllCores": "0x1",
128    "EnAllSlices": "0x1",
129    "SliceId": "0x3",
130    "ThreadMask": "0x3",
131    "Unit": "L3PMC"
132  },
133  {
134    "EventName": "l3_xi_sampled_latency_requests.far_cache",
135    "EventCode": "0xad",
136    "BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in a different NUMA node.",
137    "UMask": "0x08",
138    "EnAllCores": "0x1",
139    "EnAllSlices": "0x1",
140    "SliceId": "0x3",
141    "ThreadMask": "0x3",
142    "Unit": "L3PMC"
143  },
144  {
145    "EventName": "l3_xi_sampled_latency_requests.ext_near",
146    "EventCode": "0xad",
147    "BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in the same NUMA node.",
148    "UMask": "0x10",
149    "EnAllCores": "0x1",
150    "EnAllSlices": "0x1",
151    "SliceId": "0x3",
152    "ThreadMask": "0x3",
153    "Unit": "L3PMC"
154  },
155  {
156    "EventName": "l3_xi_sampled_latency_requests.ext_far",
157    "EventCode": "0xad",
158    "BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in a different NUMA node.",
159    "UMask": "0x20",
160    "EnAllCores": "0x1",
161    "EnAllSlices": "0x1",
162    "SliceId": "0x3",
163    "ThreadMask": "0x3",
164    "Unit": "L3PMC"
165  },
166  {
167    "EventName": "l3_xi_sampled_latency_requests.all",
168    "EventCode": "0xad",
169    "BriefDescription": "L3 cache fill requests sourced from all data sources.",
170    "UMask": "0x3f",
171    "EnAllCores": "0x1",
172    "EnAllSlices": "0x1",
173    "SliceId": "0x3",
174    "ThreadMask": "0x3",
175    "Unit": "L3PMC"
176  }
177]
178