xref: /linux/tools/perf/pmu-events/arch/x86/amdzen5/l2-cache.json (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1[
2  {
3    "EventName": "l2_request_g1.group2",
4    "EventCode": "0x60",
5    "BriefDescription": "L2 cache requests of non-cacheable type (non-cached data and instructions reads, self-modifying code checks).",
6    "UMask": "0x01"
7  },
8  {
9    "EventName": "l2_request_g1.l2_hw_pf",
10    "EventCode": "0x60",
11    "BriefDescription": "L2 cache requests: from hardware prefetchers to prefetch directly into L2 (hit or miss).",
12    "UMask": "0x02"
13  },
14  {
15    "EventName": "l2_request_g1.prefetch_l2_cmd",
16    "EventCode": "0x60",
17    "BriefDescription": "L2 cache requests: prefetch directly into L2.",
18    "UMask": "0x04"
19  },
20  {
21    "EventName": "l2_request_g1.cacheable_ic_read",
22    "EventCode": "0x60",
23    "BriefDescription": "L2 cache requests: instruction cache reads.",
24    "UMask": "0x10"
25  },
26  {
27    "EventName": "l2_request_g1.ls_rd_blk_c_s",
28    "EventCode": "0x60",
29    "BriefDescription": "L2 cache requests: data cache shared reads.",
30    "UMask": "0x20"
31  },
32  {
33    "EventName": "l2_request_g1.rd_blk_x",
34    "EventCode": "0x60",
35    "BriefDescription": "L2 cache requests: data cache stores.",
36    "UMask": "0x40"
37  },
38  {
39    "EventName": "l2_request_g1.rd_blk_l",
40    "EventCode": "0x60",
41    "BriefDescription": "L2 cache requests: data cache reads including hardware and software prefetch.",
42    "UMask": "0x80"
43  },
44  {
45    "EventName": "l2_request_g1.all_dc",
46    "EventCode": "0x60",
47    "BriefDescription": "L2 cache requests of common types from L1 data cache (including prefetches).",
48    "UMask": "0xe0"
49  },
50  {
51    "EventName": "l2_request_g1.all_no_prefetch",
52    "EventCode": "0x60",
53    "BriefDescription": "L2 cache requests of common types not including prefetches.",
54    "UMask": "0xf1"
55  },
56  {
57    "EventName": "l2_request_g1.all",
58    "EventCode": "0x60",
59    "BriefDescription": "L2 cache requests of all types.",
60    "UMask": "0xf7"
61  },
62  {
63    "EventName": "l2_request_g2.ls_rd_sized_nc",
64    "EventCode": "0x61",
65    "BriefDescription": "L2 cache requests: non-coherent, non-cacheable LS sized reads.",
66    "UMask": "0x20"
67  },
68  {
69    "EventName": "l2_request_g2.ls_rd_sized",
70    "EventCode": "0x61",
71    "BriefDescription": "L2 cache requests: coherent, non-cacheable LS sized reads.",
72    "UMask": "0x40"
73  },
74  {
75    "EventName": "l2_wcb_req.wcb_close",
76    "EventCode": "0x63",
77    "BriefDescription": "Write Combining Buffer (WCB) closures.",
78    "UMask": "0x20"
79  },
80  {
81    "EventName": "l2_cache_req_stat.ic_fill_miss",
82    "EventCode": "0x64",
83    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache request miss in L2.",
84    "UMask": "0x01"
85  },
86  {
87    "EventName": "l2_cache_req_stat.ic_fill_hit_s",
88    "EventCode": "0x64",
89    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit non-modifiable line in L2.",
90    "UMask": "0x02"
91  },
92  {
93    "EventName": "l2_cache_req_stat.ic_fill_hit_x",
94    "EventCode": "0x64",
95    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit modifiable line in L2.",
96    "UMask": "0x04"
97  },
98  {
99    "EventName": "l2_cache_req_stat.ic_hit_in_l2",
100    "EventCode": "0x64",
101    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache hits.",
102    "UMask": "0x06"
103  },
104  {
105    "EventName": "l2_cache_req_stat.ic_access_in_l2",
106    "EventCode": "0x64",
107    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache access.",
108    "UMask": "0x07"
109  },
110  {
111    "EventName": "l2_cache_req_stat.ls_rd_blk_c",
112    "EventCode": "0x64",
113    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache request miss in L2.",
114    "UMask": "0x08"
115  },
116  {
117    "EventName": "l2_cache_req_stat.ic_dc_miss_in_l2",
118    "EventCode": "0x64",
119    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache misses.",
120    "UMask": "0x09"
121  },
122  {
123    "EventName": "l2_cache_req_stat.ls_rd_blk_x",
124    "EventCode": "0x64",
125    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache store or state change hit in L2.",
126    "UMask": "0x10"
127  },
128  {
129    "EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_s",
130    "EventCode": "0x64",
131    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit non-modifiable line in L2.",
132    "UMask": "0x20"
133  },
134  {
135    "EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_x",
136    "EventCode": "0x64",
137    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit modifiable line in L2.",
138    "UMask": "0x40"
139  },
140  {
141    "EventName": "l2_cache_req_stat.ls_rd_blk_cs",
142    "EventCode": "0x64",
143    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache shared read hit in L2.",
144    "UMask": "0x80"
145  },
146  {
147    "EventName": "l2_cache_req_stat.dc_hit_in_l2",
148    "EventCode": "0x64",
149    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data cache hits.",
150    "UMask": "0xf0"
151  },
152  {
153    "EventName": "l2_cache_req_stat.ic_dc_hit_in_l2",
154    "EventCode": "0x64",
155    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache hits.",
156    "UMask": "0xf6"
157  },
158  {
159    "EventName": "l2_cache_req_stat.dc_access_in_l2",
160    "EventCode": "0x64",
161    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data cache access.",
162    "UMask": "0xf8"
163  },
164  {
165    "EventName": "l2_cache_req_stat.all",
166    "EventCode": "0x64",
167    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache access.",
168    "UMask": "0xff"
169  },
170  {
171    "EventName": "l2_pf_hit_l2.l2_hwpf",
172    "EventCode": "0x70",
173    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L2 hardware prefetchers.",
174    "UMask": "0x1f"
175  },
176  {
177    "EventName": "l2_pf_hit_l2.l1_dc_hwpf",
178    "EventCode": "0x70",
179    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L1 data hardware prefetchers.",
180    "UMask": "0xe0"
181  },
182  {
183    "EventName": "l2_pf_hit_l2.l1_dc_l2_hwpf",
184    "EventCode": "0x70",
185    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L1 data and L2 hardware prefetchers.",
186    "UMask": "0xff"
187  },
188  {
189    "EventName": "l2_pf_miss_l2_hit_l3.l2_hwpf",
190    "EventCode": "0x71",
191    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L2 hardware prefetchers.",
192    "UMask": "0x1f"
193  },
194  {
195    "EventName": "l2_pf_miss_l2_hit_l3.l1_dc_hwpf",
196    "EventCode": "0x71",
197    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L1 data hardware prefetchers.",
198    "UMask": "0xe0"
199  },
200  {
201    "EventName": "l2_pf_miss_l2_hit_l3.l1_dc_l2_hwpf",
202    "EventCode": "0x71",
203    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L1 data and L2 hardware prefetchers.",
204    "UMask": "0xff"
205  },
206  {
207    "EventName": "l2_pf_miss_l2_l3.l2_hwpf",
208    "EventCode": "0x72",
209    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L2 hardware prefetchers.",
210    "UMask": "0x1f"
211  },
212  {
213    "EventName": "l2_pf_miss_l2_l3.l1_dc_hwpf",
214    "EventCode": "0x72",
215    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L1 data hardware prefetchers.",
216    "UMask": "0xe0"
217  },
218  {
219    "EventName": "l2_pf_miss_l2_l3.l1_dc_l2_hwpf",
220    "EventCode": "0x72",
221    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L1 data and L2 hardware prefetchers.",
222    "UMask": "0xff"
223  },
224  {
225    "EventName": "l2_fill_rsp_src.local_ccx",
226    "EventCode": "0x165",
227    "BriefDescription": "L2 cache fills from L3 cache or different L2 cache in the same CCX.",
228    "UMask": "0x02"
229  },
230  {
231    "EventName": "l2_fill_rsp_src.near_cache",
232    "EventCode": "0x165",
233    "BriefDescription": "L2 cache fills from cache of another CCX when the address was in the same NUMA node.",
234    "UMask": "0x04"
235  },
236  {
237    "EventName": "l2_fill_rsp_src.dram_io_near",
238    "EventCode": "0x165",
239    "BriefDescription": "L2 cache fills from either DRAM or MMIO in the same NUMA node.",
240    "UMask": "0x08"
241  },
242  {
243    "EventName": "l2_fill_rsp_src.far_cache",
244    "EventCode": "0x165",
245    "BriefDescription": "L2 cache fills from cache of another CCX when the address was in a different NUMA node.",
246    "UMask": "0x10"
247  },
248  {
249    "EventName": "l2_fill_rsp_src.dram_io_far",
250    "EventCode": "0x165",
251    "BriefDescription": "L2 cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
252    "UMask": "0x40"
253  },
254  {
255    "EventName": "l2_fill_rsp_src.alternate_memories",
256    "EventCode": "0x165",
257    "BriefDescription": "L2 cache fills from extension memory.",
258    "UMask": "0x80"
259  },
260  {
261    "EventName": "l2_fill_rsp_src.all",
262    "EventCode": "0x165",
263    "BriefDescription": "L2 cache fills from all types of data sources.",
264    "UMask": "0xde"
265  }
266]
267