1*45c072f2SSandipan Das[ 2*45c072f2SSandipan Das { 3*45c072f2SSandipan Das "EventName": "ic_cache_fill_l2", 4*45c072f2SSandipan Das "EventCode": "0x82", 5*45c072f2SSandipan Das "BriefDescription": "Instruction cache lines (64 bytes) fulfilled from the L2 cache." 6*45c072f2SSandipan Das }, 7*45c072f2SSandipan Das { 8*45c072f2SSandipan Das "EventName": "ic_cache_fill_sys", 9*45c072f2SSandipan Das "EventCode": "0x83", 10*45c072f2SSandipan Das "BriefDescription": "Instruction cache lines (64 bytes) fulfilled from system memory or another cache." 11*45c072f2SSandipan Das }, 12*45c072f2SSandipan Das { 13*45c072f2SSandipan Das "EventName": "ic_fetch_ibs_events.fetch_tagged", 14*45c072f2SSandipan Das "EventCode": "0x188", 15*45c072f2SSandipan Das "BriefDescription": "Fetches tagged by Fetch IBS. Not all tagged fetches result in a valid sample and an IBS interrupt.", 16*45c072f2SSandipan Das "UMask": "0x02" 17*45c072f2SSandipan Das }, 18*45c072f2SSandipan Das { 19*45c072f2SSandipan Das "EventName": "ic_fetch_ibs_events.sample_discarded", 20*45c072f2SSandipan Das "EventCode": "0x188", 21*45c072f2SSandipan Das "BriefDescription": "Fetches discarded after being tagged by Fetch IBS due to reasons other than IBS filtering.", 22*45c072f2SSandipan Das "UMask": "0x04" 23*45c072f2SSandipan Das }, 24*45c072f2SSandipan Das { 25*45c072f2SSandipan Das "EventName": "ic_fetch_ibs_events.sample_filtered", 26*45c072f2SSandipan Das "EventCode": "0x188", 27*45c072f2SSandipan Das "BriefDescription": "Fetches discarded after being tagged by Fetch IBS due to IBS filtering.", 28*45c072f2SSandipan Das "UMask": "0x08" 29*45c072f2SSandipan Das }, 30*45c072f2SSandipan Das { 31*45c072f2SSandipan Das "EventName": "ic_fetch_ibs_events.sample_valid", 32*45c072f2SSandipan Das "EventCode": "0x188", 33*45c072f2SSandipan Das "BriefDescription": "Fetches tagged by Fetch IBS that result in a valid sample and an IBS interrupt.", 34*45c072f2SSandipan Das "UMask": "0x10" 35*45c072f2SSandipan Das }, 36*45c072f2SSandipan Das { 37*45c072f2SSandipan Das "EventName": "ic_tag_hit_miss.instruction_cache_hit", 38*45c072f2SSandipan Das "EventCode": "0x18e", 39*45c072f2SSandipan Das "BriefDescription": "Instruction cache hits.", 40*45c072f2SSandipan Das "UMask": "0x07" 41*45c072f2SSandipan Das }, 42*45c072f2SSandipan Das { 43*45c072f2SSandipan Das "EventName": "ic_tag_hit_miss.instruction_cache_miss", 44*45c072f2SSandipan Das "EventCode": "0x18e", 45*45c072f2SSandipan Das "BriefDescription": "Instruction cache misses.", 46*45c072f2SSandipan Das "UMask": "0x18" 47*45c072f2SSandipan Das }, 48*45c072f2SSandipan Das { 49*45c072f2SSandipan Das "EventName": "ic_tag_hit_miss.all_instruction_cache_accesses", 50*45c072f2SSandipan Das "EventCode": "0x18e", 51*45c072f2SSandipan Das "BriefDescription": "Instruction cache accesses of all types.", 52*45c072f2SSandipan Das "UMask": "0x1f" 53*45c072f2SSandipan Das }, 54*45c072f2SSandipan Das { 55*45c072f2SSandipan Das "EventName": "op_cache_hit_miss.op_cache_hit", 56*45c072f2SSandipan Das "EventCode": "0x28f", 57*45c072f2SSandipan Das "BriefDescription": "Op cache hits.", 58*45c072f2SSandipan Das "UMask": "0x03" 59*45c072f2SSandipan Das }, 60*45c072f2SSandipan Das { 61*45c072f2SSandipan Das "EventName": "op_cache_hit_miss.op_cache_miss", 62*45c072f2SSandipan Das "EventCode": "0x28f", 63*45c072f2SSandipan Das "BriefDescription": "Op cache misses.", 64*45c072f2SSandipan Das "UMask": "0x04" 65*45c072f2SSandipan Das }, 66*45c072f2SSandipan Das { 67*45c072f2SSandipan Das "EventName": "op_cache_hit_miss.all_op_cache_accesses", 68*45c072f2SSandipan Das "EventCode": "0x28f", 69*45c072f2SSandipan Das "BriefDescription": "Op cache accesses of all types.", 70*45c072f2SSandipan Das "UMask": "0x07" 71*45c072f2SSandipan Das } 72*45c072f2SSandipan Das] 73