xref: /linux/tools/perf/pmu-events/arch/x86/amdzen3/branch.json (revision 24168c5e6dfbdd5b414f048f47f75d64533296ca)
1[
2  {
3    "EventName": "bp_l1_btb_correct",
4    "EventCode": "0x8a",
5    "BriefDescription": "L1 Branch Prediction Overrides Existing Prediction (speculative)."
6  },
7  {
8    "EventName": "bp_l2_btb_correct",
9    "EventCode": "0x8b",
10    "BriefDescription": "L2 Branch Prediction Overrides Existing Prediction (speculative)."
11  },
12  {
13    "EventName": "bp_dyn_ind_pred",
14    "EventCode": "0x8e",
15    "BriefDescription": "Dynamic Indirect Predictions.",
16    "PublicDescription": "The number of times a branch used the indirect predictor to make a prediction."
17  },
18  {
19    "EventName": "bp_de_redirect",
20    "EventCode": "0x91",
21    "BriefDescription": "Decode Redirects",
22    "PublicDescription": "The number of times the instruction decoder overrides the predicted target."
23  },
24  {
25    "EventName": "bp_l1_tlb_fetch_hit",
26    "EventCode": "0x94",
27    "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB.",
28    "UMask": "0xff"
29  },
30  {
31    "EventName": "bp_l1_tlb_fetch_hit.if1g",
32    "EventCode": "0x94",
33    "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit (1G page size).",
34    "UMask": "0x04"
35  },
36  {
37    "EventName": "bp_l1_tlb_fetch_hit.if2m",
38    "EventCode": "0x94",
39    "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit (2M page size).",
40    "UMask": "0x02"
41  },
42  {
43    "EventName": "bp_l1_tlb_fetch_hit.if4k",
44    "EventCode": "0x94",
45    "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instrcution TLB hit (4K or 16K page size).",
46    "UMask": "0x01"
47  },
48  {
49    "EventName": "bp_tlb_rel",
50    "EventCode": "0x99",
51    "BriefDescription": "The number of ITLB reload requests."
52  }
53]
54