1[ 2 { 3 "MetricName": "branch_misprediction_ratio", 4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)", 5 "MetricExpr": "d_ratio(ex_ret_brn_misp, ex_ret_brn)", 6 "MetricGroup": "branch_prediction", 7 "ScaleUnit": "100%" 8 }, 9 { 10 "EventName": "all_dc_accesses", 11 "EventCode": "0x29", 12 "BriefDescription": "All L1 Data Cache Accesses", 13 "UMask": "0x07" 14 }, 15 { 16 "MetricName": "all_l2_cache_accesses", 17 "BriefDescription": "All L2 Cache Accesses", 18 "MetricExpr": "l2_request_g1.all_no_prefetch + l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3", 19 "MetricGroup": "l2_cache" 20 }, 21 { 22 "EventName": "l2_cache_accesses_from_ic_misses", 23 "EventCode": "0x60", 24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)", 25 "UMask": "0x10" 26 }, 27 { 28 "EventName": "l2_cache_accesses_from_dc_misses", 29 "EventCode": "0x60", 30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)", 31 "UMask": "0xc8" 32 }, 33 { 34 "MetricName": "l2_cache_accesses_from_l2_hwpf", 35 "BriefDescription": "L2 Cache Accesses from L2 HWPF", 36 "MetricExpr": "l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3", 37 "MetricGroup": "l2_cache" 38 }, 39 { 40 "MetricName": "all_l2_cache_misses", 41 "BriefDescription": "All L2 Cache Misses", 42 "MetricExpr": "l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3", 43 "MetricGroup": "l2_cache" 44 }, 45 { 46 "EventName": "l2_cache_misses_from_ic_miss", 47 "EventCode": "0x64", 48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses", 49 "UMask": "0x01" 50 }, 51 { 52 "EventName": "l2_cache_misses_from_dc_misses", 53 "EventCode": "0x64", 54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses", 55 "UMask": "0x08" 56 }, 57 { 58 "MetricName": "l2_cache_misses_from_l2_hwpf", 59 "BriefDescription": "L2 Cache Misses from L2 HWPF", 60 "MetricExpr": "l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3", 61 "MetricGroup": "l2_cache" 62 }, 63 { 64 "MetricName": "all_l2_cache_hits", 65 "BriefDescription": "All L2 Cache Hits", 66 "MetricExpr": "l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2", 67 "MetricGroup": "l2_cache" 68 }, 69 { 70 "EventName": "l2_cache_hits_from_ic_misses", 71 "EventCode": "0x64", 72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses", 73 "UMask": "0x06" 74 }, 75 { 76 "EventName": "l2_cache_hits_from_dc_misses", 77 "EventCode": "0x64", 78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses", 79 "UMask": "0x70" 80 }, 81 { 82 "EventName": "l2_cache_hits_from_l2_hwpf", 83 "EventCode": "0x70", 84 "BriefDescription": "L2 Cache Hits from L2 HWPF", 85 "UMask": "0xff" 86 }, 87 { 88 "EventName": "l3_accesses", 89 "EventCode": "0x04", 90 "BriefDescription": "L3 Accesses", 91 "UMask": "0xff", 92 "Unit": "L3PMC" 93 }, 94 { 95 "EventName": "l3_misses", 96 "EventCode": "0x04", 97 "BriefDescription": "L3 Misses (includes Chg2X)", 98 "UMask": "0x01", 99 "Unit": "L3PMC" 100 }, 101 { 102 "MetricName": "l3_read_miss_latency", 103 "BriefDescription": "Average L3 Read Miss Latency (in core clocks)", 104 "MetricExpr": "(xi_sys_fill_latency * 16) / xi_ccx_sdp_req1.all_l3_miss_req_typs", 105 "MetricGroup": "l3_cache", 106 "ScaleUnit": "1core clocks" 107 }, 108 { 109 "MetricName": "ic_fetch_miss_ratio", 110 "BriefDescription": "L1 Instruction Cache (32B) Fetch Miss Ratio", 111 "MetricExpr": "d_ratio(l2_cache_req_stat.ic_access_in_l2, bp_l1_tlb_fetch_hit + bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_miss)", 112 "MetricGroup": "l2_cache", 113 "ScaleUnit": "100%" 114 }, 115 { 116 "MetricName": "l1_itlb_misses", 117 "BriefDescription": "L1 ITLB Misses", 118 "MetricExpr": "bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_miss", 119 "MetricGroup": "tlb" 120 }, 121 { 122 "EventName": "l2_itlb_misses", 123 "EventCode": "0x85", 124 "BriefDescription": "L2 ITLB Misses & Instruction page walks", 125 "UMask": "0x07" 126 }, 127 { 128 "EventName": "l1_dtlb_misses", 129 "EventCode": "0x45", 130 "BriefDescription": "L1 DTLB Misses", 131 "UMask": "0xff" 132 }, 133 { 134 "EventName": "l2_dtlb_misses", 135 "EventCode": "0x45", 136 "BriefDescription": "L2 DTLB Misses & Data page walks", 137 "UMask": "0xf0" 138 }, 139 { 140 "EventName": "all_tlbs_flushed", 141 "EventCode": "0x78", 142 "BriefDescription": "All TLBs Flushed", 143 "UMask": "0xdf" 144 }, 145 { 146 "EventName": "uops_dispatched", 147 "EventCode": "0xaa", 148 "BriefDescription": "Micro-ops Dispatched", 149 "UMask": "0x03" 150 }, 151 { 152 "EventName": "sse_avx_stalls", 153 "EventCode": "0x0e", 154 "BriefDescription": "Mixed SSE/AVX Stalls", 155 "UMask": "0x0e" 156 }, 157 { 158 "EventName": "uops_retired", 159 "EventCode": "0xc1", 160 "BriefDescription": "Micro-ops Retired" 161 }, 162 { 163 "MetricName": "all_remote_links_outbound", 164 "BriefDescription": "Approximate: Outbound data bytes for all Remote Links for a node (die)", 165 "MetricExpr": "remote_outbound_data_controller_0 + remote_outbound_data_controller_1 + remote_outbound_data_controller_2 + remote_outbound_data_controller_3", 166 "MetricGroup": "data_fabric", 167 "PerPkg": "1", 168 "ScaleUnit": "3e-5MiB" 169 }, 170 { 171 "MetricName": "nps1_die_to_dram", 172 "BriefDescription": "Approximate: Combined DRAM B/bytes of all channels on a NPS1 node (die)", 173 "MetricExpr": "dram_channel_data_controller_0 + dram_channel_data_controller_1 + dram_channel_data_controller_2 + dram_channel_data_controller_3 + dram_channel_data_controller_4 + dram_channel_data_controller_5 + dram_channel_data_controller_6 + dram_channel_data_controller_7", 174 "MetricConstraint": "NO_GROUP_EVENTS", 175 "MetricGroup": "data_fabric", 176 "PerPkg": "1", 177 "ScaleUnit": "6.1e-5MiB" 178 } 179] 180