1[ 2 { 3 "BriefDescription": "ASSISTS.HARDWARE", 4 "EventCode": "0xc1", 5 "EventName": "ASSISTS.HARDWARE", 6 "SampleAfterValue": "100003", 7 "UMask": "0x4", 8 "Unit": "cpu_core" 9 }, 10 { 11 "BriefDescription": "ASSISTS.PAGE_FAULT", 12 "EventCode": "0xc1", 13 "EventName": "ASSISTS.PAGE_FAULT", 14 "SampleAfterValue": "1000003", 15 "UMask": "0x8", 16 "Unit": "cpu_core" 17 }, 18 { 19 "BriefDescription": "CORE_POWER.LICENSE_1", 20 "EventCode": "0x28", 21 "EventName": "CORE_POWER.LICENSE_1", 22 "SampleAfterValue": "200003", 23 "UMask": "0x2", 24 "Unit": "cpu_core" 25 }, 26 { 27 "BriefDescription": "CORE_POWER.LICENSE_2", 28 "EventCode": "0x28", 29 "EventName": "CORE_POWER.LICENSE_2", 30 "SampleAfterValue": "200003", 31 "UMask": "0x4", 32 "Unit": "cpu_core" 33 }, 34 { 35 "BriefDescription": "CORE_POWER.LICENSE_3", 36 "EventCode": "0x28", 37 "EventName": "CORE_POWER.LICENSE_3", 38 "SampleAfterValue": "200003", 39 "UMask": "0x8", 40 "Unit": "cpu_core" 41 }, 42 { 43 "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have any type of response.", 44 "EventCode": "0xB7", 45 "EventName": "OCR.COREWB_M.ANY_RESPONSE", 46 "MSRIndex": "0x1a6,0x1a7", 47 "MSRValue": "0x10008", 48 "SampleAfterValue": "100003", 49 "UMask": "0x1", 50 "Unit": "cpu_atom" 51 }, 52 { 53 "BriefDescription": "Counts demand data reads that have any type of response.", 54 "EventCode": "0xB7", 55 "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", 56 "MSRIndex": "0x1a6,0x1a7", 57 "MSRValue": "0x10001", 58 "SampleAfterValue": "100003", 59 "UMask": "0x1", 60 "Unit": "cpu_atom" 61 }, 62 { 63 "BriefDescription": "Counts demand data reads that have any type of response.", 64 "EventCode": "0x2A,0x2B", 65 "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", 66 "MSRIndex": "0x1a6,0x1a7", 67 "MSRValue": "0x10001", 68 "SampleAfterValue": "100003", 69 "UMask": "0x1", 70 "Unit": "cpu_core" 71 }, 72 { 73 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 74 "EventCode": "0x2A,0x2B", 75 "EventName": "OCR.DEMAND_DATA_RD.DRAM", 76 "MSRIndex": "0x1a6,0x1a7", 77 "MSRValue": "0x184000001", 78 "SampleAfterValue": "100003", 79 "UMask": "0x1", 80 "Unit": "cpu_core" 81 }, 82 { 83 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", 84 "EventCode": "0xB7", 85 "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", 86 "MSRIndex": "0x1a6,0x1a7", 87 "MSRValue": "0x10002", 88 "SampleAfterValue": "100003", 89 "UMask": "0x1", 90 "Unit": "cpu_atom" 91 }, 92 { 93 "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", 94 "EventCode": "0x2A,0x2B", 95 "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", 96 "MSRIndex": "0x1a6,0x1a7", 97 "MSRValue": "0x10002", 98 "SampleAfterValue": "100003", 99 "UMask": "0x1", 100 "Unit": "cpu_core" 101 }, 102 { 103 "BriefDescription": "Counts streaming stores that have any type of response.", 104 "EventCode": "0xB7", 105 "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", 106 "MSRIndex": "0x1a6,0x1a7", 107 "MSRValue": "0x10800", 108 "SampleAfterValue": "100003", 109 "UMask": "0x1", 110 "Unit": "cpu_atom" 111 }, 112 { 113 "BriefDescription": "Counts streaming stores that have any type of response.", 114 "EventCode": "0x2A,0x2B", 115 "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", 116 "MSRIndex": "0x1a6,0x1a7", 117 "MSRValue": "0x10800", 118 "SampleAfterValue": "100003", 119 "UMask": "0x1", 120 "Unit": "cpu_core" 121 }, 122 { 123 "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.", 124 "EventCode": "0xa5", 125 "EventName": "RS.EMPTY", 126 "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)", 127 "SampleAfterValue": "1000003", 128 "UMask": "0x7", 129 "Unit": "cpu_core" 130 }, 131 { 132 "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", 133 "CounterMask": "1", 134 "EdgeDetect": "1", 135 "EventCode": "0xa5", 136 "EventName": "RS.EMPTY_COUNT", 137 "Invert": "1", 138 "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)", 139 "SampleAfterValue": "100003", 140 "UMask": "0x7", 141 "Unit": "cpu_core" 142 }, 143 { 144 "BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY_COUNT", 145 "CounterMask": "1", 146 "Deprecated": "1", 147 "EdgeDetect": "1", 148 "EventCode": "0xa5", 149 "EventName": "RS_EMPTY.COUNT", 150 "Invert": "1", 151 "SampleAfterValue": "100003", 152 "UMask": "0x7", 153 "Unit": "cpu_core" 154 }, 155 { 156 "BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY", 157 "Deprecated": "1", 158 "EventCode": "0xa5", 159 "EventName": "RS_EMPTY.CYCLES", 160 "SampleAfterValue": "1000003", 161 "UMask": "0x7", 162 "Unit": "cpu_core" 163 }, 164 { 165 "BriefDescription": "XQ.FULL_CYCLES", 166 "CounterMask": "1", 167 "EventCode": "0x2d", 168 "EventName": "XQ.FULL_CYCLES", 169 "SampleAfterValue": "1000003", 170 "UMask": "0x1", 171 "Unit": "cpu_core" 172 } 173] 174