xref: /linux/tools/perf/pmu-events/arch/x86/alderlake/other.json (revision f9900dd0053ec35863ea50dcbefbaf143cb41419)
1*f9900dd0SZhengjun Xing[
2*f9900dd0SZhengjun Xing    {
3*f9900dd0SZhengjun Xing        "BriefDescription": "Counts demand data reads that have any type of response.",
4*f9900dd0SZhengjun Xing        "Counter": "0,1,2,3",
5*f9900dd0SZhengjun Xing        "EventCode": "0xB7",
6*f9900dd0SZhengjun Xing        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
7*f9900dd0SZhengjun Xing        "MSRIndex": "0x1a6,0x1a7",
8*f9900dd0SZhengjun Xing        "MSRValue": "0x10001",
9*f9900dd0SZhengjun Xing        "SampleAfterValue": "100003",
10*f9900dd0SZhengjun Xing        "UMask": "0x1",
11*f9900dd0SZhengjun Xing        "Unit": "cpu_atom"
12*f9900dd0SZhengjun Xing    },
13*f9900dd0SZhengjun Xing    {
14*f9900dd0SZhengjun Xing        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
15*f9900dd0SZhengjun Xing        "Counter": "0,1,2,3",
16*f9900dd0SZhengjun Xing        "EventCode": "0xB7",
17*f9900dd0SZhengjun Xing        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
18*f9900dd0SZhengjun Xing        "MSRIndex": "0x1a6,0x1a7",
19*f9900dd0SZhengjun Xing        "MSRValue": "0x10002",
20*f9900dd0SZhengjun Xing        "SampleAfterValue": "100003",
21*f9900dd0SZhengjun Xing        "UMask": "0x1",
22*f9900dd0SZhengjun Xing        "Unit": "cpu_atom"
23*f9900dd0SZhengjun Xing    },
24*f9900dd0SZhengjun Xing    {
25*f9900dd0SZhengjun Xing        "BriefDescription": "Counts streaming stores that have any type of response.",
26*f9900dd0SZhengjun Xing        "Counter": "0,1,2,3",
27*f9900dd0SZhengjun Xing        "EventCode": "0xB7",
28*f9900dd0SZhengjun Xing        "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
29*f9900dd0SZhengjun Xing        "MSRIndex": "0x1a6,0x1a7",
30*f9900dd0SZhengjun Xing        "MSRValue": "0x10800",
31*f9900dd0SZhengjun Xing        "SampleAfterValue": "100003",
32*f9900dd0SZhengjun Xing        "UMask": "0x1",
33*f9900dd0SZhengjun Xing        "Unit": "cpu_atom"
34*f9900dd0SZhengjun Xing    },
35*f9900dd0SZhengjun Xing    {
36*f9900dd0SZhengjun Xing        "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
37*f9900dd0SZhengjun Xing        "CollectPEBSRecord": "2",
38*f9900dd0SZhengjun Xing        "Counter": "0,1,2,3,4,5,6,7",
39*f9900dd0SZhengjun Xing        "EventCode": "0xc1",
40*f9900dd0SZhengjun Xing        "EventName": "ASSISTS.ANY",
41*f9900dd0SZhengjun Xing        "PEBScounters": "0,1,2,3,4,5,6,7",
42*f9900dd0SZhengjun Xing        "SampleAfterValue": "100003",
43*f9900dd0SZhengjun Xing        "UMask": "0x1f",
44*f9900dd0SZhengjun Xing        "Unit": "cpu_core"
45*f9900dd0SZhengjun Xing    },
46*f9900dd0SZhengjun Xing    {
47*f9900dd0SZhengjun Xing        "BriefDescription": "Count all other microcode assist beyond FP, AVX_TILE_MIX and A/D assists (counted by their own sub-events). This includes assists at uop writeback like AVX* load/store (non-FP) assists, Null Assist in SNC (due to lack of FP precision format convert with FMA3x3 uarch) or assists generated by ROB (like assists to due to Missprediction for FSW register - fixed in SNC)",
48*f9900dd0SZhengjun Xing        "CollectPEBSRecord": "2",
49*f9900dd0SZhengjun Xing        "Counter": "0,1,2,3,4,5,6,7",
50*f9900dd0SZhengjun Xing        "EventCode": "0xc1",
51*f9900dd0SZhengjun Xing        "EventName": "ASSISTS.HARDWARE",
52*f9900dd0SZhengjun Xing        "PEBScounters": "0,1,2,3,4,5,6,7",
53*f9900dd0SZhengjun Xing        "SampleAfterValue": "100003",
54*f9900dd0SZhengjun Xing        "UMask": "0x4",
55*f9900dd0SZhengjun Xing        "Unit": "cpu_core"
56*f9900dd0SZhengjun Xing    },
57*f9900dd0SZhengjun Xing    {
58*f9900dd0SZhengjun Xing        "BriefDescription": "TBD",
59*f9900dd0SZhengjun Xing        "CollectPEBSRecord": "2",
60*f9900dd0SZhengjun Xing        "Counter": "0,1,2,3,4,5,6,7",
61*f9900dd0SZhengjun Xing        "EventCode": "0xc1",
62*f9900dd0SZhengjun Xing        "EventName": "ASSISTS.PAGE_FAULT",
63*f9900dd0SZhengjun Xing        "PEBScounters": "0,1,2,3,4,5,6,7",
64*f9900dd0SZhengjun Xing        "SampleAfterValue": "1000003",
65*f9900dd0SZhengjun Xing        "UMask": "0x8",
66*f9900dd0SZhengjun Xing        "Unit": "cpu_core"
67*f9900dd0SZhengjun Xing    },
68*f9900dd0SZhengjun Xing    {
69*f9900dd0SZhengjun Xing        "BriefDescription": "TBD",
70*f9900dd0SZhengjun Xing        "CollectPEBSRecord": "2",
71*f9900dd0SZhengjun Xing        "Counter": "0,1,2,3",
72*f9900dd0SZhengjun Xing        "EventCode": "0x28",
73*f9900dd0SZhengjun Xing        "EventName": "CORE_POWER.LICENSE_1",
74*f9900dd0SZhengjun Xing        "PEBScounters": "0,1,2,3",
75*f9900dd0SZhengjun Xing        "SampleAfterValue": "200003",
76*f9900dd0SZhengjun Xing        "UMask": "0x2",
77*f9900dd0SZhengjun Xing        "Unit": "cpu_core"
78*f9900dd0SZhengjun Xing    },
79*f9900dd0SZhengjun Xing    {
80*f9900dd0SZhengjun Xing        "BriefDescription": "TBD",
81*f9900dd0SZhengjun Xing        "CollectPEBSRecord": "2",
82*f9900dd0SZhengjun Xing        "Counter": "0,1,2,3",
83*f9900dd0SZhengjun Xing        "EventCode": "0x28",
84*f9900dd0SZhengjun Xing        "EventName": "CORE_POWER.LICENSE_2",
85*f9900dd0SZhengjun Xing        "PEBScounters": "0,1,2,3",
86*f9900dd0SZhengjun Xing        "SampleAfterValue": "200003",
87*f9900dd0SZhengjun Xing        "UMask": "0x4",
88*f9900dd0SZhengjun Xing        "Unit": "cpu_core"
89*f9900dd0SZhengjun Xing    },
90*f9900dd0SZhengjun Xing    {
91*f9900dd0SZhengjun Xing        "BriefDescription": "TBD",
92*f9900dd0SZhengjun Xing        "CollectPEBSRecord": "2",
93*f9900dd0SZhengjun Xing        "Counter": "0,1,2,3",
94*f9900dd0SZhengjun Xing        "EventCode": "0x28",
95*f9900dd0SZhengjun Xing        "EventName": "CORE_POWER.LICENSE_3",
96*f9900dd0SZhengjun Xing        "PEBScounters": "0,1,2,3",
97*f9900dd0SZhengjun Xing        "SampleAfterValue": "200003",
98*f9900dd0SZhengjun Xing        "UMask": "0x8",
99*f9900dd0SZhengjun Xing        "Unit": "cpu_core"
100*f9900dd0SZhengjun Xing    },
101*f9900dd0SZhengjun Xing    {
102*f9900dd0SZhengjun Xing        "BriefDescription": "Counts demand data reads that have any type of response.",
103*f9900dd0SZhengjun Xing        "Counter": "0,1,2,3",
104*f9900dd0SZhengjun Xing        "EventCode": "0x2A,0x2B",
105*f9900dd0SZhengjun Xing        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
106*f9900dd0SZhengjun Xing        "MSRIndex": "0x1a6,0x1a7",
107*f9900dd0SZhengjun Xing        "MSRValue": "0x10001",
108*f9900dd0SZhengjun Xing        "SampleAfterValue": "100003",
109*f9900dd0SZhengjun Xing        "UMask": "0x1",
110*f9900dd0SZhengjun Xing        "Unit": "cpu_core"
111*f9900dd0SZhengjun Xing    },
112*f9900dd0SZhengjun Xing    {
113*f9900dd0SZhengjun Xing        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
114*f9900dd0SZhengjun Xing        "Counter": "0,1,2,3",
115*f9900dd0SZhengjun Xing        "EventCode": "0x2A,0x2B",
116*f9900dd0SZhengjun Xing        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
117*f9900dd0SZhengjun Xing        "MSRIndex": "0x1a6,0x1a7",
118*f9900dd0SZhengjun Xing        "MSRValue": "0x10002",
119*f9900dd0SZhengjun Xing        "SampleAfterValue": "100003",
120*f9900dd0SZhengjun Xing        "UMask": "0x1",
121*f9900dd0SZhengjun Xing        "Unit": "cpu_core"
122*f9900dd0SZhengjun Xing    },
123*f9900dd0SZhengjun Xing    {
124*f9900dd0SZhengjun Xing        "BriefDescription": "Counts streaming stores that have any type of response.",
125*f9900dd0SZhengjun Xing        "Counter": "0,1,2,3",
126*f9900dd0SZhengjun Xing        "EventCode": "0x2A,0x2B",
127*f9900dd0SZhengjun Xing        "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
128*f9900dd0SZhengjun Xing        "MSRIndex": "0x1a6,0x1a7",
129*f9900dd0SZhengjun Xing        "MSRValue": "0x10800",
130*f9900dd0SZhengjun Xing        "SampleAfterValue": "100003",
131*f9900dd0SZhengjun Xing        "UMask": "0x1",
132*f9900dd0SZhengjun Xing        "Unit": "cpu_core"
133*f9900dd0SZhengjun Xing    },
134*f9900dd0SZhengjun Xing    {
135*f9900dd0SZhengjun Xing        "BriefDescription": "TBD",
136*f9900dd0SZhengjun Xing        "CollectPEBSRecord": "2",
137*f9900dd0SZhengjun Xing        "Counter": "0,1,2,3",
138*f9900dd0SZhengjun Xing        "CounterMask": "1",
139*f9900dd0SZhengjun Xing        "EventCode": "0x2d",
140*f9900dd0SZhengjun Xing        "EventName": "XQ.FULL_CYCLES",
141*f9900dd0SZhengjun Xing        "PEBScounters": "0,1,2,3",
142*f9900dd0SZhengjun Xing        "SampleAfterValue": "1000003",
143*f9900dd0SZhengjun Xing        "UMask": "0x1",
144*f9900dd0SZhengjun Xing        "Unit": "cpu_core"
145*f9900dd0SZhengjun Xing    }
146*f9900dd0SZhengjun Xing]