1f9900dd0SZhengjun Xing[ 2f9900dd0SZhengjun Xing { 34c12f41aSZhengjun Xing "BriefDescription": "ASSISTS.HARDWARE", 4*17d4b192SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 54c12f41aSZhengjun Xing "EventCode": "0xc1", 64c12f41aSZhengjun Xing "EventName": "ASSISTS.HARDWARE", 74c12f41aSZhengjun Xing "SampleAfterValue": "100003", 84c12f41aSZhengjun Xing "UMask": "0x4", 94c12f41aSZhengjun Xing "Unit": "cpu_core" 104c12f41aSZhengjun Xing }, 114c12f41aSZhengjun Xing { 124c12f41aSZhengjun Xing "BriefDescription": "ASSISTS.PAGE_FAULT", 13*17d4b192SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 144c12f41aSZhengjun Xing "EventCode": "0xc1", 154c12f41aSZhengjun Xing "EventName": "ASSISTS.PAGE_FAULT", 164c12f41aSZhengjun Xing "SampleAfterValue": "1000003", 174c12f41aSZhengjun Xing "UMask": "0x8", 184c12f41aSZhengjun Xing "Unit": "cpu_core" 194c12f41aSZhengjun Xing }, 204c12f41aSZhengjun Xing { 214c12f41aSZhengjun Xing "BriefDescription": "CORE_POWER.LICENSE_1", 22*17d4b192SIan Rogers "Counter": "0,1,2,3", 234c12f41aSZhengjun Xing "EventCode": "0x28", 244c12f41aSZhengjun Xing "EventName": "CORE_POWER.LICENSE_1", 254c12f41aSZhengjun Xing "SampleAfterValue": "200003", 264c12f41aSZhengjun Xing "UMask": "0x2", 274c12f41aSZhengjun Xing "Unit": "cpu_core" 284c12f41aSZhengjun Xing }, 294c12f41aSZhengjun Xing { 304c12f41aSZhengjun Xing "BriefDescription": "CORE_POWER.LICENSE_2", 31*17d4b192SIan Rogers "Counter": "0,1,2,3", 324c12f41aSZhengjun Xing "EventCode": "0x28", 334c12f41aSZhengjun Xing "EventName": "CORE_POWER.LICENSE_2", 344c12f41aSZhengjun Xing "SampleAfterValue": "200003", 354c12f41aSZhengjun Xing "UMask": "0x4", 364c12f41aSZhengjun Xing "Unit": "cpu_core" 374c12f41aSZhengjun Xing }, 384c12f41aSZhengjun Xing { 394c12f41aSZhengjun Xing "BriefDescription": "CORE_POWER.LICENSE_3", 40*17d4b192SIan Rogers "Counter": "0,1,2,3", 414c12f41aSZhengjun Xing "EventCode": "0x28", 424c12f41aSZhengjun Xing "EventName": "CORE_POWER.LICENSE_3", 434c12f41aSZhengjun Xing "SampleAfterValue": "200003", 444c12f41aSZhengjun Xing "UMask": "0x8", 454c12f41aSZhengjun Xing "Unit": "cpu_core" 464c12f41aSZhengjun Xing }, 474c12f41aSZhengjun Xing { 482252ddf4SIan Rogers "BriefDescription": "This event is deprecated. [This event is alias to MISC_RETIRED.LBR_INSERTS]", 49*17d4b192SIan Rogers "Counter": "0,1,2,3,4,5", 502252ddf4SIan Rogers "Deprecated": "1", 512252ddf4SIan Rogers "EventCode": "0xe4", 522252ddf4SIan Rogers "EventName": "LBR_INSERTS.ANY", 532252ddf4SIan Rogers "PEBS": "1", 542252ddf4SIan Rogers "SampleAfterValue": "1000003", 552252ddf4SIan Rogers "UMask": "0x1", 562252ddf4SIan Rogers "Unit": "cpu_atom" 572252ddf4SIan Rogers }, 582252ddf4SIan Rogers { 59a80de066SIan Rogers "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have any type of response.", 60*17d4b192SIan Rogers "Counter": "0,1,2,3,4,5", 61a80de066SIan Rogers "EventCode": "0xB7", 62a80de066SIan Rogers "EventName": "OCR.COREWB_M.ANY_RESPONSE", 63a80de066SIan Rogers "MSRIndex": "0x1a6,0x1a7", 64a80de066SIan Rogers "MSRValue": "0x10008", 65a80de066SIan Rogers "SampleAfterValue": "100003", 66a80de066SIan Rogers "UMask": "0x1", 67a80de066SIan Rogers "Unit": "cpu_atom" 68a80de066SIan Rogers }, 69a80de066SIan Rogers { 70f9900dd0SZhengjun Xing "BriefDescription": "Counts demand data reads that have any type of response.", 71*17d4b192SIan Rogers "Counter": "0,1,2,3,4,5", 72f9900dd0SZhengjun Xing "EventCode": "0xB7", 73f9900dd0SZhengjun Xing "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", 74f9900dd0SZhengjun Xing "MSRIndex": "0x1a6,0x1a7", 75f9900dd0SZhengjun Xing "MSRValue": "0x10001", 76f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 77f9900dd0SZhengjun Xing "UMask": "0x1", 78f9900dd0SZhengjun Xing "Unit": "cpu_atom" 79f9900dd0SZhengjun Xing }, 80f9900dd0SZhengjun Xing { 81f9900dd0SZhengjun Xing "BriefDescription": "Counts demand data reads that have any type of response.", 82*17d4b192SIan Rogers "Counter": "0,1,2,3", 83f9900dd0SZhengjun Xing "EventCode": "0x2A,0x2B", 84f9900dd0SZhengjun Xing "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", 85f9900dd0SZhengjun Xing "MSRIndex": "0x1a6,0x1a7", 86f9900dd0SZhengjun Xing "MSRValue": "0x10001", 87f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 88f9900dd0SZhengjun Xing "UMask": "0x1", 89f9900dd0SZhengjun Xing "Unit": "cpu_core" 90f9900dd0SZhengjun Xing }, 91f9900dd0SZhengjun Xing { 92a80de066SIan Rogers "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 93*17d4b192SIan Rogers "Counter": "0,1,2,3", 94a80de066SIan Rogers "EventCode": "0x2A,0x2B", 95a80de066SIan Rogers "EventName": "OCR.DEMAND_DATA_RD.DRAM", 96a80de066SIan Rogers "MSRIndex": "0x1a6,0x1a7", 97a80de066SIan Rogers "MSRValue": "0x184000001", 98a80de066SIan Rogers "SampleAfterValue": "100003", 99a80de066SIan Rogers "UMask": "0x1", 100a80de066SIan Rogers "Unit": "cpu_core" 101a80de066SIan Rogers }, 102a80de066SIan Rogers { 1034c12f41aSZhengjun Xing "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", 104*17d4b192SIan Rogers "Counter": "0,1,2,3,4,5", 1054c12f41aSZhengjun Xing "EventCode": "0xB7", 1064c12f41aSZhengjun Xing "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", 1074c12f41aSZhengjun Xing "MSRIndex": "0x1a6,0x1a7", 1084c12f41aSZhengjun Xing "MSRValue": "0x10002", 1094c12f41aSZhengjun Xing "SampleAfterValue": "100003", 1104c12f41aSZhengjun Xing "UMask": "0x1", 1114c12f41aSZhengjun Xing "Unit": "cpu_atom" 1124c12f41aSZhengjun Xing }, 1134c12f41aSZhengjun Xing { 114f9900dd0SZhengjun Xing "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", 115*17d4b192SIan Rogers "Counter": "0,1,2,3", 116f9900dd0SZhengjun Xing "EventCode": "0x2A,0x2B", 117f9900dd0SZhengjun Xing "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", 118f9900dd0SZhengjun Xing "MSRIndex": "0x1a6,0x1a7", 119f9900dd0SZhengjun Xing "MSRValue": "0x10002", 120f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 121f9900dd0SZhengjun Xing "UMask": "0x1", 122f9900dd0SZhengjun Xing "Unit": "cpu_core" 123f9900dd0SZhengjun Xing }, 124f9900dd0SZhengjun Xing { 125f9900dd0SZhengjun Xing "BriefDescription": "Counts streaming stores that have any type of response.", 126*17d4b192SIan Rogers "Counter": "0,1,2,3,4,5", 1274c12f41aSZhengjun Xing "EventCode": "0xB7", 1284c12f41aSZhengjun Xing "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", 1294c12f41aSZhengjun Xing "MSRIndex": "0x1a6,0x1a7", 1304c12f41aSZhengjun Xing "MSRValue": "0x10800", 1314c12f41aSZhengjun Xing "SampleAfterValue": "100003", 1324c12f41aSZhengjun Xing "UMask": "0x1", 1334c12f41aSZhengjun Xing "Unit": "cpu_atom" 1344c12f41aSZhengjun Xing }, 1354c12f41aSZhengjun Xing { 1364c12f41aSZhengjun Xing "BriefDescription": "Counts streaming stores that have any type of response.", 137*17d4b192SIan Rogers "Counter": "0,1,2,3", 138f9900dd0SZhengjun Xing "EventCode": "0x2A,0x2B", 139f9900dd0SZhengjun Xing "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", 140f9900dd0SZhengjun Xing "MSRIndex": "0x1a6,0x1a7", 141f9900dd0SZhengjun Xing "MSRValue": "0x10800", 142f9900dd0SZhengjun Xing "SampleAfterValue": "100003", 143f9900dd0SZhengjun Xing "UMask": "0x1", 144f9900dd0SZhengjun Xing "Unit": "cpu_core" 145f9900dd0SZhengjun Xing }, 146f9900dd0SZhengjun Xing { 147a95ab294SIan Rogers "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.", 148*17d4b192SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 149a95ab294SIan Rogers "EventCode": "0xa5", 150a95ab294SIan Rogers "EventName": "RS.EMPTY", 1514c12f41aSZhengjun Xing "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)", 152a95ab294SIan Rogers "SampleAfterValue": "1000003", 153a95ab294SIan Rogers "UMask": "0x7", 154a95ab294SIan Rogers "Unit": "cpu_core" 155a95ab294SIan Rogers }, 156a95ab294SIan Rogers { 157a95ab294SIan Rogers "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", 158*17d4b192SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 159a95ab294SIan Rogers "CounterMask": "1", 160a95ab294SIan Rogers "EdgeDetect": "1", 161a95ab294SIan Rogers "EventCode": "0xa5", 162a95ab294SIan Rogers "EventName": "RS.EMPTY_COUNT", 163a95ab294SIan Rogers "Invert": "1", 1644c12f41aSZhengjun Xing "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)", 165a95ab294SIan Rogers "SampleAfterValue": "100003", 166a95ab294SIan Rogers "UMask": "0x7", 167a95ab294SIan Rogers "Unit": "cpu_core" 168a95ab294SIan Rogers }, 169a95ab294SIan Rogers { 170*17d4b192SIan Rogers "BriefDescription": "Cycles when Reservation Station (RS) is empty due to a resource in the back-end", 171*17d4b192SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 172*17d4b192SIan Rogers "EventCode": "0xa5", 173*17d4b192SIan Rogers "EventName": "RS.EMPTY_RESOURCE", 174*17d4b192SIan Rogers "SampleAfterValue": "1000003", 175*17d4b192SIan Rogers "UMask": "0x1", 176*17d4b192SIan Rogers "Unit": "cpu_core" 177*17d4b192SIan Rogers }, 178*17d4b192SIan Rogers { 179a95ab294SIan Rogers "BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY_COUNT", 180*17d4b192SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 181a95ab294SIan Rogers "CounterMask": "1", 1824c12f41aSZhengjun Xing "Deprecated": "1", 183a95ab294SIan Rogers "EdgeDetect": "1", 184a95ab294SIan Rogers "EventCode": "0xa5", 185a95ab294SIan Rogers "EventName": "RS_EMPTY.COUNT", 186a95ab294SIan Rogers "Invert": "1", 187a95ab294SIan Rogers "SampleAfterValue": "100003", 188a95ab294SIan Rogers "UMask": "0x7", 189a95ab294SIan Rogers "Unit": "cpu_core" 190a95ab294SIan Rogers }, 191a95ab294SIan Rogers { 192a95ab294SIan Rogers "BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY", 193*17d4b192SIan Rogers "Counter": "0,1,2,3,4,5,6,7", 1944c12f41aSZhengjun Xing "Deprecated": "1", 195a95ab294SIan Rogers "EventCode": "0xa5", 196a95ab294SIan Rogers "EventName": "RS_EMPTY.CYCLES", 197a95ab294SIan Rogers "SampleAfterValue": "1000003", 198a95ab294SIan Rogers "UMask": "0x7", 199a95ab294SIan Rogers "Unit": "cpu_core" 200a95ab294SIan Rogers }, 201a95ab294SIan Rogers { 202*17d4b192SIan Rogers "BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state)", 203*17d4b192SIan Rogers "Counter": "0,1,2,3,4,5", 204*17d4b192SIan Rogers "EventCode": "0x75", 205*17d4b192SIan Rogers "EventName": "SERIALIZATION.C01_MS_SCB", 206*17d4b192SIan Rogers "SampleAfterValue": "200003", 207*17d4b192SIan Rogers "UMask": "0x4", 208*17d4b192SIan Rogers "Unit": "cpu_atom" 209*17d4b192SIan Rogers }, 210*17d4b192SIan Rogers { 211588c8a2dSIan Rogers "BriefDescription": "Cycles the uncore cannot take further requests", 212*17d4b192SIan Rogers "Counter": "0,1,2,3", 213f9900dd0SZhengjun Xing "CounterMask": "1", 214f9900dd0SZhengjun Xing "EventCode": "0x2d", 215f9900dd0SZhengjun Xing "EventName": "XQ.FULL_CYCLES", 216588c8a2dSIan Rogers "PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).", 217f9900dd0SZhengjun Xing "SampleAfterValue": "1000003", 218f9900dd0SZhengjun Xing "UMask": "0x1", 219f9900dd0SZhengjun Xing "Unit": "cpu_core" 220f9900dd0SZhengjun Xing } 221f9900dd0SZhengjun Xing] 222