1[ 2 { 3 "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.", 4 "CollectPEBSRecord": "2", 5 "Counter": "0,1,2,3,4,5", 6 "EventCode": "0x05", 7 "EventName": "LD_HEAD.ANY_AT_RET", 8 "PEBScounters": "0,1,2,3,4,5", 9 "SampleAfterValue": "1000003", 10 "Speculative": "1", 11 "UMask": "0xff", 12 "Unit": "cpu_atom" 13 }, 14 { 15 "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.", 16 "CollectPEBSRecord": "2", 17 "Counter": "0,1,2,3,4,5", 18 "EventCode": "0x05", 19 "EventName": "LD_HEAD.L1_BOUND_AT_RET", 20 "PEBScounters": "0,1,2,3,4,5", 21 "SampleAfterValue": "1000003", 22 "Speculative": "1", 23 "UMask": "0xf4", 24 "Unit": "cpu_atom" 25 }, 26 { 27 "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.", 28 "CollectPEBSRecord": "2", 29 "Counter": "0,1,2,3,4,5", 30 "EventCode": "0x05", 31 "EventName": "LD_HEAD.OTHER_AT_RET", 32 "PEBScounters": "0,1,2,3,4,5", 33 "SampleAfterValue": "1000003", 34 "Speculative": "1", 35 "UMask": "0xc0", 36 "Unit": "cpu_atom" 37 }, 38 { 39 "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.", 40 "CollectPEBSRecord": "2", 41 "Counter": "0,1,2,3,4,5", 42 "EventCode": "0x05", 43 "EventName": "LD_HEAD.PGWALK_AT_RET", 44 "PEBScounters": "0,1,2,3,4,5", 45 "SampleAfterValue": "1000003", 46 "Speculative": "1", 47 "UMask": "0xa0", 48 "Unit": "cpu_atom" 49 }, 50 { 51 "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.", 52 "CollectPEBSRecord": "2", 53 "Counter": "0,1,2,3,4,5", 54 "EventCode": "0x05", 55 "EventName": "LD_HEAD.ST_ADDR_AT_RET", 56 "PEBScounters": "0,1,2,3,4,5", 57 "SampleAfterValue": "1000003", 58 "Speculative": "1", 59 "UMask": "0x84", 60 "Unit": "cpu_atom" 61 }, 62 { 63 "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.", 64 "CollectPEBSRecord": "2", 65 "Counter": "0,1,2,3,4,5", 66 "EventCode": "0xc3", 67 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 68 "PEBScounters": "0,1,2,3,4,5", 69 "SampleAfterValue": "20003", 70 "Speculative": "1", 71 "UMask": "0x2", 72 "Unit": "cpu_atom" 73 }, 74 { 75 "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", 76 "Counter": "0,1,2,3,4,5", 77 "EventCode": "0xB7", 78 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", 79 "MSRIndex": "0x1a6,0x1a7", 80 "MSRValue": "0x3F84400001", 81 "SampleAfterValue": "100003", 82 "UMask": "0x1", 83 "Unit": "cpu_atom" 84 }, 85 { 86 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", 87 "Counter": "0,1,2,3,4,5", 88 "EventCode": "0xB7", 89 "EventName": "OCR.DEMAND_RFO.L3_MISS", 90 "MSRIndex": "0x1a6,0x1a7", 91 "MSRValue": "0x3F84400002", 92 "SampleAfterValue": "100003", 93 "UMask": "0x1", 94 "Unit": "cpu_atom" 95 }, 96 { 97 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 98 "CollectPEBSRecord": "2", 99 "Counter": "0,1,2,3", 100 "CounterMask": "6", 101 "EventCode": "0xa3", 102 "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 103 "PEBScounters": "0,1,2,3", 104 "SampleAfterValue": "1000003", 105 "Speculative": "1", 106 "UMask": "0x6", 107 "Unit": "cpu_core" 108 }, 109 { 110 "BriefDescription": "Number of machine clears due to memory ordering conflicts.", 111 "CollectPEBSRecord": "2", 112 "Counter": "0,1,2,3,4,5,6,7", 113 "EventCode": "0xc3", 114 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 115 "PEBScounters": "0,1,2,3,4,5,6,7", 116 "SampleAfterValue": "100003", 117 "Speculative": "1", 118 "UMask": "0x2", 119 "Unit": "cpu_core" 120 }, 121 { 122 "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", 123 "CollectPEBSRecord": "2", 124 "Counter": "0,1,2,3", 125 "CounterMask": "2", 126 "EventCode": "0x47", 127 "EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", 128 "PEBScounters": "0,1,2,3", 129 "SampleAfterValue": "1000003", 130 "Speculative": "1", 131 "UMask": "0x2", 132 "Unit": "cpu_core" 133 }, 134 { 135 "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", 136 "CollectPEBSRecord": "2", 137 "Counter": "0,1,2,3", 138 "CounterMask": "3", 139 "EventCode": "0x47", 140 "EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS", 141 "PEBScounters": "0,1,2,3", 142 "SampleAfterValue": "1000003", 143 "Speculative": "1", 144 "UMask": "0x3", 145 "Unit": "cpu_core" 146 }, 147 { 148 "BriefDescription": "MEMORY_ACTIVITY.STALLS_L2_MISS", 149 "CollectPEBSRecord": "2", 150 "Counter": "0,1,2,3", 151 "CounterMask": "5", 152 "EventCode": "0x47", 153 "EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS", 154 "PEBScounters": "0,1,2,3", 155 "SampleAfterValue": "1000003", 156 "Speculative": "1", 157 "UMask": "0x5", 158 "Unit": "cpu_core" 159 }, 160 { 161 "BriefDescription": "MEMORY_ACTIVITY.STALLS_L3_MISS", 162 "CollectPEBSRecord": "2", 163 "Counter": "0,1,2,3", 164 "CounterMask": "9", 165 "EventCode": "0x47", 166 "EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS", 167 "PEBScounters": "0,1,2,3", 168 "SampleAfterValue": "1000003", 169 "Speculative": "1", 170 "UMask": "0x9", 171 "Unit": "cpu_core" 172 }, 173 { 174 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 175 "CollectPEBSRecord": "2", 176 "Counter": "1,2,3,4,5,6,7", 177 "Data_LA": "1", 178 "EventCode": "0xcd", 179 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 180 "MSRIndex": "0x3F6", 181 "MSRValue": "0x80", 182 "PEBS": "2", 183 "PEBScounters": "1,2,3,4,5,6,7", 184 "SampleAfterValue": "1009", 185 "TakenAlone": "1", 186 "UMask": "0x1", 187 "Unit": "cpu_core" 188 }, 189 { 190 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 191 "CollectPEBSRecord": "2", 192 "Counter": "1,2,3,4,5,6,7", 193 "Data_LA": "1", 194 "EventCode": "0xcd", 195 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 196 "MSRIndex": "0x3F6", 197 "MSRValue": "0x10", 198 "PEBS": "2", 199 "PEBScounters": "1,2,3,4,5,6,7", 200 "SampleAfterValue": "20011", 201 "TakenAlone": "1", 202 "UMask": "0x1", 203 "Unit": "cpu_core" 204 }, 205 { 206 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 207 "CollectPEBSRecord": "2", 208 "Counter": "1,2,3,4,5,6,7", 209 "Data_LA": "1", 210 "EventCode": "0xcd", 211 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 212 "MSRIndex": "0x3F6", 213 "MSRValue": "0x100", 214 "PEBS": "2", 215 "PEBScounters": "1,2,3,4,5,6,7", 216 "SampleAfterValue": "503", 217 "TakenAlone": "1", 218 "UMask": "0x1", 219 "Unit": "cpu_core" 220 }, 221 { 222 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 223 "CollectPEBSRecord": "2", 224 "Counter": "1,2,3,4,5,6,7", 225 "Data_LA": "1", 226 "EventCode": "0xcd", 227 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 228 "MSRIndex": "0x3F6", 229 "MSRValue": "0x20", 230 "PEBS": "2", 231 "PEBScounters": "1,2,3,4,5,6,7", 232 "SampleAfterValue": "100007", 233 "TakenAlone": "1", 234 "UMask": "0x1", 235 "Unit": "cpu_core" 236 }, 237 { 238 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 239 "CollectPEBSRecord": "2", 240 "Counter": "1,2,3,4,5,6,7", 241 "Data_LA": "1", 242 "EventCode": "0xcd", 243 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 244 "MSRIndex": "0x3F6", 245 "MSRValue": "0x4", 246 "PEBS": "2", 247 "PEBScounters": "1,2,3,4,5,6,7", 248 "SampleAfterValue": "100003", 249 "TakenAlone": "1", 250 "UMask": "0x1", 251 "Unit": "cpu_core" 252 }, 253 { 254 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 255 "CollectPEBSRecord": "2", 256 "Counter": "1,2,3,4,5,6,7", 257 "Data_LA": "1", 258 "EventCode": "0xcd", 259 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 260 "MSRIndex": "0x3F6", 261 "MSRValue": "0x200", 262 "PEBS": "2", 263 "PEBScounters": "1,2,3,4,5,6,7", 264 "SampleAfterValue": "101", 265 "TakenAlone": "1", 266 "UMask": "0x1", 267 "Unit": "cpu_core" 268 }, 269 { 270 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 271 "CollectPEBSRecord": "2", 272 "Counter": "1,2,3,4,5,6,7", 273 "Data_LA": "1", 274 "EventCode": "0xcd", 275 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 276 "MSRIndex": "0x3F6", 277 "MSRValue": "0x40", 278 "PEBS": "2", 279 "PEBScounters": "1,2,3,4,5,6,7", 280 "SampleAfterValue": "2003", 281 "TakenAlone": "1", 282 "UMask": "0x1", 283 "Unit": "cpu_core" 284 }, 285 { 286 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 287 "CollectPEBSRecord": "2", 288 "Counter": "1,2,3,4,5,6,7", 289 "Data_LA": "1", 290 "EventCode": "0xcd", 291 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 292 "MSRIndex": "0x3F6", 293 "MSRValue": "0x8", 294 "PEBS": "2", 295 "PEBScounters": "1,2,3,4,5,6,7", 296 "SampleAfterValue": "50021", 297 "TakenAlone": "1", 298 "UMask": "0x1", 299 "Unit": "cpu_core" 300 }, 301 { 302 "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.", 303 "CollectPEBSRecord": "2", 304 "Data_LA": "1", 305 "EventCode": "0xcd", 306 "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", 307 "PEBS": "2", 308 "SampleAfterValue": "1000003", 309 "UMask": "0x2", 310 "Unit": "cpu_core" 311 }, 312 { 313 "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", 314 "Counter": "0,1,2,3,4,5,6,7", 315 "EventCode": "0x2A,0x2B", 316 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", 317 "MSRIndex": "0x1a6,0x1a7", 318 "MSRValue": "0x3FBFC00001", 319 "SampleAfterValue": "100003", 320 "UMask": "0x1", 321 "Unit": "cpu_core" 322 }, 323 { 324 "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", 325 "Counter": "0,1,2,3,4,5,6,7", 326 "EventCode": "0x2A,0x2B", 327 "EventName": "OCR.DEMAND_RFO.L3_MISS", 328 "MSRIndex": "0x1a6,0x1a7", 329 "MSRValue": "0x3FBFC00002", 330 "SampleAfterValue": "100003", 331 "UMask": "0x1", 332 "Unit": "cpu_core" 333 } 334] 335