1[ 2 { 3 "BriefDescription": "ARITH.FPDIV_ACTIVE", 4 "CounterMask": "1", 5 "EventCode": "0xb0", 6 "EventName": "ARITH.FPDIV_ACTIVE", 7 "SampleAfterValue": "1000003", 8 "UMask": "0x1", 9 "Unit": "cpu_core" 10 }, 11 { 12 "BriefDescription": "Counts all microcode FP assists.", 13 "EventCode": "0xc1", 14 "EventName": "ASSISTS.FP", 15 "PublicDescription": "Counts all microcode Floating Point assists.", 16 "SampleAfterValue": "100003", 17 "UMask": "0x2", 18 "Unit": "cpu_core" 19 }, 20 { 21 "BriefDescription": "ASSISTS.SSE_AVX_MIX", 22 "EventCode": "0xc1", 23 "EventName": "ASSISTS.SSE_AVX_MIX", 24 "SampleAfterValue": "1000003", 25 "UMask": "0x10", 26 "Unit": "cpu_core" 27 }, 28 { 29 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]", 30 "EventCode": "0xb3", 31 "EventName": "FP_ARITH_DISPATCHED.PORT_0", 32 "SampleAfterValue": "2000003", 33 "UMask": "0x1", 34 "Unit": "cpu_core" 35 }, 36 { 37 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]", 38 "EventCode": "0xb3", 39 "EventName": "FP_ARITH_DISPATCHED.PORT_1", 40 "SampleAfterValue": "2000003", 41 "UMask": "0x2", 42 "Unit": "cpu_core" 43 }, 44 { 45 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]", 46 "EventCode": "0xb3", 47 "EventName": "FP_ARITH_DISPATCHED.PORT_5", 48 "SampleAfterValue": "2000003", 49 "UMask": "0x4", 50 "Unit": "cpu_core" 51 }, 52 { 53 "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]", 54 "EventCode": "0xb3", 55 "EventName": "FP_ARITH_DISPATCHED.V0", 56 "SampleAfterValue": "2000003", 57 "UMask": "0x1", 58 "Unit": "cpu_core" 59 }, 60 { 61 "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]", 62 "EventCode": "0xb3", 63 "EventName": "FP_ARITH_DISPATCHED.V1", 64 "SampleAfterValue": "2000003", 65 "UMask": "0x2", 66 "Unit": "cpu_core" 67 }, 68 { 69 "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]", 70 "EventCode": "0xb3", 71 "EventName": "FP_ARITH_DISPATCHED.V2", 72 "SampleAfterValue": "2000003", 73 "UMask": "0x4", 74 "Unit": "cpu_core" 75 }, 76 { 77 "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 78 "EventCode": "0xc7", 79 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 80 "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 81 "SampleAfterValue": "100003", 82 "UMask": "0x4", 83 "Unit": "cpu_core" 84 }, 85 { 86 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 87 "EventCode": "0xc7", 88 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 89 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 90 "SampleAfterValue": "100003", 91 "UMask": "0x8", 92 "Unit": "cpu_core" 93 }, 94 { 95 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 96 "EventCode": "0xc7", 97 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 98 "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 99 "SampleAfterValue": "100003", 100 "UMask": "0x10", 101 "Unit": "cpu_core" 102 }, 103 { 104 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 105 "EventCode": "0xc7", 106 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 107 "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 108 "SampleAfterValue": "100003", 109 "UMask": "0x20", 110 "Unit": "cpu_core" 111 }, 112 { 113 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", 114 "EventCode": "0xc7", 115 "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", 116 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 117 "SampleAfterValue": "100003", 118 "UMask": "0x18", 119 "Unit": "cpu_core" 120 }, 121 { 122 "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", 123 "EventCode": "0xc7", 124 "EventName": "FP_ARITH_INST_RETIRED.SCALAR", 125 "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 126 "SampleAfterValue": "1000003", 127 "UMask": "0x3", 128 "Unit": "cpu_core" 129 }, 130 { 131 "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 132 "EventCode": "0xc7", 133 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 134 "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 135 "SampleAfterValue": "100003", 136 "UMask": "0x1", 137 "Unit": "cpu_core" 138 }, 139 { 140 "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 141 "EventCode": "0xc7", 142 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 143 "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 144 "SampleAfterValue": "100003", 145 "UMask": "0x2", 146 "Unit": "cpu_core" 147 }, 148 { 149 "BriefDescription": "Number of any Vector retired FP arithmetic instructions", 150 "EventCode": "0xc7", 151 "EventName": "FP_ARITH_INST_RETIRED.VECTOR", 152 "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 153 "SampleAfterValue": "1000003", 154 "UMask": "0xfc", 155 "Unit": "cpu_core" 156 }, 157 { 158 "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", 159 "EventCode": "0xc3", 160 "EventName": "MACHINE_CLEARS.FP_ASSIST", 161 "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.", 162 "SampleAfterValue": "20003", 163 "UMask": "0x4", 164 "Unit": "cpu_atom" 165 }, 166 { 167 "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).", 168 "EventCode": "0xc2", 169 "EventName": "UOPS_RETIRED.FPDIV", 170 "PEBS": "1", 171 "SampleAfterValue": "2000003", 172 "UMask": "0x8", 173 "Unit": "cpu_atom" 174 } 175] 176