1[ 2 { 3 "BriefDescription": "Counts the number of cycles the floating point divider is in the loop stage.", 4 "Counter": "0,1,2,3,4,5", 5 "EventCode": "0xcd", 6 "EventName": "ARITH.FPDIV_ACTIVE", 7 "SampleAfterValue": "1000003", 8 "UMask": "0x2", 9 "Unit": "cpu_atom" 10 }, 11 { 12 "BriefDescription": "ARITH.FPDIV_ACTIVE", 13 "Counter": "0,1,2,3,4,5,6,7", 14 "CounterMask": "1", 15 "EventCode": "0xb0", 16 "EventName": "ARITH.FPDIV_ACTIVE", 17 "PublicDescription": "ARITH.FPDIV_ACTIVE Available PDIST counters: 0", 18 "SampleAfterValue": "1000003", 19 "UMask": "0x1", 20 "Unit": "cpu_core" 21 }, 22 { 23 "BriefDescription": "Counts the number of floating point divider uops executed per cycle.", 24 "Counter": "0,1,2,3,4,5", 25 "EventCode": "0xcd", 26 "EventName": "ARITH.FPDIV_UOPS", 27 "SampleAfterValue": "1000003", 28 "UMask": "0x8", 29 "Unit": "cpu_atom" 30 }, 31 { 32 "BriefDescription": "Counts all microcode FP assists.", 33 "Counter": "0,1,2,3,4,5,6,7", 34 "EventCode": "0xc1", 35 "EventName": "ASSISTS.FP", 36 "PublicDescription": "Counts all microcode Floating Point assists. Available PDIST counters: 0", 37 "SampleAfterValue": "100003", 38 "UMask": "0x2", 39 "Unit": "cpu_core" 40 }, 41 { 42 "BriefDescription": "ASSISTS.SSE_AVX_MIX", 43 "Counter": "0,1,2,3,4,5,6,7", 44 "EventCode": "0xc1", 45 "EventName": "ASSISTS.SSE_AVX_MIX", 46 "PublicDescription": "ASSISTS.SSE_AVX_MIX Available PDIST counters: 0", 47 "SampleAfterValue": "1000003", 48 "UMask": "0x10", 49 "Unit": "cpu_core" 50 }, 51 { 52 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]", 53 "Counter": "0,1,2,3,4,5,6,7", 54 "EventCode": "0xb3", 55 "EventName": "FP_ARITH_DISPATCHED.PORT_0", 56 "PublicDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0] Available PDIST counters: 0", 57 "SampleAfterValue": "2000003", 58 "UMask": "0x1", 59 "Unit": "cpu_core" 60 }, 61 { 62 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]", 63 "Counter": "0,1,2,3,4,5,6,7", 64 "EventCode": "0xb3", 65 "EventName": "FP_ARITH_DISPATCHED.PORT_1", 66 "PublicDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1] Available PDIST counters: 0", 67 "SampleAfterValue": "2000003", 68 "UMask": "0x2", 69 "Unit": "cpu_core" 70 }, 71 { 72 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]", 73 "Counter": "0,1,2,3,4,5,6,7", 74 "EventCode": "0xb3", 75 "EventName": "FP_ARITH_DISPATCHED.PORT_5", 76 "PublicDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2] Available PDIST counters: 0", 77 "SampleAfterValue": "2000003", 78 "UMask": "0x4", 79 "Unit": "cpu_core" 80 }, 81 { 82 "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]", 83 "Counter": "0,1,2,3,4,5,6,7", 84 "EventCode": "0xb3", 85 "EventName": "FP_ARITH_DISPATCHED.V0", 86 "PublicDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0] Available PDIST counters: 0", 87 "SampleAfterValue": "2000003", 88 "UMask": "0x1", 89 "Unit": "cpu_core" 90 }, 91 { 92 "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]", 93 "Counter": "0,1,2,3,4,5,6,7", 94 "EventCode": "0xb3", 95 "EventName": "FP_ARITH_DISPATCHED.V1", 96 "PublicDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1] Available PDIST counters: 0", 97 "SampleAfterValue": "2000003", 98 "UMask": "0x2", 99 "Unit": "cpu_core" 100 }, 101 { 102 "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]", 103 "Counter": "0,1,2,3,4,5,6,7", 104 "EventCode": "0xb3", 105 "EventName": "FP_ARITH_DISPATCHED.V2", 106 "PublicDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5] Available PDIST counters: 0", 107 "SampleAfterValue": "2000003", 108 "UMask": "0x4", 109 "Unit": "cpu_core" 110 }, 111 { 112 "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 113 "Counter": "0,1,2,3,4,5,6,7", 114 "EventCode": "0xc7", 115 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 116 "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 117 "SampleAfterValue": "100003", 118 "UMask": "0x4", 119 "Unit": "cpu_core" 120 }, 121 { 122 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 123 "Counter": "0,1,2,3,4,5,6,7", 124 "EventCode": "0xc7", 125 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 126 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 127 "SampleAfterValue": "100003", 128 "UMask": "0x8", 129 "Unit": "cpu_core" 130 }, 131 { 132 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 133 "Counter": "0,1,2,3,4,5,6,7", 134 "EventCode": "0xc7", 135 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 136 "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 137 "SampleAfterValue": "100003", 138 "UMask": "0x10", 139 "Unit": "cpu_core" 140 }, 141 { 142 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 143 "Counter": "0,1,2,3,4,5,6,7", 144 "EventCode": "0xc7", 145 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 146 "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 147 "SampleAfterValue": "100003", 148 "UMask": "0x20", 149 "Unit": "cpu_core" 150 }, 151 { 152 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", 153 "Counter": "0,1,2,3,4,5,6,7", 154 "EventCode": "0xc7", 155 "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", 156 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 157 "SampleAfterValue": "100003", 158 "UMask": "0x18", 159 "Unit": "cpu_core" 160 }, 161 { 162 "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", 163 "Counter": "0,1,2,3,4,5,6,7", 164 "EventCode": "0xc7", 165 "EventName": "FP_ARITH_INST_RETIRED.SCALAR", 166 "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 167 "SampleAfterValue": "1000003", 168 "UMask": "0x3", 169 "Unit": "cpu_core" 170 }, 171 { 172 "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 173 "Counter": "0,1,2,3,4,5,6,7", 174 "EventCode": "0xc7", 175 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 176 "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 177 "SampleAfterValue": "100003", 178 "UMask": "0x1", 179 "Unit": "cpu_core" 180 }, 181 { 182 "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 183 "Counter": "0,1,2,3,4,5,6,7", 184 "EventCode": "0xc7", 185 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 186 "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 187 "SampleAfterValue": "100003", 188 "UMask": "0x2", 189 "Unit": "cpu_core" 190 }, 191 { 192 "BriefDescription": "Number of any Vector retired FP arithmetic instructions", 193 "Counter": "0,1,2,3,4,5,6,7", 194 "EventCode": "0xc7", 195 "EventName": "FP_ARITH_INST_RETIRED.VECTOR", 196 "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 197 "SampleAfterValue": "1000003", 198 "UMask": "0xfc", 199 "Unit": "cpu_core" 200 }, 201 { 202 "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", 203 "Counter": "0,1,2,3,4,5", 204 "EventCode": "0xc3", 205 "EventName": "MACHINE_CLEARS.FP_ASSIST", 206 "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.", 207 "SampleAfterValue": "20003", 208 "UMask": "0x4", 209 "Unit": "cpu_atom" 210 }, 211 { 212 "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).", 213 "Counter": "0,1,2,3,4,5", 214 "EventCode": "0xc2", 215 "EventName": "UOPS_RETIRED.FPDIV", 216 "SampleAfterValue": "2000003", 217 "UMask": "0x8", 218 "Unit": "cpu_atom" 219 } 220] 221