1[ 2 { 3 "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", 4 "CollectPEBSRecord": "2", 5 "Counter": "0,1,2,3,4,5", 6 "EventCode": "0xc3", 7 "EventName": "MACHINE_CLEARS.FP_ASSIST", 8 "PEBScounters": "0,1,2,3,4,5", 9 "SampleAfterValue": "20003", 10 "Speculative": "1", 11 "UMask": "0x4", 12 "Unit": "cpu_atom" 13 }, 14 { 15 "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).", 16 "CollectPEBSRecord": "2", 17 "Counter": "0,1,2,3,4,5", 18 "EventCode": "0xc2", 19 "EventName": "UOPS_RETIRED.FPDIV", 20 "PEBS": "1", 21 "PEBScounters": "0,1,2,3,4,5", 22 "SampleAfterValue": "2000003", 23 "UMask": "0x8", 24 "Unit": "cpu_atom" 25 }, 26 { 27 "BriefDescription": "ARITH.FPDIV_ACTIVE", 28 "CollectPEBSRecord": "2", 29 "Counter": "0,1,2,3,4,5,6,7", 30 "CounterMask": "1", 31 "EventCode": "0xb0", 32 "EventName": "ARITH.FPDIV_ACTIVE", 33 "PEBScounters": "0,1,2,3,4,5,6,7", 34 "SampleAfterValue": "1000003", 35 "Speculative": "1", 36 "UMask": "0x1", 37 "Unit": "cpu_core" 38 }, 39 { 40 "BriefDescription": "Counts all microcode FP assists.", 41 "CollectPEBSRecord": "2", 42 "Counter": "0,1,2,3,4,5,6,7", 43 "EventCode": "0xc1", 44 "EventName": "ASSISTS.FP", 45 "PEBScounters": "0,1,2,3,4,5,6,7", 46 "SampleAfterValue": "100003", 47 "Speculative": "1", 48 "UMask": "0x2", 49 "Unit": "cpu_core" 50 }, 51 { 52 "BriefDescription": "ASSISTS.SSE_AVX_MIX", 53 "CollectPEBSRecord": "2", 54 "Counter": "0,1,2,3,4,5,6,7", 55 "EventCode": "0xc1", 56 "EventName": "ASSISTS.SSE_AVX_MIX", 57 "PEBScounters": "0,1,2,3,4,5,6,7", 58 "SampleAfterValue": "1000003", 59 "Speculative": "1", 60 "UMask": "0x10", 61 "Unit": "cpu_core" 62 }, 63 { 64 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0", 65 "CollectPEBSRecord": "2", 66 "Counter": "0,1,2,3,4,5,6,7", 67 "EventCode": "0xb3", 68 "EventName": "FP_ARITH_DISPATCHED.PORT_0", 69 "PEBScounters": "0,1,2,3,4,5,6,7", 70 "SampleAfterValue": "2000003", 71 "Speculative": "1", 72 "UMask": "0x1", 73 "Unit": "cpu_core" 74 }, 75 { 76 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1", 77 "CollectPEBSRecord": "2", 78 "Counter": "0,1,2,3,4,5,6,7", 79 "EventCode": "0xb3", 80 "EventName": "FP_ARITH_DISPATCHED.PORT_1", 81 "PEBScounters": "0,1,2,3,4,5,6,7", 82 "SampleAfterValue": "2000003", 83 "Speculative": "1", 84 "UMask": "0x2", 85 "Unit": "cpu_core" 86 }, 87 { 88 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5", 89 "CollectPEBSRecord": "2", 90 "Counter": "0,1,2,3,4,5,6,7", 91 "EventCode": "0xb3", 92 "EventName": "FP_ARITH_DISPATCHED.PORT_5", 93 "PEBScounters": "0,1,2,3,4,5,6,7", 94 "SampleAfterValue": "2000003", 95 "Speculative": "1", 96 "UMask": "0x4", 97 "Unit": "cpu_core" 98 }, 99 { 100 "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 101 "CollectPEBSRecord": "2", 102 "Counter": "0,1,2,3,4,5,6,7", 103 "EventCode": "0xc7", 104 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 105 "PEBScounters": "0,1,2,3,4,5,6,7", 106 "SampleAfterValue": "100003", 107 "UMask": "0x4", 108 "Unit": "cpu_core" 109 }, 110 { 111 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 112 "CollectPEBSRecord": "2", 113 "Counter": "0,1,2,3,4,5,6,7", 114 "EventCode": "0xc7", 115 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 116 "PEBScounters": "0,1,2,3,4,5,6,7", 117 "SampleAfterValue": "100003", 118 "UMask": "0x8", 119 "Unit": "cpu_core" 120 }, 121 { 122 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 123 "CollectPEBSRecord": "2", 124 "Counter": "0,1,2,3,4,5,6,7", 125 "EventCode": "0xc7", 126 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 127 "PEBScounters": "0,1,2,3,4,5,6,7", 128 "SampleAfterValue": "100003", 129 "UMask": "0x10", 130 "Unit": "cpu_core" 131 }, 132 { 133 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 134 "CollectPEBSRecord": "2", 135 "Counter": "0,1,2,3,4,5,6,7", 136 "EventCode": "0xc7", 137 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 138 "PEBScounters": "0,1,2,3,4,5,6,7", 139 "SampleAfterValue": "100003", 140 "UMask": "0x20", 141 "Unit": "cpu_core" 142 }, 143 { 144 "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 145 "CollectPEBSRecord": "2", 146 "Counter": "0,1,2,3,4,5,6,7", 147 "EventCode": "0xc7", 148 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 149 "PEBScounters": "0,1,2,3,4,5,6,7", 150 "SampleAfterValue": "100003", 151 "UMask": "0x1", 152 "Unit": "cpu_core" 153 }, 154 { 155 "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 156 "CollectPEBSRecord": "2", 157 "Counter": "0,1,2,3,4,5,6,7", 158 "EventCode": "0xc7", 159 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 160 "PEBScounters": "0,1,2,3,4,5,6,7", 161 "SampleAfterValue": "100003", 162 "UMask": "0x2", 163 "Unit": "cpu_core" 164 } 165] 166