xref: /linux/tools/perf/pmu-events/arch/test/test_soc/cpu/other.json (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1[
2    {
3        "EventCode": "0x6",
4        "Counter": "0,1",
5        "UMask": "0x80",
6        "EventName": "SEGMENT_REG_LOADS.ANY",
7        "SampleAfterValue": "200000",
8        "BriefDescription": "Number of segment register loads."
9    },
10    {
11        "EventCode": "0x9",
12        "Counter": "0,1",
13        "UMask": "0x20",
14        "EventName": "DISPATCH_BLOCKED.ANY",
15        "SampleAfterValue": "200000",
16        "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason"
17    },
18    {
19        "EventCode": "0x3A",
20        "Counter": "0,1",
21        "UMask": "0x0",
22        "EventName": "EIST_TRANS",
23        "SampleAfterValue": "200000",
24        "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions"
25    }
26]