1*508b2289SThomas Richter[ 2*508b2289SThomas Richter { 3*508b2289SThomas Richter "Unit": "CPU-M-CF", 4*508b2289SThomas Richter "EventCode": "0", 5*508b2289SThomas Richter "EventName": "CPU_CYCLES", 6*508b2289SThomas Richter "BriefDescription": "Cycle Count", 7*508b2289SThomas Richter "PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state." 8*508b2289SThomas Richter }, 9*508b2289SThomas Richter { 10*508b2289SThomas Richter "Unit": "CPU-M-CF", 11*508b2289SThomas Richter "EventCode": "1", 12*508b2289SThomas Richter "EventName": "INSTRUCTIONS", 13*508b2289SThomas Richter "BriefDescription": "Instruction Count", 14*508b2289SThomas Richter "PublicDescription": "This counter counts the total number of instructions executed by the CPU." 15*508b2289SThomas Richter }, 16*508b2289SThomas Richter { 17*508b2289SThomas Richter "Unit": "CPU-M-CF", 18*508b2289SThomas Richter "EventCode": "2", 19*508b2289SThomas Richter "EventName": "L1I_DIR_WRITES", 20*508b2289SThomas Richter "BriefDescription": "Level-1 I-Cache Directory Write Count", 21*508b2289SThomas Richter "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes." 22*508b2289SThomas Richter }, 23*508b2289SThomas Richter { 24*508b2289SThomas Richter "Unit": "CPU-M-CF", 25*508b2289SThomas Richter "EventCode": "3", 26*508b2289SThomas Richter "EventName": "L1I_PENALTY_CYCLES", 27*508b2289SThomas Richter "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", 28*508b2289SThomas Richter "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache." 29*508b2289SThomas Richter }, 30*508b2289SThomas Richter { 31*508b2289SThomas Richter "Unit": "CPU-M-CF", 32*508b2289SThomas Richter "EventCode": "4", 33*508b2289SThomas Richter "EventName": "L1D_DIR_WRITES", 34*508b2289SThomas Richter "BriefDescription": "Level-1 D-Cache Directory Write Count", 35*508b2289SThomas Richter "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes." 36*508b2289SThomas Richter }, 37*508b2289SThomas Richter { 38*508b2289SThomas Richter "Unit": "CPU-M-CF", 39*508b2289SThomas Richter "EventCode": "5", 40*508b2289SThomas Richter "EventName": "L1D_PENALTY_CYCLES", 41*508b2289SThomas Richter "BriefDescription": "Level-1 D-Cache Penalty Cycle Count", 42*508b2289SThomas Richter "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache." 43*508b2289SThomas Richter }, 44*508b2289SThomas Richter { 45*508b2289SThomas Richter "Unit": "CPU-M-CF", 46*508b2289SThomas Richter "EventCode": "32", 47*508b2289SThomas Richter "EventName": "PROBLEM_STATE_CPU_CYCLES", 48*508b2289SThomas Richter "BriefDescription": "Problem-State Cycle Count", 49*508b2289SThomas Richter "PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state." 50*508b2289SThomas Richter }, 51*508b2289SThomas Richter { 52*508b2289SThomas Richter "Unit": "CPU-M-CF", 53*508b2289SThomas Richter "EventCode": "33", 54*508b2289SThomas Richter "EventName": "PROBLEM_STATE_INSTRUCTIONS", 55*508b2289SThomas Richter "BriefDescription": "Problem-State Instruction Count", 56*508b2289SThomas Richter "PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state." 57*508b2289SThomas Richter } 58*508b2289SThomas Richter] 59