1[ 2 { 3 "BriefDescription": "Transaction count", 4 "MetricName": "transaction", 5 "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL if has_event(TX_C_TEND) else 0" 6 }, 7 { 8 "BriefDescription": "Cycles per Instruction", 9 "MetricName": "cpi", 10 "MetricExpr": "CPU_CYCLES / INSTRUCTIONS if has_event(INSTRUCTIONS) else 0" 11 }, 12 { 13 "BriefDescription": "Problem State Instruction Ratio", 14 "MetricName": "prbstate", 15 "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0" 16 }, 17 { 18 "BriefDescription": "Level One Miss per 100 Instructions", 19 "MetricName": "l1mp", 20 "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0" 21 }, 22 { 23 "BriefDescription": "Percentage sourced from Level 2 cache", 24 "MetricName": "l2p", 25 "MetricExpr": "((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ) else 0" 26 }, 27 { 28 "BriefDescription": "Percentage sourced from Level 3 on same chip cache", 29 "MetricName": "l3p", 30 "MetricExpr": "((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + DCW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW_ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ_CHIP_HIT) else 0" 31 }, 32 { 33 "BriefDescription": "Percentage sourced from Level 4 Local cache on same book", 34 "MetricName": "l4lp", 35 "MetricExpr": "((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_ON_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + IDCW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDCW_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ_DRAWER_HIT) else 0" 36 }, 37 { 38 "BriefDescription": "Percentage sourced from Level 4 Remote cache on different book", 39 "MetricName": "l4rp", 40 "MetricExpr": "((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAWER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_OFF_DRAWER) else 0" 41 }, 42 { 43 "BriefDescription": "Percentage sourced from memory", 44 "MetricName": "memp", 45 "MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_ON_CHIP_MEMORY) else 0" 46 }, 47 { 48 "BriefDescription": "Cycles per Instructions from Finite cache/memory", 49 "MetricName": "finite_cpi", 50 "MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS if has_event(L1C_TLB2_MISSES) else 0" 51 }, 52 { 53 "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1", 54 "MetricName": "est_cpi", 55 "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS) if has_event(INSTRUCTIONS) else 0" 56 }, 57 { 58 "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss", 59 "MetricName": "scpl1m", 60 "MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES) if has_event(L1C_TLB2_MISSES) else 0" 61 }, 62 { 63 "BriefDescription": "Estimated TLB CPU percentage of Total CPU", 64 "MetricName": "tlb_percent", 65 "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100 if has_event(CPU_CYCLES) else 0" 66 }, 67 { 68 "BriefDescription": "Estimated Cycles per TLB Miss", 69 "MetricName": "tlb_miss", 70 "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) if has_event(DTLB2_MISSES) else 0" 71 } 72] 73