1*7f76b311SThomas Richter[ 2*7f76b311SThomas Richter { 3*7f76b311SThomas Richter "Unit": "CPU-M-CF", 4*7f76b311SThomas Richter "EventCode": "0", 5*7f76b311SThomas Richter "EventName": "CPU_CYCLES", 6*7f76b311SThomas Richter "BriefDescription": "Cycle Count", 7*7f76b311SThomas Richter "PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state." 8*7f76b311SThomas Richter }, 9*7f76b311SThomas Richter { 10*7f76b311SThomas Richter "Unit": "CPU-M-CF", 11*7f76b311SThomas Richter "EventCode": "1", 12*7f76b311SThomas Richter "EventName": "INSTRUCTIONS", 13*7f76b311SThomas Richter "BriefDescription": "Instruction Count", 14*7f76b311SThomas Richter "PublicDescription": "This counter counts the total number of instructions executed by the CPU." 15*7f76b311SThomas Richter }, 16*7f76b311SThomas Richter { 17*7f76b311SThomas Richter "Unit": "CPU-M-CF", 18*7f76b311SThomas Richter "EventCode": "2", 19*7f76b311SThomas Richter "EventName": "L1I_DIR_WRITES", 20*7f76b311SThomas Richter "BriefDescription": "Level-1 I-Cache Directory Write Count", 21*7f76b311SThomas Richter "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes." 22*7f76b311SThomas Richter }, 23*7f76b311SThomas Richter { 24*7f76b311SThomas Richter "Unit": "CPU-M-CF", 25*7f76b311SThomas Richter "EventCode": "3", 26*7f76b311SThomas Richter "EventName": "L1I_PENALTY_CYCLES", 27*7f76b311SThomas Richter "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", 28*7f76b311SThomas Richter "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache." 29*7f76b311SThomas Richter }, 30*7f76b311SThomas Richter { 31*7f76b311SThomas Richter "Unit": "CPU-M-CF", 32*7f76b311SThomas Richter "EventCode": "4", 33*7f76b311SThomas Richter "EventName": "L1D_DIR_WRITES", 34*7f76b311SThomas Richter "BriefDescription": "Level-1 D-Cache Directory Write Count", 35*7f76b311SThomas Richter "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes." 36*7f76b311SThomas Richter }, 37*7f76b311SThomas Richter { 38*7f76b311SThomas Richter "Unit": "CPU-M-CF", 39*7f76b311SThomas Richter "EventCode": "5", 40*7f76b311SThomas Richter "EventName": "L1D_PENALTY_CYCLES", 41*7f76b311SThomas Richter "BriefDescription": "Level-1 D-Cache Penalty Cycle Count", 42*7f76b311SThomas Richter "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache." 43*7f76b311SThomas Richter }, 44*7f76b311SThomas Richter { 45*7f76b311SThomas Richter "Unit": "CPU-M-CF", 46*7f76b311SThomas Richter "EventCode": "32", 47*7f76b311SThomas Richter "EventName": "PROBLEM_STATE_CPU_CYCLES", 48*7f76b311SThomas Richter "BriefDescription": "Problem-State Cycle Count", 49*7f76b311SThomas Richter "PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state." 50*7f76b311SThomas Richter }, 51*7f76b311SThomas Richter { 52*7f76b311SThomas Richter "Unit": "CPU-M-CF", 53*7f76b311SThomas Richter "EventCode": "33", 54*7f76b311SThomas Richter "EventName": "PROBLEM_STATE_INSTRUCTIONS", 55*7f76b311SThomas Richter "BriefDescription": "Problem-State Instruction Count", 56*7f76b311SThomas Richter "PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state." 57*7f76b311SThomas Richter } 58*7f76b311SThomas Richter] 59