xref: /linux/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json (revision 0526b56cbc3c489642bd6a5fe4b718dea7ef0ee8) 
1[
2  {
3    "EventName": "ICACHE_RETIRED",
4    "EventCode": "0x0000102",
5    "BriefDescription": "Instruction cache miss"
6  },
7  {
8    "EventName": "DCACHE_MISS_MMIO_ACCESSES",
9    "EventCode": "0x0000202",
10    "BriefDescription": "Data cache miss or memory-mapped I/O access"
11  },
12  {
13    "EventName": "DCACHE_WRITEBACK",
14    "EventCode": "0x0000402",
15    "BriefDescription": "Data cache write-back"
16  },
17  {
18    "EventName": "INST_TLB_MISS",
19    "EventCode": "0x0000802",
20    "BriefDescription": "Instruction TLB miss"
21  },
22  {
23    "EventName": "DATA_TLB_MISS",
24    "EventCode": "0x0001002",
25    "BriefDescription": "Data TLB miss"
26  },
27  {
28    "EventName": "UTLB_MISS",
29    "EventCode": "0x0002002",
30    "BriefDescription": "UTLB miss"
31  }
32]