1[ 2 { 3 "MetricExpr": "PM_BR_MPRED_CMPL / PM_BR_PRED * 100", 4 "MetricGroup": "branch_prediction", 5 "MetricName": "br_misprediction_percent" 6 }, 7 { 8 "BriefDescription": "Count cache branch misprediction per instruction", 9 "MetricExpr": "PM_BR_MPRED_CCACHE / PM_RUN_INST_CMPL * 100", 10 "MetricGroup": "branch_prediction", 11 "MetricName": "ccache_mispredict_rate_percent" 12 }, 13 { 14 "BriefDescription": "Count cache branch misprediction", 15 "MetricExpr": "PM_BR_MPRED_CCACHE / PM_BR_PRED_CCACHE * 100", 16 "MetricGroup": "branch_prediction", 17 "MetricName": "ccache_misprediction_percent" 18 }, 19 { 20 "BriefDescription": "Link stack branch misprediction", 21 "MetricExpr": "PM_BR_MPRED_LSTACK / PM_RUN_INST_CMPL * 100", 22 "MetricGroup": "branch_prediction", 23 "MetricName": "lstack_mispredict_rate_percent" 24 }, 25 { 26 "BriefDescription": "Link stack branch misprediction", 27 "MetricExpr": "PM_BR_MPRED_LSTACK/ PM_BR_PRED_LSTACK * 100", 28 "MetricGroup": "branch_prediction", 29 "MetricName": "lstack_misprediction_percent" 30 }, 31 { 32 "BriefDescription": "% Branches Taken", 33 "MetricExpr": "PM_BR_TAKEN_CMPL * 100 / PM_BRU_FIN", 34 "MetricGroup": "branch_prediction", 35 "MetricName": "taken_branches_percent" 36 }, 37 { 38 "BriefDescription": "Completion stall due to a Branch Unit", 39 "MetricExpr": "PM_CMPLU_STALL_BRU/PM_RUN_INST_CMPL", 40 "MetricGroup": "cpi_breakdown", 41 "MetricName": "bru_stall_cpi" 42 }, 43 { 44 "BriefDescription": "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish", 45 "MetricExpr": "PM_CMPLU_STALL_CRYPTO/PM_RUN_INST_CMPL", 46 "MetricGroup": "cpi_breakdown", 47 "MetricName": "crypto_stall_cpi" 48 }, 49 { 50 "BriefDescription": "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest", 51 "MetricExpr": "PM_CMPLU_STALL_DCACHE_MISS/PM_RUN_INST_CMPL", 52 "MetricGroup": "cpi_breakdown", 53 "MetricName": "dcache_miss_stall_cpi" 54 }, 55 { 56 "BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued to the Decimal Floating Point execution pipe and waiting to finish.", 57 "MetricExpr": "PM_CMPLU_STALL_DFLONG/PM_RUN_INST_CMPL", 58 "MetricGroup": "cpi_breakdown", 59 "MetricName": "dflong_stall_cpi" 60 }, 61 { 62 "BriefDescription": "Stalls due to short latency decimal floating ops.", 63 "MetricExpr": "dfu_stall_cpi - dflong_stall_cpi", 64 "MetricGroup": "cpi_breakdown", 65 "MetricName": "dfu_other_stall_cpi" 66 }, 67 { 68 "BriefDescription": "Finish stall because the NTF instruction was issued to the Decimal Floating Point execution pipe and waiting to finish.", 69 "MetricExpr": "PM_CMPLU_STALL_DFU/PM_RUN_INST_CMPL", 70 "MetricGroup": "cpi_breakdown", 71 "MetricName": "dfu_stall_cpi" 72 }, 73 { 74 "BriefDescription": "Completion stall by Dcache miss which resolved off node memory/cache", 75 "MetricExpr": "dmiss_non_local_stall_cpi - dmiss_remote_stall_cpi", 76 "MetricGroup": "cpi_breakdown", 77 "MetricName": "dmiss_distant_stall_cpi" 78 }, 79 { 80 "BriefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)", 81 "MetricExpr": "PM_CMPLU_STALL_DMISS_L21_L31/PM_RUN_INST_CMPL", 82 "MetricGroup": "cpi_breakdown", 83 "MetricName": "dmiss_l21_l31_stall_cpi" 84 }, 85 { 86 "BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict", 87 "MetricExpr": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT/PM_RUN_INST_CMPL", 88 "MetricGroup": "cpi_breakdown", 89 "MetricName": "dmiss_l2l3_conflict_stall_cpi" 90 }, 91 { 92 "BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 without conflict", 93 "MetricExpr": "dmiss_l2l3_stall_cpi - dmiss_l2l3_conflict_stall_cpi", 94 "MetricGroup": "cpi_breakdown", 95 "MetricName": "dmiss_l2l3_noconflict_stall_cpi" 96 }, 97 { 98 "BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3", 99 "MetricExpr": "PM_CMPLU_STALL_DMISS_L2L3/PM_RUN_INST_CMPL", 100 "MetricGroup": "cpi_breakdown", 101 "MetricName": "dmiss_l2l3_stall_cpi" 102 }, 103 { 104 "BriefDescription": "Completion stall due to cache miss resolving missed the L3", 105 "MetricExpr": "PM_CMPLU_STALL_DMISS_L3MISS/PM_RUN_INST_CMPL", 106 "MetricGroup": "cpi_breakdown", 107 "MetricName": "dmiss_l3miss_stall_cpi" 108 }, 109 { 110 "BriefDescription": "Completion stall due to cache miss that resolves in local memory", 111 "MetricExpr": "PM_CMPLU_STALL_DMISS_LMEM/PM_RUN_INST_CMPL", 112 "MetricGroup": "cpi_breakdown", 113 "MetricName": "dmiss_lmem_stall_cpi" 114 }, 115 { 116 "BriefDescription": "Completion stall by Dcache miss which resolved outside of local memory", 117 "MetricExpr": "dmiss_l3miss_stall_cpi - dmiss_l21_l31_stall_cpi - dmiss_lmem_stall_cpi", 118 "MetricGroup": "cpi_breakdown", 119 "MetricName": "dmiss_non_local_stall_cpi" 120 }, 121 { 122 "BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or memory)", 123 "MetricExpr": "PM_CMPLU_STALL_DMISS_REMOTE/PM_RUN_INST_CMPL", 124 "MetricGroup": "cpi_breakdown", 125 "MetricName": "dmiss_remote_stall_cpi" 126 }, 127 { 128 "BriefDescription": "Stalls due to short latency double precision ops.", 129 "MetricExpr": "dp_stall_cpi - dplong_stall_cpi", 130 "MetricGroup": "cpi_breakdown", 131 "MetricName": "dp_other_stall_cpi" 132 }, 133 { 134 "BriefDescription": "Finish stall because the NTF instruction was a scalar instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format.", 135 "MetricExpr": "PM_CMPLU_STALL_DP/PM_RUN_INST_CMPL", 136 "MetricGroup": "cpi_breakdown", 137 "MetricName": "dp_stall_cpi" 138 }, 139 { 140 "BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format.", 141 "MetricExpr": "PM_CMPLU_STALL_DPLONG/PM_RUN_INST_CMPL", 142 "MetricGroup": "cpi_breakdown", 143 "MetricName": "dplong_stall_cpi" 144 }, 145 { 146 "BriefDescription": "Finish stall because the NTF instruction is an EIEIO waiting for response from L2", 147 "MetricExpr": "PM_CMPLU_STALL_EIEIO/PM_RUN_INST_CMPL", 148 "MetricGroup": "cpi_breakdown", 149 "MetricName": "eieio_stall_cpi" 150 }, 151 { 152 "BriefDescription": "Finish stall because the next to finish instruction suffered an ERAT miss and the EMQ was full", 153 "MetricExpr": "PM_CMPLU_STALL_EMQ_FULL/PM_RUN_INST_CMPL", 154 "MetricGroup": "cpi_breakdown", 155 "MetricName": "emq_full_stall_cpi" 156 }, 157 { 158 "MetricExpr": "erat_miss_stall_cpi + emq_full_stall_cpi", 159 "MetricGroup": "cpi_breakdown", 160 "MetricName": "emq_stall_cpi" 161 }, 162 { 163 "BriefDescription": "Finish stall because the NTF instruction was a load or store that suffered a translation miss", 164 "MetricExpr": "PM_CMPLU_STALL_ERAT_MISS/PM_RUN_INST_CMPL", 165 "MetricGroup": "cpi_breakdown", 166 "MetricName": "erat_miss_stall_cpi" 167 }, 168 { 169 "BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete", 170 "MetricExpr": "PM_CMPLU_STALL_EXCEPTION/PM_RUN_INST_CMPL", 171 "MetricGroup": "cpi_breakdown", 172 "MetricName": "exception_stall_cpi" 173 }, 174 { 175 "BriefDescription": "Completion stall due to execution units for other reasons.", 176 "MetricExpr": "exec_unit_stall_cpi - scalar_stall_cpi - vector_stall_cpi", 177 "MetricGroup": "cpi_breakdown", 178 "MetricName": "exec_unit_other_stall_cpi" 179 }, 180 { 181 "BriefDescription": "Completion stall due to execution units (FXU/VSU/CRU)", 182 "MetricExpr": "PM_CMPLU_STALL_EXEC_UNIT/PM_RUN_INST_CMPL", 183 "MetricGroup": "cpi_breakdown", 184 "MetricName": "exec_unit_stall_cpi" 185 }, 186 { 187 "BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion", 188 "MetricExpr": "PM_CMPLU_STALL_FLUSH_ANY_THREAD/PM_RUN_INST_CMPL", 189 "MetricGroup": "cpi_breakdown", 190 "MetricName": "flush_any_thread_stall_cpi" 191 }, 192 { 193 "BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (division, square root)", 194 "MetricExpr": "PM_CMPLU_STALL_FXLONG/PM_RUN_INST_CMPL", 195 "MetricGroup": "cpi_breakdown", 196 "MetricName": "fxlong_stall_cpi" 197 }, 198 { 199 "BriefDescription": "Stalls due to short latency integer ops", 200 "MetricExpr": "fxu_stall_cpi - fxlong_stall_cpi", 201 "MetricGroup": "cpi_breakdown", 202 "MetricName": "fxu_other_stall_cpi" 203 }, 204 { 205 "BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes", 206 "MetricExpr": "PM_CMPLU_STALL_FXU/PM_RUN_INST_CMPL", 207 "MetricGroup": "cpi_breakdown", 208 "MetricName": "fxu_stall_cpi" 209 }, 210 { 211 "BriefDescription": "Instruction Completion Table empty for this thread due to branch mispred", 212 "MetricExpr": "PM_ICT_NOSLOT_BR_MPRED/PM_RUN_INST_CMPL", 213 "MetricGroup": "cpi_breakdown", 214 "MetricName": "ict_noslot_br_mpred_cpi" 215 }, 216 { 217 "BriefDescription": "Instruction Completion Table empty for this thread due to Icache Miss and branch mispred", 218 "MetricExpr": "PM_ICT_NOSLOT_BR_MPRED_ICMISS/PM_RUN_INST_CMPL", 219 "MetricGroup": "cpi_breakdown", 220 "MetricName": "ict_noslot_br_mpred_icmiss_cpi" 221 }, 222 { 223 "BriefDescription": "Instruction Completion Table other stalls", 224 "MetricExpr": "nothing_dispatched_cpi - ict_noslot_ic_miss_cpi - ict_noslot_br_mpred_icmiss_cpi - ict_noslot_br_mpred_cpi - ict_noslot_disp_held_cpi", 225 "MetricGroup": "cpi_breakdown", 226 "MetricName": "ict_noslot_cyc_other_cpi" 227 }, 228 { 229 "BriefDescription": "Cycles in which the NTC instruciton is held at dispatch for any reason", 230 "MetricExpr": "PM_ICT_NOSLOT_DISP_HELD/PM_RUN_INST_CMPL", 231 "MetricGroup": "cpi_breakdown", 232 "MetricName": "ict_noslot_disp_held_cpi" 233 }, 234 { 235 "BriefDescription": "Instruction Completion Table empty for this thread due to dispatch holds because the History Buffer was full. Could be GPR/VSR/VMR/FPR/CR/XVF", 236 "MetricExpr": "PM_ICT_NOSLOT_DISP_HELD_HB_FULL/PM_RUN_INST_CMPL", 237 "MetricGroup": "cpi_breakdown", 238 "MetricName": "ict_noslot_disp_held_hb_full_cpi" 239 }, 240 { 241 "BriefDescription": "Instruction Completion Table empty for this thread due to dispatch hold on this thread due to Issue q full, BRQ full, XVCF Full, Count cache, Link, Tar full", 242 "MetricExpr": "PM_ICT_NOSLOT_DISP_HELD_ISSQ/PM_RUN_INST_CMPL", 243 "MetricGroup": "cpi_breakdown", 244 "MetricName": "ict_noslot_disp_held_issq_cpi" 245 }, 246 { 247 "BriefDescription": "ICT_NOSLOT_DISP_HELD_OTHER_CPI", 248 "MetricExpr": "ict_noslot_disp_held_cpi - ict_noslot_disp_held_hb_full_cpi - ict_noslot_disp_held_sync_cpi - ict_noslot_disp_held_tbegin_cpi - ict_noslot_disp_held_issq_cpi", 249 "MetricGroup": "cpi_breakdown", 250 "MetricName": "ict_noslot_disp_held_other_cpi" 251 }, 252 { 253 "BriefDescription": "Dispatch held due to a synchronizing instruction at dispatch", 254 "MetricExpr": "PM_ICT_NOSLOT_DISP_HELD_SYNC/PM_RUN_INST_CMPL", 255 "MetricGroup": "cpi_breakdown", 256 "MetricName": "ict_noslot_disp_held_sync_cpi" 257 }, 258 { 259 "BriefDescription": "the NTC instruction is being held at dispatch because it is a tbegin instruction and there is an older tbegin in the pipeline that must complete before the younger tbegin can dispatch", 260 "MetricExpr": "PM_ICT_NOSLOT_DISP_HELD_TBEGIN/PM_RUN_INST_CMPL", 261 "MetricGroup": "cpi_breakdown", 262 "MetricName": "ict_noslot_disp_held_tbegin_cpi" 263 }, 264 { 265 "BriefDescription": "ICT_NOSLOT_IC_L2_CPI", 266 "MetricExpr": "ict_noslot_ic_miss_cpi - ict_noslot_ic_l3_cpi - ict_noslot_ic_l3miss_cpi", 267 "MetricGroup": "cpi_breakdown", 268 "MetricName": "ict_noslot_ic_l2_cpi" 269 }, 270 { 271 "BriefDescription": "Instruction Completion Table empty for this thread due to icache misses that were sourced from the local L3", 272 "MetricExpr": "PM_ICT_NOSLOT_IC_L3/PM_RUN_INST_CMPL", 273 "MetricGroup": "cpi_breakdown", 274 "MetricName": "ict_noslot_ic_l3_cpi" 275 }, 276 { 277 "BriefDescription": "Instruction Completion Table empty for this thread due to icache misses that were sourced from beyond the local L3. The source could be local/remote/distant memory or another core's cache", 278 "MetricExpr": "PM_ICT_NOSLOT_IC_L3MISS/PM_RUN_INST_CMPL", 279 "MetricGroup": "cpi_breakdown", 280 "MetricName": "ict_noslot_ic_l3miss_cpi" 281 }, 282 { 283 "BriefDescription": "Instruction Completion Table empty for this thread due to Icache Miss", 284 "MetricExpr": "PM_ICT_NOSLOT_IC_MISS/PM_RUN_INST_CMPL", 285 "MetricGroup": "cpi_breakdown", 286 "MetricName": "ict_noslot_ic_miss_cpi" 287 }, 288 { 289 "MetricExpr": "ntc_issue_held_darq_full_cpi + ntc_issue_held_arb_cpi + ntc_issue_held_other_cpi", 290 "MetricGroup": "cpi_breakdown", 291 "MetricName": "issue_hold_cpi" 292 }, 293 { 294 "BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied", 295 "MetricExpr": "PM_CMPLU_STALL_LARX/PM_RUN_INST_CMPL", 296 "MetricGroup": "cpi_breakdown", 297 "MetricName": "larx_stall_cpi" 298 }, 299 { 300 "BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data", 301 "MetricExpr": "PM_CMPLU_STALL_LHS/PM_RUN_INST_CMPL", 302 "MetricGroup": "cpi_breakdown", 303 "MetricName": "lhs_stall_cpi" 304 }, 305 { 306 "BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full", 307 "MetricExpr": "PM_CMPLU_STALL_LMQ_FULL/PM_RUN_INST_CMPL", 308 "MetricGroup": "cpi_breakdown", 309 "MetricName": "lmq_full_stall_cpi" 310 }, 311 { 312 "BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish", 313 "MetricExpr": "PM_CMPLU_STALL_LOAD_FINISH/PM_RUN_INST_CMPL", 314 "MetricGroup": "cpi_breakdown", 315 "MetricName": "load_finish_stall_cpi" 316 }, 317 { 318 "BriefDescription": "Finish stall because the NTF instruction was a load that was held in LSAQ because the LRQ was full", 319 "MetricExpr": "PM_CMPLU_STALL_LRQ_FULL/PM_RUN_INST_CMPL", 320 "MetricGroup": "cpi_breakdown", 321 "MetricName": "lrq_full_stall_cpi" 322 }, 323 { 324 "BriefDescription": "Finish stall due to LRQ miscellaneous reasons, lost arbitration to LMQ slot, bank collisions, set prediction cleanup, set prediction multihit and others", 325 "MetricExpr": "PM_CMPLU_STALL_LRQ_OTHER/PM_RUN_INST_CMPL", 326 "MetricGroup": "cpi_breakdown", 327 "MetricName": "lrq_other_stall_cpi" 328 }, 329 { 330 "MetricExpr": "lmq_full_stall_cpi + st_fwd_stall_cpi + lhs_stall_cpi + lsu_mfspr_stall_cpi + larx_stall_cpi + lrq_other_stall_cpi", 331 "MetricGroup": "cpi_breakdown", 332 "MetricName": "lrq_stall_cpi" 333 }, 334 { 335 "BriefDescription": "Finish stall because the NTF instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ won arbitration to the LSU pipe when this instruction tried to launch", 336 "MetricExpr": "PM_CMPLU_STALL_LSAQ_ARB/PM_RUN_INST_CMPL", 337 "MetricGroup": "cpi_breakdown", 338 "MetricName": "lsaq_arb_stall_cpi" 339 }, 340 { 341 "MetricExpr": "lrq_full_stall_cpi + srq_full_stall_cpi + lsaq_arb_stall_cpi", 342 "MetricGroup": "cpi_breakdown", 343 "MetricName": "lsaq_stall_cpi" 344 }, 345 { 346 "BriefDescription": "Finish stall because the NTF instruction was an LSU op (other than a load or a store) with all its dependencies met and just going through the LSU pipe to finish", 347 "MetricExpr": "PM_CMPLU_STALL_LSU_FIN/PM_RUN_INST_CMPL", 348 "MetricGroup": "cpi_breakdown", 349 "MetricName": "lsu_fin_stall_cpi" 350 }, 351 { 352 "BriefDescription": "Completion stall of one cycle because the LSU requested to flush the next iop in the sequence. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to complete", 353 "MetricExpr": "PM_CMPLU_STALL_LSU_FLUSH_NEXT/PM_RUN_INST_CMPL", 354 "MetricGroup": "cpi_breakdown", 355 "MetricName": "lsu_flush_next_stall_cpi" 356 }, 357 { 358 "BriefDescription": "Finish stall because the NTF instruction was a mfspr instruction targeting an LSU SPR and it was waiting for the register data to be returned", 359 "MetricExpr": "PM_CMPLU_STALL_LSU_MFSPR/PM_RUN_INST_CMPL", 360 "MetricGroup": "cpi_breakdown", 361 "MetricName": "lsu_mfspr_stall_cpi" 362 }, 363 { 364 "BriefDescription": "Completion LSU stall for other reasons", 365 "MetricExpr": "lsu_stall_cpi - lsu_fin_stall_cpi - store_finish_stall_cpi - srq_stall_cpi - load_finish_stall_cpi + lsu_stall_dcache_miss_cpi - lrq_stall_cpi + emq_stall_cpi - lsaq_stall_cpi", 366 "MetricGroup": "cpi_breakdown", 367 "MetricName": "lsu_other_stall_cpi" 368 }, 369 { 370 "BriefDescription": "Completion stall by LSU instruction", 371 "MetricExpr": "PM_CMPLU_STALL_LSU/PM_RUN_INST_CMPL", 372 "MetricGroup": "cpi_breakdown", 373 "MetricName": "lsu_stall_cpi" 374 }, 375 { 376 "BriefDescription": "Completion stall because the ISU is updating the register and notifying the Effective Address Table (EAT)", 377 "MetricExpr": "PM_CMPLU_STALL_MTFPSCR/PM_RUN_INST_CMPL", 378 "MetricGroup": "cpi_breakdown", 379 "MetricName": "mtfpscr_stall_cpi" 380 }, 381 { 382 "BriefDescription": "Completion stall because the ISU is updating the TEXASR to keep track of the nested tbegin. This is a short delay, and it includes ROT", 383 "MetricExpr": "PM_CMPLU_STALL_NESTED_TBEGIN/PM_RUN_INST_CMPL", 384 "MetricGroup": "cpi_breakdown", 385 "MetricName": "nested_tbegin_stall_cpi" 386 }, 387 { 388 "BriefDescription": "Completion stall because the ISU is updating the TEXASR to keep track of the nested tend and decrement the TEXASR nested level. This is a short delay", 389 "MetricExpr": "PM_CMPLU_STALL_NESTED_TEND/PM_RUN_INST_CMPL", 390 "MetricGroup": "cpi_breakdown", 391 "MetricName": "nested_tend_stall_cpi" 392 }, 393 { 394 "BriefDescription": "Number of cycles the Instruction Completion Table has no itags assigned to this thread", 395 "MetricExpr": "PM_ICT_NOSLOT_CYC/PM_RUN_INST_CMPL", 396 "MetricGroup": "cpi_breakdown", 397 "MetricName": "nothing_dispatched_cpi" 398 }, 399 { 400 "BriefDescription": "Finish stall because the NTF instruction was one that must finish at dispatch.", 401 "MetricExpr": "PM_CMPLU_STALL_NTC_DISP_FIN/PM_RUN_INST_CMPL", 402 "MetricGroup": "cpi_breakdown", 403 "MetricName": "ntc_disp_fin_stall_cpi" 404 }, 405 { 406 "BriefDescription": "Cycles in which the oldest instruction in the pipeline (NTC) finishes. This event is used to account for cycles in which work is being completed in the CPI stack", 407 "MetricExpr": "PM_NTC_FIN/PM_RUN_INST_CMPL", 408 "MetricGroup": "cpi_breakdown", 409 "MetricName": "ntc_fin_cpi" 410 }, 411 { 412 "BriefDescription": "Completion stall due to ntc flush", 413 "MetricExpr": "PM_CMPLU_STALL_NTC_FLUSH/PM_RUN_INST_CMPL", 414 "MetricGroup": "cpi_breakdown", 415 "MetricName": "ntc_flush_stall_cpi" 416 }, 417 { 418 "BriefDescription": "The NTC instruction is being held at dispatch because it lost arbitration onto the issue pipe to another instruction (from the same thread or a different thread)", 419 "MetricExpr": "PM_NTC_ISSUE_HELD_ARB/PM_RUN_INST_CMPL", 420 "MetricGroup": "cpi_breakdown", 421 "MetricName": "ntc_issue_held_arb_cpi" 422 }, 423 { 424 "BriefDescription": "The NTC instruction is being held at dispatch because there are no slots in the DARQ for it", 425 "MetricExpr": "PM_NTC_ISSUE_HELD_DARQ_FULL/PM_RUN_INST_CMPL", 426 "MetricGroup": "cpi_breakdown", 427 "MetricName": "ntc_issue_held_darq_full_cpi" 428 }, 429 { 430 "BriefDescription": "The NTC instruction is being held at dispatch during regular pipeline cycles, or because the VSU is busy with multi-cycle instructions, or because of a write-back collision with VSU", 431 "MetricExpr": "PM_NTC_ISSUE_HELD_OTHER/PM_RUN_INST_CMPL", 432 "MetricGroup": "cpi_breakdown", 433 "MetricName": "ntc_issue_held_other_cpi" 434 }, 435 { 436 "BriefDescription": "Cycles unaccounted for.", 437 "MetricExpr": "run_cpi - completion_cpi - thread_block_stall_cpi - stall_cpi - nothing_dispatched_cpi", 438 "MetricGroup": "cpi_breakdown", 439 "MetricName": "other_cpi" 440 }, 441 { 442 "BriefDescription": "Completion stall for other reasons", 443 "MetricExpr": "stall_cpi - ntc_disp_fin_stall_cpi - ntc_flush_stall_cpi - lsu_stall_cpi - exec_unit_stall_cpi - bru_stall_cpi", 444 "MetricGroup": "cpi_breakdown", 445 "MetricName": "other_stall_cpi" 446 }, 447 { 448 "BriefDescription": "Finish stall because the NTF instruction was a paste waiting for response from L2", 449 "MetricExpr": "PM_CMPLU_STALL_PASTE/PM_RUN_INST_CMPL", 450 "MetricGroup": "cpi_breakdown", 451 "MetricName": "paste_stall_cpi" 452 }, 453 { 454 "BriefDescription": "Finish stall because the NTF instruction was issued to the Permute execution pipe and waiting to finish.", 455 "MetricExpr": "PM_CMPLU_STALL_PM/PM_RUN_INST_CMPL", 456 "MetricGroup": "cpi_breakdown", 457 "MetricName": "pm_stall_cpi" 458 }, 459 { 460 "BriefDescription": "Run cycles per run instruction", 461 "MetricExpr": "PM_RUN_CYC / PM_RUN_INST_CMPL", 462 "MetricGroup": "cpi_breakdown", 463 "MetricName": "run_cpi" 464 }, 465 { 466 "BriefDescription": "Run_cycles", 467 "MetricExpr": "PM_RUN_CYC/PM_RUN_INST_CMPL", 468 "MetricGroup": "cpi_breakdown", 469 "MetricName": "run_cyc_cpi" 470 }, 471 { 472 "MetricExpr": "fxu_stall_cpi + dp_stall_cpi + dfu_stall_cpi + pm_stall_cpi + crypto_stall_cpi", 473 "MetricGroup": "cpi_breakdown", 474 "MetricName": "scalar_stall_cpi" 475 }, 476 { 477 "BriefDescription": "Finish stall because the NTF instruction was awaiting L2 response for an SLB", 478 "MetricExpr": "PM_CMPLU_STALL_SLB/PM_RUN_INST_CMPL", 479 "MetricGroup": "cpi_breakdown", 480 "MetricName": "slb_stall_cpi" 481 }, 482 { 483 "BriefDescription": "Finish stall while waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECC", 484 "MetricExpr": "PM_CMPLU_STALL_SPEC_FINISH/PM_RUN_INST_CMPL", 485 "MetricGroup": "cpi_breakdown", 486 "MetricName": "spec_finish_stall_cpi" 487 }, 488 { 489 "BriefDescription": "Finish stall because the NTF instruction was a store that was held in LSAQ because the SRQ was full", 490 "MetricExpr": "PM_CMPLU_STALL_SRQ_FULL/PM_RUN_INST_CMPL", 491 "MetricGroup": "cpi_breakdown", 492 "MetricName": "srq_full_stall_cpi" 493 }, 494 { 495 "MetricExpr": "store_data_stall_cpi + eieio_stall_cpi + stcx_stall_cpi + slb_stall_cpi + tend_stall_cpi + paste_stall_cpi + tlbie_stall_cpi + store_pipe_arb_stall_cpi + store_fin_arb_stall_cpi", 496 "MetricGroup": "cpi_breakdown", 497 "MetricName": "srq_stall_cpi" 498 }, 499 { 500 "BriefDescription": "Completion stall due to store forward", 501 "MetricExpr": "PM_CMPLU_STALL_ST_FWD/PM_RUN_INST_CMPL", 502 "MetricGroup": "cpi_breakdown", 503 "MetricName": "st_fwd_stall_cpi" 504 }, 505 { 506 "BriefDescription": "Nothing completed and Instruction Completion Table not empty", 507 "MetricExpr": "PM_CMPLU_STALL/PM_RUN_INST_CMPL", 508 "MetricGroup": "cpi_breakdown", 509 "MetricName": "stall_cpi" 510 }, 511 { 512 "BriefDescription": "Finish stall because the NTF instruction was a stcx waiting for response from L2", 513 "MetricExpr": "PM_CMPLU_STALL_STCX/PM_RUN_INST_CMPL", 514 "MetricGroup": "cpi_breakdown", 515 "MetricName": "stcx_stall_cpi" 516 }, 517 { 518 "BriefDescription": "Finish stall because the next to finish instruction was a store waiting on data", 519 "MetricExpr": "PM_CMPLU_STALL_STORE_DATA/PM_RUN_INST_CMPL", 520 "MetricGroup": "cpi_breakdown", 521 "MetricName": "store_data_stall_cpi" 522 }, 523 { 524 "BriefDescription": "Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. This means the instruction is ready to finish but there are instructions ahead of it, using the finish pipe", 525 "MetricExpr": "PM_CMPLU_STALL_STORE_FIN_ARB/PM_RUN_INST_CMPL", 526 "MetricGroup": "cpi_breakdown", 527 "MetricName": "store_fin_arb_stall_cpi" 528 }, 529 { 530 "BriefDescription": "Finish stall because the NTF instruction was a store with all its dependencies met, just waiting to go through the LSU pipe to finish", 531 "MetricExpr": "PM_CMPLU_STALL_STORE_FINISH/PM_RUN_INST_CMPL", 532 "MetricGroup": "cpi_breakdown", 533 "MetricName": "store_finish_stall_cpi" 534 }, 535 { 536 "BriefDescription": "Finish stall because the NTF instruction was a store waiting for the next relaunch opportunity after an internal reject. This means the instruction is ready to relaunch and tried once but lost arbitration", 537 "MetricExpr": "PM_CMPLU_STALL_STORE_PIPE_ARB/PM_RUN_INST_CMPL", 538 "MetricGroup": "cpi_breakdown", 539 "MetricName": "store_pipe_arb_stall_cpi" 540 }, 541 { 542 "BriefDescription": "Finish stall because the NTF instruction was a tend instruction awaiting response from L2", 543 "MetricExpr": "PM_CMPLU_STALL_TEND/PM_RUN_INST_CMPL", 544 "MetricGroup": "cpi_breakdown", 545 "MetricName": "tend_stall_cpi" 546 }, 547 { 548 "BriefDescription": "Completion Stalled because the thread was blocked", 549 "MetricExpr": "PM_CMPLU_STALL_THRD/PM_RUN_INST_CMPL", 550 "MetricGroup": "cpi_breakdown", 551 "MetricName": "thread_block_stall_cpi" 552 }, 553 { 554 "BriefDescription": "Finish stall because the NTF instruction was a tlbie waiting for response from L2", 555 "MetricExpr": "PM_CMPLU_STALL_TLBIE/PM_RUN_INST_CMPL", 556 "MetricGroup": "cpi_breakdown", 557 "MetricName": "tlbie_stall_cpi" 558 }, 559 { 560 "BriefDescription": "Vector stalls due to small latency double precision ops", 561 "MetricExpr": "vdp_stall_cpi - vdplong_stall_cpi", 562 "MetricGroup": "cpi_breakdown", 563 "MetricName": "vdp_other_stall_cpi" 564 }, 565 { 566 "BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to the Double Precision execution pipe and waiting to finish.", 567 "MetricExpr": "PM_CMPLU_STALL_VDP/PM_RUN_INST_CMPL", 568 "MetricGroup": "cpi_breakdown", 569 "MetricName": "vdp_stall_cpi" 570 }, 571 { 572 "BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format.", 573 "MetricExpr": "PM_CMPLU_STALL_VDPLONG/PM_RUN_INST_CMPL", 574 "MetricGroup": "cpi_breakdown", 575 "MetricName": "vdplong_stall_cpi" 576 }, 577 { 578 "MetricExpr": "vfxu_stall_cpi + vdp_stall_cpi", 579 "MetricGroup": "cpi_breakdown", 580 "MetricName": "vector_stall_cpi" 581 }, 582 { 583 "BriefDescription": "Completion stall due to a long latency vector fixed point instruction (division, square root)", 584 "MetricExpr": "PM_CMPLU_STALL_VFXLONG/PM_RUN_INST_CMPL", 585 "MetricGroup": "cpi_breakdown", 586 "MetricName": "vfxlong_stall_cpi" 587 }, 588 { 589 "BriefDescription": "Vector stalls due to small latency integer ops", 590 "MetricExpr": "vfxu_stall_cpi - vfxlong_stall_cpi", 591 "MetricGroup": "cpi_breakdown", 592 "MetricName": "vfxu_other_stall_cpi" 593 }, 594 { 595 "BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes", 596 "MetricExpr": "PM_CMPLU_STALL_VFXU/PM_RUN_INST_CMPL", 597 "MetricGroup": "cpi_breakdown", 598 "MetricName": "vfxu_stall_cpi" 599 }, 600 { 601 "BriefDescription": "% of DL1 Reloads from Distant L2 or L3 (Modified) per Inst", 602 "MetricExpr": "PM_DATA_FROM_DL2L3_MOD * 100 / PM_RUN_INST_CMPL", 603 "MetricGroup": "dl1_reloads_percent_per_inst", 604 "MetricName": "dl1_reload_from_dl2l3_mod_rate_percent" 605 }, 606 { 607 "BriefDescription": "% of DL1 Reloads from Distant L2 or L3 (Shared) per Inst", 608 "MetricExpr": "PM_DATA_FROM_DL2L3_SHR * 100 / PM_RUN_INST_CMPL", 609 "MetricGroup": "dl1_reloads_percent_per_inst", 610 "MetricName": "dl1_reload_from_dl2l3_shr_rate_percent" 611 }, 612 { 613 "BriefDescription": "% of DL1 Reloads from Distant Memory per Inst", 614 "MetricExpr": "PM_DATA_FROM_DMEM * 100 / PM_RUN_INST_CMPL", 615 "MetricGroup": "dl1_reloads_percent_per_inst", 616 "MetricName": "dl1_reload_from_dmem_rate_percent" 617 }, 618 { 619 "BriefDescription": "% of DL1 reloads from Private L2, other core per Inst", 620 "MetricExpr": "PM_DATA_FROM_L21_MOD * 100 / PM_RUN_INST_CMPL", 621 "MetricGroup": "dl1_reloads_percent_per_inst", 622 "MetricName": "dl1_reload_from_l21_mod_rate_percent" 623 }, 624 { 625 "BriefDescription": "% of DL1 reloads from Private L2, other core per Inst", 626 "MetricExpr": "PM_DATA_FROM_L21_SHR * 100 / PM_RUN_INST_CMPL", 627 "MetricGroup": "dl1_reloads_percent_per_inst", 628 "MetricName": "dl1_reload_from_l21_shr_rate_percent" 629 }, 630 { 631 "BriefDescription": "% of DL1 reloads from L2 per Inst", 632 "MetricExpr": "PM_DATA_FROM_L2MISS * 100 / PM_RUN_INST_CMPL", 633 "MetricGroup": "dl1_reloads_percent_per_inst", 634 "MetricName": "dl1_reload_from_l2_miss_rate_percent" 635 }, 636 { 637 "BriefDescription": "% of DL1 reloads from L2 per Inst", 638 "MetricExpr": "PM_DATA_FROM_L2 * 100 / PM_RUN_INST_CMPL", 639 "MetricGroup": "dl1_reloads_percent_per_inst", 640 "MetricName": "dl1_reload_from_l2_rate_percent" 641 }, 642 { 643 "BriefDescription": "% of DL1 reloads from Private L3 M state, other core per Inst", 644 "MetricExpr": "PM_DATA_FROM_L31_MOD * 100 / PM_RUN_INST_CMPL", 645 "MetricGroup": "dl1_reloads_percent_per_inst", 646 "MetricName": "dl1_reload_from_l31_mod_rate_percent" 647 }, 648 { 649 "BriefDescription": "% of DL1 reloads from Private L3 S tate, other core per Inst", 650 "MetricExpr": "PM_DATA_FROM_L31_SHR * 100 / PM_RUN_INST_CMPL", 651 "MetricGroup": "dl1_reloads_percent_per_inst", 652 "MetricName": "dl1_reload_from_l31_shr_rate_percent" 653 }, 654 { 655 "BriefDescription": "% of DL1 Reloads that came from the L3 and were brought into the L3 by a prefetch, per instruction completed", 656 "MetricExpr": "PM_DATA_FROM_L3_MEPF * 100 / PM_RUN_INST_CMPL", 657 "MetricGroup": "dl1_reloads_percent_per_inst", 658 "MetricName": "dl1_reload_from_l3_mepf_rate_percent" 659 }, 660 { 661 "BriefDescription": "% of DL1 reloads from L3 per Inst", 662 "MetricExpr": "PM_DATA_FROM_L3MISS * 100 / PM_RUN_INST_CMPL", 663 "MetricGroup": "dl1_reloads_percent_per_inst", 664 "MetricName": "dl1_reload_from_l3_miss_rate_percent" 665 }, 666 { 667 "BriefDescription": "% of DL1 Reloads from L3 per Inst", 668 "MetricExpr": "PM_DATA_FROM_L3 * 100 / PM_RUN_INST_CMPL", 669 "MetricGroup": "dl1_reloads_percent_per_inst", 670 "MetricName": "dl1_reload_from_l3_rate_percent" 671 }, 672 { 673 "BriefDescription": "% of DL1 Reloads from Local Memory per Inst", 674 "MetricExpr": "PM_DATA_FROM_LMEM * 100 / PM_RUN_INST_CMPL", 675 "MetricGroup": "dl1_reloads_percent_per_inst", 676 "MetricName": "dl1_reload_from_lmem_rate_percent" 677 }, 678 { 679 "BriefDescription": "% of DL1 reloads from Private L3, other core per Inst", 680 "MetricExpr": "PM_DATA_FROM_RL2L3_MOD * 100 / PM_RUN_INST_CMPL", 681 "MetricGroup": "dl1_reloads_percent_per_inst", 682 "MetricName": "dl1_reload_from_rl2l3_mod_rate_percent" 683 }, 684 { 685 "BriefDescription": "% of DL1 reloads from Private L3, other core per Inst", 686 "MetricExpr": "PM_DATA_FROM_RL2L3_SHR * 100 / PM_RUN_INST_CMPL", 687 "MetricGroup": "dl1_reloads_percent_per_inst", 688 "MetricName": "dl1_reload_from_rl2l3_shr_rate_percent" 689 }, 690 { 691 "BriefDescription": "% of DL1 Reloads from Remote Memory per Inst", 692 "MetricExpr": "PM_DATA_FROM_RMEM * 100 / PM_RUN_INST_CMPL", 693 "MetricGroup": "dl1_reloads_percent_per_inst", 694 "MetricName": "dl1_reload_from_rmem_rate_percent" 695 }, 696 { 697 "BriefDescription": "Percentage of L1 demand load misses per run instruction", 698 "MetricExpr": "PM_LD_MISS_L1 * 100 / PM_RUN_INST_CMPL", 699 "MetricGroup": "dl1_reloads_percent_per_inst", 700 "MetricName": "l1_ld_miss_rate_percent" 701 }, 702 { 703 "BriefDescription": "% of DL1 misses that result in a cache reload", 704 "MetricExpr": "PM_L1_DCACHE_RELOAD_VALID * 100 / PM_LD_MISS_L1", 705 "MetricGroup": "dl1_reloads_percent_per_ref", 706 "MetricName": "dl1_miss_reloads_percent" 707 }, 708 { 709 "BriefDescription": "% of DL1 dL1_Reloads from Distant L2 or L3 (Modified)", 710 "MetricExpr": "PM_DATA_FROM_DL2L3_MOD * 100 / PM_L1_DCACHE_RELOAD_VALID", 711 "MetricGroup": "dl1_reloads_percent_per_ref", 712 "MetricName": "dl1_reload_from_dl2l3_mod_percent" 713 }, 714 { 715 "BriefDescription": "% of DL1 dL1_Reloads from Distant L2 or L3 (Shared)", 716 "MetricExpr": "PM_DATA_FROM_DL2L3_SHR * 100 / PM_L1_DCACHE_RELOAD_VALID", 717 "MetricGroup": "dl1_reloads_percent_per_ref", 718 "MetricName": "dl1_reload_from_dl2l3_shr_percent" 719 }, 720 { 721 "BriefDescription": "% of DL1 dL1_Reloads from Distant Memory", 722 "MetricExpr": "PM_DATA_FROM_DMEM * 100 / PM_L1_DCACHE_RELOAD_VALID", 723 "MetricGroup": "dl1_reloads_percent_per_ref", 724 "MetricName": "dl1_reload_from_dmem_percent" 725 }, 726 { 727 "BriefDescription": "% of DL1 reloads from Private L2, other core", 728 "MetricExpr": "PM_DATA_FROM_L21_MOD * 100 / PM_L1_DCACHE_RELOAD_VALID", 729 "MetricGroup": "dl1_reloads_percent_per_ref", 730 "MetricName": "dl1_reload_from_l21_mod_percent" 731 }, 732 { 733 "BriefDescription": "% of DL1 reloads from Private L2, other core", 734 "MetricExpr": "PM_DATA_FROM_L21_SHR * 100 / PM_L1_DCACHE_RELOAD_VALID", 735 "MetricGroup": "dl1_reloads_percent_per_ref", 736 "MetricName": "dl1_reload_from_l21_shr_percent" 737 }, 738 { 739 "BriefDescription": "% of DL1 Reloads from sources beyond the local L2", 740 "MetricExpr": "PM_DATA_FROM_L2MISS * 100 / PM_L1_DCACHE_RELOAD_VALID", 741 "MetricGroup": "dl1_reloads_percent_per_ref", 742 "MetricName": "dl1_reload_from_l2_miss_percent" 743 }, 744 { 745 "BriefDescription": "% of DL1 reloads from L2", 746 "MetricExpr": "PM_DATA_FROM_L2 * 100 / PM_L1_DCACHE_RELOAD_VALID", 747 "MetricGroup": "dl1_reloads_percent_per_ref", 748 "MetricName": "dl1_reload_from_l2_percent" 749 }, 750 { 751 "BriefDescription": "% of DL1 reloads from Private L3, other core", 752 "MetricExpr": "PM_DATA_FROM_L31_MOD * 100 / PM_L1_DCACHE_RELOAD_VALID", 753 "MetricGroup": "dl1_reloads_percent_per_ref", 754 "MetricName": "dl1_reload_from_l31_mod_percent" 755 }, 756 { 757 "BriefDescription": "% of DL1 reloads from Private L3, other core", 758 "MetricExpr": "PM_DATA_FROM_L31_SHR * 100 / PM_L1_DCACHE_RELOAD_VALID", 759 "MetricGroup": "dl1_reloads_percent_per_ref", 760 "MetricName": "dl1_reload_from_l31_shr_percent" 761 }, 762 { 763 "BriefDescription": "% of DL1 Reloads that came from L3 and were brought into the L3 by a prefetch", 764 "MetricExpr": "PM_DATA_FROM_L3_MEPF * 100 / PM_L1_DCACHE_RELOAD_VALID", 765 "MetricGroup": "dl1_reloads_percent_per_ref", 766 "MetricName": "dl1_reload_from_l3_mepf_percent" 767 }, 768 { 769 "BriefDescription": "% of DL1 Reloads from sources beyond the local L3", 770 "MetricExpr": "PM_DATA_FROM_L3MISS * 100 / PM_L1_DCACHE_RELOAD_VALID", 771 "MetricGroup": "dl1_reloads_percent_per_ref", 772 "MetricName": "dl1_reload_from_l3_miss_percent" 773 }, 774 { 775 "BriefDescription": "% of DL1 Reloads from L3", 776 "MetricExpr": "PM_DATA_FROM_L3 * 100 / PM_L1_DCACHE_RELOAD_VALID", 777 "MetricGroup": "dl1_reloads_percent_per_ref", 778 "MetricName": "dl1_reload_from_l3_percent" 779 }, 780 { 781 "BriefDescription": "% of DL1 dL1_Reloads from Local Memory", 782 "MetricExpr": "PM_DATA_FROM_LMEM * 100 / PM_L1_DCACHE_RELOAD_VALID", 783 "MetricGroup": "dl1_reloads_percent_per_ref", 784 "MetricName": "dl1_reload_from_lmem_percent" 785 }, 786 { 787 "BriefDescription": "% of DL1 dL1_Reloads from Remote L2 or L3 (Modified)", 788 "MetricExpr": "PM_DATA_FROM_RL2L3_MOD * 100 / PM_L1_DCACHE_RELOAD_VALID", 789 "MetricGroup": "dl1_reloads_percent_per_ref", 790 "MetricName": "dl1_reload_from_rl2l3_mod_percent" 791 }, 792 { 793 "BriefDescription": "% of DL1 dL1_Reloads from Remote L2 or L3 (Shared)", 794 "MetricExpr": "PM_DATA_FROM_RL2L3_SHR * 100 / PM_L1_DCACHE_RELOAD_VALID", 795 "MetricGroup": "dl1_reloads_percent_per_ref", 796 "MetricName": "dl1_reload_from_rl2l3_shr_percent" 797 }, 798 { 799 "BriefDescription": "% of DL1 dL1_Reloads from Remote Memory", 800 "MetricExpr": "PM_DATA_FROM_RMEM * 100 / PM_L1_DCACHE_RELOAD_VALID", 801 "MetricGroup": "dl1_reloads_percent_per_ref", 802 "MetricName": "dl1_reload_from_rmem_percent" 803 }, 804 { 805 "BriefDescription": "estimate of dl2l3 distant MOD miss rates with measured DL2L3 MOD latency as a %of dcache miss cpi", 806 "MetricExpr": "PM_DATA_FROM_DL2L3_MOD * PM_MRK_DATA_FROM_DL2L3_MOD_CYC / PM_MRK_DATA_FROM_DL2L3_MOD / PM_CMPLU_STALL_DCACHE_MISS *100", 807 "MetricGroup": "estimated_dcache_miss_cpi", 808 "MetricName": "dl2l3_mod_cpi_percent" 809 }, 810 { 811 "BriefDescription": "estimate of dl2l3 distant SHR miss rates with measured DL2L3 SHR latency as a %of dcache miss cpi", 812 "MetricExpr": "PM_DATA_FROM_DL2L3_SHR * PM_MRK_DATA_FROM_DL2L3_SHR_CYC / PM_MRK_DATA_FROM_DL2L3_SHR / PM_CMPLU_STALL_DCACHE_MISS *100", 813 "MetricGroup": "estimated_dcache_miss_cpi", 814 "MetricName": "dl2l3_shr_cpi_percent" 815 }, 816 { 817 "BriefDescription": "estimate of distant L4 miss rates with measured DL4 latency as a %of dcache miss cpi", 818 "MetricExpr": "PM_DATA_FROM_DL4 * PM_MRK_DATA_FROM_DL4_CYC / PM_MRK_DATA_FROM_DL4 / PM_CMPLU_STALL_DCACHE_MISS *100", 819 "MetricGroup": "estimated_dcache_miss_cpi", 820 "MetricName": "dl4_cpi_percent" 821 }, 822 { 823 "BriefDescription": "estimate of distant memory miss rates with measured DMEM latency as a %of dcache miss cpi", 824 "MetricExpr": "PM_DATA_FROM_DMEM * PM_MRK_DATA_FROM_DMEM_CYC / PM_MRK_DATA_FROM_DMEM / PM_CMPLU_STALL_DCACHE_MISS *100", 825 "MetricGroup": "estimated_dcache_miss_cpi", 826 "MetricName": "dmem_cpi_percent" 827 }, 828 { 829 "BriefDescription": "estimate of dl21 MOD miss rates with measured L21 MOD latency as a %of dcache miss cpi", 830 "MetricExpr": "PM_DATA_FROM_L21_MOD * PM_MRK_DATA_FROM_L21_MOD_CYC / PM_MRK_DATA_FROM_L21_MOD / PM_CMPLU_STALL_DCACHE_MISS *100", 831 "MetricGroup": "estimated_dcache_miss_cpi", 832 "MetricName": "l21_mod_cpi_percent" 833 }, 834 { 835 "BriefDescription": "estimate of dl21 SHR miss rates with measured L21 SHR latency as a %of dcache miss cpi", 836 "MetricExpr": "PM_DATA_FROM_L21_SHR * PM_MRK_DATA_FROM_L21_SHR_CYC / PM_MRK_DATA_FROM_L21_SHR / PM_CMPLU_STALL_DCACHE_MISS *100", 837 "MetricGroup": "estimated_dcache_miss_cpi", 838 "MetricName": "l21_shr_cpi_percent" 839 }, 840 { 841 "BriefDescription": "estimate of dl2 miss rates with measured L2 latency as a %of dcache miss cpi", 842 "MetricExpr": "PM_DATA_FROM_L2 * PM_MRK_DATA_FROM_L2_CYC / PM_MRK_DATA_FROM_L2 / PM_CMPLU_STALL_DCACHE_MISS *100", 843 "MetricGroup": "estimated_dcache_miss_cpi", 844 "MetricName": "l2_cpi_percent" 845 }, 846 { 847 "BriefDescription": "estimate of dl31 MOD miss rates with measured L31 MOD latency as a %of dcache miss cpi", 848 "MetricExpr": "PM_DATA_FROM_L31_MOD * PM_MRK_DATA_FROM_L31_MOD_CYC / PM_MRK_DATA_FROM_L31_MOD / PM_CMPLU_STALL_DCACHE_MISS *100", 849 "MetricGroup": "estimated_dcache_miss_cpi", 850 "MetricName": "l31_mod_cpi_percent" 851 }, 852 { 853 "BriefDescription": "estimate of dl31 SHR miss rates with measured L31 SHR latency as a %of dcache miss cpi", 854 "MetricExpr": "PM_DATA_FROM_L31_SHR * PM_MRK_DATA_FROM_L31_SHR_CYC / PM_MRK_DATA_FROM_L31_SHR / PM_CMPLU_STALL_DCACHE_MISS *100", 855 "MetricGroup": "estimated_dcache_miss_cpi", 856 "MetricName": "l31_shr_cpi_percent" 857 }, 858 { 859 "BriefDescription": "estimate of dl3 miss rates with measured L3 latency as a % of dcache miss cpi", 860 "MetricExpr": "PM_DATA_FROM_L3 * PM_MRK_DATA_FROM_L3_CYC / PM_MRK_DATA_FROM_L3 / PM_CMPLU_STALL_DCACHE_MISS * 100", 861 "MetricGroup": "estimated_dcache_miss_cpi", 862 "MetricName": "l3_cpi_percent" 863 }, 864 { 865 "BriefDescription": "estimate of Local memory miss rates with measured LMEM latency as a %of dcache miss cpi", 866 "MetricExpr": "PM_DATA_FROM_LMEM * PM_MRK_DATA_FROM_LMEM_CYC / PM_MRK_DATA_FROM_LMEM / PM_CMPLU_STALL_DCACHE_MISS *100", 867 "MetricGroup": "estimated_dcache_miss_cpi", 868 "MetricName": "lmem_cpi_percent" 869 }, 870 { 871 "BriefDescription": "estimate of dl2l3 remote MOD miss rates with measured RL2L3 MOD latency as a %of dcache miss cpi", 872 "MetricExpr": "PM_DATA_FROM_RL2L3_MOD * PM_MRK_DATA_FROM_RL2L3_MOD_CYC / PM_MRK_DATA_FROM_RL2L3_MOD / PM_CMPLU_STALL_DCACHE_MISS *100", 873 "MetricGroup": "estimated_dcache_miss_cpi", 874 "MetricName": "rl2l3_mod_cpi_percent" 875 }, 876 { 877 "BriefDescription": "estimate of dl2l3 shared miss rates with measured RL2L3 SHR latency as a %of dcache miss cpi", 878 "MetricExpr": "PM_DATA_FROM_RL2L3_SHR * PM_MRK_DATA_FROM_RL2L3_SHR_CYC / PM_MRK_DATA_FROM_RL2L3_SHR / PM_CMPLU_STALL_DCACHE_MISS * 100", 879 "MetricGroup": "estimated_dcache_miss_cpi", 880 "MetricName": "rl2l3_shr_cpi_percent" 881 }, 882 { 883 "BriefDescription": "estimate of remote L4 miss rates with measured RL4 latency as a %of dcache miss cpi", 884 "MetricExpr": "PM_DATA_FROM_RL4 * PM_MRK_DATA_FROM_RL4_CYC / PM_MRK_DATA_FROM_RL4 / PM_CMPLU_STALL_DCACHE_MISS *100", 885 "MetricGroup": "estimated_dcache_miss_cpi", 886 "MetricName": "rl4_cpi_percent" 887 }, 888 { 889 "BriefDescription": "estimate of remote memory miss rates with measured RMEM latency as a %of dcache miss cpi", 890 "MetricExpr": "PM_DATA_FROM_RMEM * PM_MRK_DATA_FROM_RMEM_CYC / PM_MRK_DATA_FROM_RMEM / PM_CMPLU_STALL_DCACHE_MISS *100", 891 "MetricGroup": "estimated_dcache_miss_cpi", 892 "MetricName": "rmem_cpi_percent" 893 }, 894 { 895 "BriefDescription": "Branch Mispredict flushes per instruction", 896 "MetricExpr": "PM_FLUSH_MPRED / PM_RUN_INST_CMPL * 100", 897 "MetricGroup": "general", 898 "MetricName": "br_mpred_flush_rate_percent" 899 }, 900 { 901 "BriefDescription": "Cycles per instruction", 902 "MetricExpr": "PM_CYC / PM_INST_CMPL", 903 "MetricGroup": "general", 904 "MetricName": "cpi" 905 }, 906 { 907 "BriefDescription": "GCT empty cycles", 908 "MetricExpr": "(PM_FLUSH_DISP / PM_RUN_INST_CMPL) * 100", 909 "MetricGroup": "general", 910 "MetricName": "disp_flush_rate_percent" 911 }, 912 { 913 "BriefDescription": "% DTLB miss rate per inst", 914 "MetricExpr": "PM_DTLB_MISS / PM_RUN_INST_CMPL *100", 915 "MetricGroup": "general", 916 "MetricName": "dtlb_miss_rate_percent" 917 }, 918 { 919 "BriefDescription": "Flush rate (%)", 920 "MetricExpr": "PM_FLUSH * 100 / PM_RUN_INST_CMPL", 921 "MetricGroup": "general", 922 "MetricName": "flush_rate_percent" 923 }, 924 { 925 "BriefDescription": "Instructions per cycles", 926 "MetricExpr": "PM_INST_CMPL / PM_CYC", 927 "MetricGroup": "general", 928 "MetricName": "ipc" 929 }, 930 { 931 "BriefDescription": "% ITLB miss rate per inst", 932 "MetricExpr": "PM_ITLB_MISS / PM_RUN_INST_CMPL *100", 933 "MetricGroup": "general", 934 "MetricName": "itlb_miss_rate_percent" 935 }, 936 { 937 "BriefDescription": "Percentage of L1 load misses per L1 load ref", 938 "MetricExpr": "PM_LD_MISS_L1 / PM_LD_REF_L1 * 100", 939 "MetricGroup": "general", 940 "MetricName": "l1_ld_miss_ratio_percent" 941 }, 942 { 943 "BriefDescription": "Percentage of L1 store misses per run instruction", 944 "MetricExpr": "PM_ST_MISS_L1 * 100 / PM_RUN_INST_CMPL", 945 "MetricGroup": "general", 946 "MetricName": "l1_st_miss_rate_percent" 947 }, 948 { 949 "BriefDescription": "Percentage of L1 store misses per L1 store ref", 950 "MetricExpr": "PM_ST_MISS_L1 / PM_ST_FIN * 100", 951 "MetricGroup": "general", 952 "MetricName": "l1_st_miss_ratio_percent" 953 }, 954 { 955 "BriefDescription": "L2 Instruction Miss Rate (per instruction)(%)", 956 "MetricExpr": "PM_INST_FROM_L2MISS * 100 / PM_RUN_INST_CMPL", 957 "MetricGroup": "general", 958 "MetricName": "l2_inst_miss_rate_percent" 959 }, 960 { 961 "BriefDescription": "L2 dmand Load Miss Rate (per run instruction)(%)", 962 "MetricExpr": "PM_DATA_FROM_L2MISS * 100 / PM_RUN_INST_CMPL", 963 "MetricGroup": "general", 964 "MetricName": "l2_ld_miss_rate_percent" 965 }, 966 { 967 "BriefDescription": "L2 PTEG Miss Rate (per run instruction)(%)", 968 "MetricExpr": "PM_DPTEG_FROM_L2MISS * 100 / PM_RUN_INST_CMPL", 969 "MetricGroup": "general", 970 "MetricName": "l2_pteg_miss_rate_percent" 971 }, 972 { 973 "BriefDescription": "L3 Instruction Miss Rate (per instruction)(%)", 974 "MetricExpr": "PM_INST_FROM_L3MISS * 100 / PM_RUN_INST_CMPL", 975 "MetricGroup": "general", 976 "MetricName": "l3_inst_miss_rate_percent" 977 }, 978 { 979 "BriefDescription": "L3 demand Load Miss Rate (per run instruction)(%)", 980 "MetricExpr": "PM_DATA_FROM_L3MISS * 100 / PM_RUN_INST_CMPL", 981 "MetricGroup": "general", 982 "MetricName": "l3_ld_miss_rate_percent" 983 }, 984 { 985 "BriefDescription": "L3 PTEG Miss Rate (per run instruction)(%)", 986 "MetricExpr": "PM_DPTEG_FROM_L3MISS * 100 / PM_RUN_INST_CMPL", 987 "MetricGroup": "general", 988 "MetricName": "l3_pteg_miss_rate_percent" 989 }, 990 { 991 "BriefDescription": "Run cycles per cycle", 992 "MetricExpr": "PM_RUN_CYC / PM_CYC*100", 993 "MetricGroup": "general", 994 "MetricName": "run_cycles_percent" 995 }, 996 { 997 "BriefDescription": "Instruction dispatch-to-completion ratio", 998 "MetricExpr": "PM_INST_DISP / PM_INST_CMPL", 999 "MetricGroup": "general", 1000 "MetricName": "speculation" 1001 }, 1002 { 1003 "BriefDescription": "% of ICache reloads from Distant L2 or L3 (Modified) per Inst", 1004 "MetricExpr": "PM_INST_FROM_DL2L3_MOD * 100 / PM_RUN_INST_CMPL", 1005 "MetricGroup": "instruction_misses_percent_per_inst", 1006 "MetricName": "inst_from_dl2l3_mod_rate_percent" 1007 }, 1008 { 1009 "BriefDescription": "% of ICache reloads from Distant L2 or L3 (Shared) per Inst", 1010 "MetricExpr": "PM_INST_FROM_DL2L3_SHR * 100 / PM_RUN_INST_CMPL", 1011 "MetricGroup": "instruction_misses_percent_per_inst", 1012 "MetricName": "inst_from_dl2l3_shr_rate_percent" 1013 }, 1014 { 1015 "BriefDescription": "% of ICache reloads from Distant L4 per Inst", 1016 "MetricExpr": "PM_INST_FROM_DL4 * 100 / PM_RUN_INST_CMPL", 1017 "MetricGroup": "instruction_misses_percent_per_inst", 1018 "MetricName": "inst_from_dl4_rate_percent" 1019 }, 1020 { 1021 "BriefDescription": "% of ICache reloads from Distant Memory per Inst", 1022 "MetricExpr": "PM_INST_FROM_DMEM * 100 / PM_RUN_INST_CMPL", 1023 "MetricGroup": "instruction_misses_percent_per_inst", 1024 "MetricName": "inst_from_dmem_rate_percent" 1025 }, 1026 { 1027 "BriefDescription": "% of ICache reloads from Private L2, other core per Inst", 1028 "MetricExpr": "PM_INST_FROM_L21_MOD * 100 / PM_RUN_INST_CMPL", 1029 "MetricGroup": "instruction_misses_percent_per_inst", 1030 "MetricName": "inst_from_l21_mod_rate_percent" 1031 }, 1032 { 1033 "BriefDescription": "% of ICache reloads from Private L2, other core per Inst", 1034 "MetricExpr": "PM_INST_FROM_L21_SHR * 100 / PM_RUN_INST_CMPL", 1035 "MetricGroup": "instruction_misses_percent_per_inst", 1036 "MetricName": "inst_from_l21_shr_rate_percent" 1037 }, 1038 { 1039 "BriefDescription": "% of ICache reloads from L2 per Inst", 1040 "MetricExpr": "PM_INST_FROM_L2 * 100 / PM_RUN_INST_CMPL", 1041 "MetricGroup": "instruction_misses_percent_per_inst", 1042 "MetricName": "inst_from_l2_rate_percent" 1043 }, 1044 { 1045 "BriefDescription": "% of ICache reloads from Private L3, other core per Inst", 1046 "MetricExpr": "PM_INST_FROM_L31_MOD * 100 / PM_RUN_INST_CMPL", 1047 "MetricGroup": "instruction_misses_percent_per_inst", 1048 "MetricName": "inst_from_l31_mod_rate_percent" 1049 }, 1050 { 1051 "BriefDescription": "% of ICache reloads from Private L3 other core per Inst", 1052 "MetricExpr": "PM_INST_FROM_L31_SHR * 100 / PM_RUN_INST_CMPL", 1053 "MetricGroup": "instruction_misses_percent_per_inst", 1054 "MetricName": "inst_from_l31_shr_rate_percent" 1055 }, 1056 { 1057 "BriefDescription": "% of ICache reloads from L3 per Inst", 1058 "MetricExpr": "PM_INST_FROM_L3 * 100 / PM_RUN_INST_CMPL", 1059 "MetricGroup": "instruction_misses_percent_per_inst", 1060 "MetricName": "inst_from_l3_rate_percent" 1061 }, 1062 { 1063 "BriefDescription": "% of ICache reloads from Local L4 per Inst", 1064 "MetricExpr": "PM_INST_FROM_LL4 * 100 / PM_RUN_INST_CMPL", 1065 "MetricGroup": "instruction_misses_percent_per_inst", 1066 "MetricName": "inst_from_ll4_rate_percent" 1067 }, 1068 { 1069 "BriefDescription": "% of ICache reloads from Local Memory per Inst", 1070 "MetricExpr": "PM_INST_FROM_LMEM * 100 / PM_RUN_INST_CMPL", 1071 "MetricGroup": "instruction_misses_percent_per_inst", 1072 "MetricName": "inst_from_lmem_rate_percent" 1073 }, 1074 { 1075 "BriefDescription": "% of ICache reloads from Remote L2 or L3 (Modified) per Inst", 1076 "MetricExpr": "PM_INST_FROM_RL2L3_MOD * 100 / PM_RUN_INST_CMPL", 1077 "MetricGroup": "instruction_misses_percent_per_inst", 1078 "MetricName": "inst_from_rl2l3_mod_rate_percent" 1079 }, 1080 { 1081 "BriefDescription": "% of ICache reloads from Remote L2 or L3 (Shared) per Inst", 1082 "MetricExpr": "PM_INST_FROM_RL2L3_SHR * 100 / PM_RUN_INST_CMPL", 1083 "MetricGroup": "instruction_misses_percent_per_inst", 1084 "MetricName": "inst_from_rl2l3_shr_rate_percent" 1085 }, 1086 { 1087 "BriefDescription": "% of ICache reloads from Remote L4 per Inst", 1088 "MetricExpr": "PM_INST_FROM_RL4 * 100 / PM_RUN_INST_CMPL", 1089 "MetricGroup": "instruction_misses_percent_per_inst", 1090 "MetricName": "inst_from_rl4_rate_percent" 1091 }, 1092 { 1093 "BriefDescription": "% of ICache reloads from Remote Memory per Inst", 1094 "MetricExpr": "PM_INST_FROM_RMEM * 100 / PM_RUN_INST_CMPL", 1095 "MetricGroup": "instruction_misses_percent_per_inst", 1096 "MetricName": "inst_from_rmem_rate_percent" 1097 }, 1098 { 1099 "BriefDescription": "Instruction Cache Miss Rate (Per run Instruction)(%)", 1100 "MetricExpr": "PM_L1_ICACHE_MISS * 100 / PM_RUN_INST_CMPL", 1101 "MetricGroup": "instruction_misses_percent_per_inst", 1102 "MetricName": "l1_inst_miss_rate_percent" 1103 }, 1104 { 1105 "BriefDescription": "Icache Fetchs per Icache Miss", 1106 "MetricExpr": "(PM_L1_ICACHE_MISS - PM_IC_PREF_WRITE) / PM_L1_ICACHE_MISS", 1107 "MetricGroup": "instruction_stats_percent_per_ref", 1108 "MetricName": "icache_miss_reload" 1109 }, 1110 { 1111 "BriefDescription": "% of ICache reloads due to prefetch", 1112 "MetricExpr": "PM_IC_PREF_WRITE * 100 / PM_L1_ICACHE_MISS", 1113 "MetricGroup": "instruction_stats_percent_per_ref", 1114 "MetricName": "icache_pref_percent" 1115 }, 1116 { 1117 "BriefDescription": "% of ICache reloads from Distant L2 or L3 (Modified)", 1118 "MetricExpr": "PM_INST_FROM_DL2L3_MOD * 100 / PM_L1_ICACHE_MISS", 1119 "MetricGroup": "instruction_stats_percent_per_ref", 1120 "MetricName": "inst_from_dl2l3_mod_percent" 1121 }, 1122 { 1123 "BriefDescription": "% of ICache reloads from Distant L2 or L3 (Shared)", 1124 "MetricExpr": "PM_INST_FROM_DL2L3_SHR * 100 / PM_L1_ICACHE_MISS", 1125 "MetricGroup": "instruction_stats_percent_per_ref", 1126 "MetricName": "inst_from_dl2l3_shr_percent" 1127 }, 1128 { 1129 "BriefDescription": "% of ICache reloads from Distant L4", 1130 "MetricExpr": "PM_INST_FROM_DL4 * 100 / PM_L1_ICACHE_MISS", 1131 "MetricGroup": "instruction_stats_percent_per_ref", 1132 "MetricName": "inst_from_dl4_percent" 1133 }, 1134 { 1135 "BriefDescription": "% of ICache reloads from Distant Memory", 1136 "MetricExpr": "PM_INST_FROM_DMEM * 100 / PM_L1_ICACHE_MISS", 1137 "MetricGroup": "instruction_stats_percent_per_ref", 1138 "MetricName": "inst_from_dmem_percent" 1139 }, 1140 { 1141 "BriefDescription": "% of ICache reloads from Private L2, other core", 1142 "MetricExpr": "PM_INST_FROM_L21_MOD * 100 / PM_L1_ICACHE_MISS", 1143 "MetricGroup": "instruction_stats_percent_per_ref", 1144 "MetricName": "inst_from_l21_mod_percent" 1145 }, 1146 { 1147 "BriefDescription": "% of ICache reloads from Private L2, other core", 1148 "MetricExpr": "PM_INST_FROM_L21_SHR * 100 / PM_L1_ICACHE_MISS", 1149 "MetricGroup": "instruction_stats_percent_per_ref", 1150 "MetricName": "inst_from_l21_shr_percent" 1151 }, 1152 { 1153 "BriefDescription": "% of ICache reloads from L2", 1154 "MetricExpr": "PM_INST_FROM_L2 * 100 / PM_L1_ICACHE_MISS", 1155 "MetricGroup": "instruction_stats_percent_per_ref", 1156 "MetricName": "inst_from_l2_percent" 1157 }, 1158 { 1159 "BriefDescription": "% of ICache reloads from Private L3, other core", 1160 "MetricExpr": "PM_INST_FROM_L31_MOD * 100 / PM_L1_ICACHE_MISS", 1161 "MetricGroup": "instruction_stats_percent_per_ref", 1162 "MetricName": "inst_from_l31_mod_percent" 1163 }, 1164 { 1165 "BriefDescription": "% of ICache reloads from Private L3, other core", 1166 "MetricExpr": "PM_INST_FROM_L31_SHR * 100 / PM_L1_ICACHE_MISS", 1167 "MetricGroup": "instruction_stats_percent_per_ref", 1168 "MetricName": "inst_from_l31_shr_percent" 1169 }, 1170 { 1171 "BriefDescription": "% of ICache reloads from L3", 1172 "MetricExpr": "PM_INST_FROM_L3 * 100 / PM_L1_ICACHE_MISS", 1173 "MetricGroup": "instruction_stats_percent_per_ref", 1174 "MetricName": "inst_from_l3_percent" 1175 }, 1176 { 1177 "BriefDescription": "% of ICache reloads from Local L4", 1178 "MetricExpr": "PM_INST_FROM_LL4 * 100 / PM_L1_ICACHE_MISS", 1179 "MetricGroup": "instruction_stats_percent_per_ref", 1180 "MetricName": "inst_from_ll4_percent" 1181 }, 1182 { 1183 "BriefDescription": "% of ICache reloads from Local Memory", 1184 "MetricExpr": "PM_INST_FROM_LMEM * 100 / PM_L1_ICACHE_MISS", 1185 "MetricGroup": "instruction_stats_percent_per_ref", 1186 "MetricName": "inst_from_lmem_percent" 1187 }, 1188 { 1189 "BriefDescription": "% of ICache reloads from Remote L2 or L3 (Modified)", 1190 "MetricExpr": "PM_INST_FROM_RL2L3_MOD * 100 / PM_L1_ICACHE_MISS", 1191 "MetricGroup": "instruction_stats_percent_per_ref", 1192 "MetricName": "inst_from_rl2l3_mod_percent" 1193 }, 1194 { 1195 "BriefDescription": "% of ICache reloads from Remote L2 or L3 (Shared)", 1196 "MetricExpr": "PM_INST_FROM_RL2L3_SHR * 100 / PM_L1_ICACHE_MISS", 1197 "MetricGroup": "instruction_stats_percent_per_ref", 1198 "MetricName": "inst_from_rl2l3_shr_percent" 1199 }, 1200 { 1201 "BriefDescription": "% of ICache reloads from Remote L4", 1202 "MetricExpr": "PM_INST_FROM_RL4 * 100 / PM_L1_ICACHE_MISS", 1203 "MetricGroup": "instruction_stats_percent_per_ref", 1204 "MetricName": "inst_from_rl4_percent" 1205 }, 1206 { 1207 "BriefDescription": "% of ICache reloads from Remote Memory", 1208 "MetricExpr": "PM_INST_FROM_RMEM * 100 / PM_L1_ICACHE_MISS", 1209 "MetricGroup": "instruction_stats_percent_per_ref", 1210 "MetricName": "inst_from_rmem_percent" 1211 }, 1212 { 1213 "BriefDescription": "Demand load misses as a % of L2 LD dispatches (per thread)", 1214 "MetricExpr": "PM_L1_DCACHE_RELOAD_VALID / (PM_L2_LD / 2) * 100", 1215 "MetricGroup": "l2_stats", 1216 "MetricName": "l2_dem_ld_disp_percent" 1217 }, 1218 { 1219 "BriefDescription": "L2 Store misses as a % of total L2 Store dispatches (per thread)", 1220 "MetricExpr": "PM_L2_ST_MISS / PM_L2_ST * 100", 1221 "MetricGroup": "l2_stats", 1222 "MetricName": "l2_st_miss_ratio_percent" 1223 }, 1224 { 1225 "BriefDescription": "L2 stores that require a cache write (4 pclks per disp attempt) % of pclks", 1226 "MetricExpr": "((PM_L2_ST_DISP/2)*4) / PM_RUN_CYC * 100", 1227 "MetricGroup": "l2_stats", 1228 "MetricName": "l2_st_wr_util" 1229 }, 1230 { 1231 "BriefDescription": "Average icache miss latency", 1232 "MetricExpr": "PM_IC_DEMAND_CYC / PM_IC_DEMAND_REQ", 1233 "MetricGroup": "latency", 1234 "MetricName": "average_il1_miss_latency" 1235 }, 1236 { 1237 "BriefDescription": "Marked L2L3 remote Load latency", 1238 "MetricExpr": "PM_MRK_DATA_FROM_DL2L3_MOD_CYC/ PM_MRK_DATA_FROM_DL2L3_MOD", 1239 "MetricGroup": "latency", 1240 "MetricName": "dl2l3_mod_latency" 1241 }, 1242 { 1243 "BriefDescription": "Marked L2L3 distant Load latency", 1244 "MetricExpr": "PM_MRK_DATA_FROM_DL2L3_SHR_CYC/ PM_MRK_DATA_FROM_DL2L3_SHR", 1245 "MetricGroup": "latency", 1246 "MetricName": "dl2l3_shr_latency" 1247 }, 1248 { 1249 "BriefDescription": "Distant L4 average load latency", 1250 "MetricExpr": "PM_MRK_DATA_FROM_DL4_CYC/ PM_MRK_DATA_FROM_DL4", 1251 "MetricGroup": "latency", 1252 "MetricName": "dl4_latency" 1253 }, 1254 { 1255 "BriefDescription": "Marked Dmem Load latency", 1256 "MetricExpr": "PM_MRK_DATA_FROM_DMEM_CYC/ PM_MRK_DATA_FROM_DMEM", 1257 "MetricGroup": "latency", 1258 "MetricName": "dmem_latency" 1259 }, 1260 { 1261 "BriefDescription": "average L1 miss latency using marked events", 1262 "MetricExpr": "PM_MRK_LD_MISS_L1_CYC / PM_MRK_LD_MISS_L1", 1263 "MetricGroup": "latency", 1264 "MetricName": "estimated_dl1miss_latency" 1265 }, 1266 { 1267 "BriefDescription": "Marked L21 Load latency", 1268 "MetricExpr": "PM_MRK_DATA_FROM_L21_MOD_CYC/ PM_MRK_DATA_FROM_L21_MOD", 1269 "MetricGroup": "latency", 1270 "MetricName": "l21_mod_latency" 1271 }, 1272 { 1273 "BriefDescription": "Marked L21 Load latency", 1274 "MetricExpr": "PM_MRK_DATA_FROM_L21_SHR_CYC/ PM_MRK_DATA_FROM_L21_SHR", 1275 "MetricGroup": "latency", 1276 "MetricName": "l21_shr_latency" 1277 }, 1278 { 1279 "BriefDescription": "Marked L2 Load latency", 1280 "MetricExpr": "PM_MRK_DATA_FROM_L2_CYC/ PM_MRK_DATA_FROM_L2", 1281 "MetricGroup": "latency", 1282 "MetricName": "l2_latency" 1283 }, 1284 { 1285 "BriefDescription": "Marked L31 Load latency", 1286 "MetricExpr": "PM_MRK_DATA_FROM_L31_MOD_CYC/ PM_MRK_DATA_FROM_L31_MOD", 1287 "MetricGroup": "latency", 1288 "MetricName": "l31_mod_latency" 1289 }, 1290 { 1291 "BriefDescription": "Marked L31 Load latency", 1292 "MetricExpr": "PM_MRK_DATA_FROM_L31_SHR_CYC/ PM_MRK_DATA_FROM_L31_SHR", 1293 "MetricGroup": "latency", 1294 "MetricName": "l31_shr_latency" 1295 }, 1296 { 1297 "BriefDescription": "Marked L3 Load latency", 1298 "MetricExpr": "PM_MRK_DATA_FROM_L3_CYC/ PM_MRK_DATA_FROM_L3", 1299 "MetricGroup": "latency", 1300 "MetricName": "l3_latency" 1301 }, 1302 { 1303 "BriefDescription": "Local L4 average load latency", 1304 "MetricExpr": "PM_MRK_DATA_FROM_LL4_CYC/ PM_MRK_DATA_FROM_LL4", 1305 "MetricGroup": "latency", 1306 "MetricName": "ll4_latency" 1307 }, 1308 { 1309 "BriefDescription": "Marked Lmem Load latency", 1310 "MetricExpr": "PM_MRK_DATA_FROM_LMEM_CYC/ PM_MRK_DATA_FROM_LMEM", 1311 "MetricGroup": "latency", 1312 "MetricName": "lmem_latency" 1313 }, 1314 { 1315 "BriefDescription": "Marked L2L3 remote Load latency", 1316 "MetricExpr": "PM_MRK_DATA_FROM_RL2L3_MOD_CYC/ PM_MRK_DATA_FROM_RL2L3_MOD", 1317 "MetricGroup": "latency", 1318 "MetricName": "rl2l3_mod_latency" 1319 }, 1320 { 1321 "BriefDescription": "Marked L2L3 remote Load latency", 1322 "MetricExpr": "PM_MRK_DATA_FROM_RL2L3_SHR_CYC/ PM_MRK_DATA_FROM_RL2L3_SHR", 1323 "MetricGroup": "latency", 1324 "MetricName": "rl2l3_shr_latency" 1325 }, 1326 { 1327 "BriefDescription": "Remote L4 average load latency", 1328 "MetricExpr": "PM_MRK_DATA_FROM_RL4_CYC/ PM_MRK_DATA_FROM_RL4", 1329 "MetricGroup": "latency", 1330 "MetricName": "rl4_latency" 1331 }, 1332 { 1333 "BriefDescription": "Marked Rmem Load latency", 1334 "MetricExpr": "PM_MRK_DATA_FROM_RMEM_CYC/ PM_MRK_DATA_FROM_RMEM", 1335 "MetricGroup": "latency", 1336 "MetricName": "rmem_latency" 1337 }, 1338 { 1339 "BriefDescription": "ERAT miss reject ratio", 1340 "MetricExpr": "PM_LSU_REJECT_ERAT_MISS * 100 / PM_RUN_INST_CMPL", 1341 "MetricGroup": "lsu_rejects", 1342 "MetricName": "erat_reject_rate_percent" 1343 }, 1344 { 1345 "BriefDescription": "LHS reject ratio", 1346 "MetricExpr": "PM_LSU_REJECT_LHS *100/ PM_RUN_INST_CMPL", 1347 "MetricGroup": "lsu_rejects", 1348 "MetricName": "lhs_reject_rate_percent" 1349 }, 1350 { 1351 "BriefDescription": "ERAT miss reject ratio", 1352 "MetricExpr": "PM_LSU_REJECT_LMQ_FULL * 100 / PM_RUN_INST_CMPL", 1353 "MetricGroup": "lsu_rejects", 1354 "MetricName": "lmq_full_reject_rate_percent" 1355 }, 1356 { 1357 "BriefDescription": "ERAT miss reject ratio", 1358 "MetricExpr": "PM_LSU_REJECT_LMQ_FULL * 100 / PM_LD_REF_L1", 1359 "MetricGroup": "lsu_rejects", 1360 "MetricName": "lmq_full_reject_ratio_percent" 1361 }, 1362 { 1363 "BriefDescription": "L4 locality(%)", 1364 "MetricExpr": "PM_DATA_FROM_LL4 * 100 / (PM_DATA_FROM_LL4 + PM_DATA_FROM_RL4 + PM_DATA_FROM_DL4)", 1365 "MetricGroup": "memory", 1366 "MetricName": "l4_locality" 1367 }, 1368 { 1369 "BriefDescription": "Ratio of reloads from local L4 to distant L4", 1370 "MetricExpr": "PM_DATA_FROM_LL4 / PM_DATA_FROM_DL4", 1371 "MetricGroup": "memory", 1372 "MetricName": "ld_ll4_per_ld_dmem" 1373 }, 1374 { 1375 "BriefDescription": "Ratio of reloads from local L4 to remote+distant L4", 1376 "MetricExpr": "PM_DATA_FROM_LL4 / (PM_DATA_FROM_DL4 + PM_DATA_FROM_RL4)", 1377 "MetricGroup": "memory", 1378 "MetricName": "ld_ll4_per_ld_mem" 1379 }, 1380 { 1381 "BriefDescription": "Ratio of reloads from local L4 to remote L4", 1382 "MetricExpr": "PM_DATA_FROM_LL4 / PM_DATA_FROM_RL4", 1383 "MetricGroup": "memory", 1384 "MetricName": "ld_ll4_per_ld_rl4" 1385 }, 1386 { 1387 "BriefDescription": "Number of loads from local memory per loads from distant memory", 1388 "MetricExpr": "PM_DATA_FROM_LMEM / PM_DATA_FROM_DMEM", 1389 "MetricGroup": "memory", 1390 "MetricName": "ld_lmem_per_ld_dmem" 1391 }, 1392 { 1393 "BriefDescription": "Number of loads from local memory per loads from remote and distant memory", 1394 "MetricExpr": "PM_DATA_FROM_LMEM / (PM_DATA_FROM_DMEM + PM_DATA_FROM_RMEM)", 1395 "MetricGroup": "memory", 1396 "MetricName": "ld_lmem_per_ld_mem" 1397 }, 1398 { 1399 "BriefDescription": "Number of loads from local memory per loads from remote memory", 1400 "MetricExpr": "PM_DATA_FROM_LMEM / PM_DATA_FROM_RMEM", 1401 "MetricGroup": "memory", 1402 "MetricName": "ld_lmem_per_ld_rmem" 1403 }, 1404 { 1405 "BriefDescription": "Number of loads from remote memory per loads from distant memory", 1406 "MetricExpr": "PM_DATA_FROM_RMEM / PM_DATA_FROM_DMEM", 1407 "MetricGroup": "memory", 1408 "MetricName": "ld_rmem_per_ld_dmem" 1409 }, 1410 { 1411 "BriefDescription": "Memory locality", 1412 "MetricExpr": "PM_DATA_FROM_LMEM * 100/ (PM_DATA_FROM_LMEM + PM_DATA_FROM_RMEM + PM_DATA_FROM_DMEM)", 1413 "MetricGroup": "memory", 1414 "MetricName": "mem_locality_percent" 1415 }, 1416 { 1417 "BriefDescription": "L1 Prefetches issued by the prefetch machine per instruction (per thread)", 1418 "MetricExpr": "PM_L1_PREF / PM_RUN_INST_CMPL * 100", 1419 "MetricGroup": "prefetch", 1420 "MetricName": "l1_prefetch_rate_percent" 1421 }, 1422 { 1423 "BriefDescription": "DERAT Miss Rate (per run instruction)(%)", 1424 "MetricExpr": "PM_LSU_DERAT_MISS * 100 / PM_RUN_INST_CMPL", 1425 "MetricGroup": "pteg_reloads_percent_per_inst", 1426 "MetricName": "derat_miss_rate_percent" 1427 }, 1428 { 1429 "BriefDescription": "% of DERAT reloads from Distant L2 or L3 (Modified) per inst", 1430 "MetricExpr": "PM_DPTEG_FROM_DL2L3_MOD * 100 / PM_RUN_INST_CMPL", 1431 "MetricGroup": "pteg_reloads_percent_per_inst", 1432 "MetricName": "pteg_from_dl2l3_mod_rate_percent" 1433 }, 1434 { 1435 "BriefDescription": "% of DERAT reloads from Distant L2 or L3 (Shared) per inst", 1436 "MetricExpr": "PM_DPTEG_FROM_DL2L3_SHR * 100 / PM_RUN_INST_CMPL", 1437 "MetricGroup": "pteg_reloads_percent_per_inst", 1438 "MetricName": "pteg_from_dl2l3_shr_rate_percent" 1439 }, 1440 { 1441 "BriefDescription": "% of DERAT reloads from Distant L4 per inst", 1442 "MetricExpr": "PM_DPTEG_FROM_DL4 * 100 / PM_RUN_INST_CMPL", 1443 "MetricGroup": "pteg_reloads_percent_per_inst", 1444 "MetricName": "pteg_from_dl4_rate_percent" 1445 }, 1446 { 1447 "BriefDescription": "% of DERAT reloads from Distant Memory per inst", 1448 "MetricExpr": "PM_DPTEG_FROM_DMEM * 100 / PM_RUN_INST_CMPL", 1449 "MetricGroup": "pteg_reloads_percent_per_inst", 1450 "MetricName": "pteg_from_dmem_rate_percent" 1451 }, 1452 { 1453 "BriefDescription": "% of DERAT reloads from Private L2, other core per inst", 1454 "MetricExpr": "PM_DPTEG_FROM_L21_MOD * 100 / PM_RUN_INST_CMPL", 1455 "MetricGroup": "pteg_reloads_percent_per_inst", 1456 "MetricName": "pteg_from_l21_mod_rate_percent" 1457 }, 1458 { 1459 "BriefDescription": "% of DERAT reloads from Private L2, other core per inst", 1460 "MetricExpr": "PM_DPTEG_FROM_L21_SHR * 100 / PM_RUN_INST_CMPL", 1461 "MetricGroup": "pteg_reloads_percent_per_inst", 1462 "MetricName": "pteg_from_l21_shr_rate_percent" 1463 }, 1464 { 1465 "BriefDescription": "% of DERAT reloads from L2 per inst", 1466 "MetricExpr": "PM_DPTEG_FROM_L2 * 100 / PM_RUN_INST_CMPL", 1467 "MetricGroup": "pteg_reloads_percent_per_inst", 1468 "MetricName": "pteg_from_l2_rate_percent" 1469 }, 1470 { 1471 "BriefDescription": "% of DERAT reloads from Private L3, other core per inst", 1472 "MetricExpr": "PM_DPTEG_FROM_L31_MOD * 100 / PM_RUN_INST_CMPL", 1473 "MetricGroup": "pteg_reloads_percent_per_inst", 1474 "MetricName": "pteg_from_l31_mod_rate_percent" 1475 }, 1476 { 1477 "BriefDescription": "% of DERAT reloads from Private L3, other core per inst", 1478 "MetricExpr": "PM_DPTEG_FROM_L31_SHR * 100 / PM_RUN_INST_CMPL", 1479 "MetricGroup": "pteg_reloads_percent_per_inst", 1480 "MetricName": "pteg_from_l31_shr_rate_percent" 1481 }, 1482 { 1483 "BriefDescription": "% of DERAT reloads from L3 per inst", 1484 "MetricExpr": "PM_DPTEG_FROM_L3 * 100 / PM_RUN_INST_CMPL", 1485 "MetricGroup": "pteg_reloads_percent_per_inst", 1486 "MetricName": "pteg_from_l3_rate_percent" 1487 }, 1488 { 1489 "BriefDescription": "% of DERAT reloads from Local L4 per inst", 1490 "MetricExpr": "PM_DPTEG_FROM_LL4 * 100 / PM_RUN_INST_CMPL", 1491 "MetricGroup": "pteg_reloads_percent_per_inst", 1492 "MetricName": "pteg_from_ll4_rate_percent" 1493 }, 1494 { 1495 "BriefDescription": "% of DERAT reloads from Local Memory per inst", 1496 "MetricExpr": "PM_DPTEG_FROM_LMEM * 100 / PM_RUN_INST_CMPL", 1497 "MetricGroup": "pteg_reloads_percent_per_inst", 1498 "MetricName": "pteg_from_lmem_rate_percent" 1499 }, 1500 { 1501 "BriefDescription": "% of DERAT reloads from Remote L2 or L3 (Modified) per inst", 1502 "MetricExpr": "PM_DPTEG_FROM_RL2L3_MOD * 100 / PM_RUN_INST_CMPL", 1503 "MetricGroup": "pteg_reloads_percent_per_inst", 1504 "MetricName": "pteg_from_rl2l3_mod_rate_percent" 1505 }, 1506 { 1507 "BriefDescription": "% of DERAT reloads from Remote L2 or L3 (Shared) per inst", 1508 "MetricExpr": "PM_DPTEG_FROM_RL2L3_SHR * 100 / PM_RUN_INST_CMPL", 1509 "MetricGroup": "pteg_reloads_percent_per_inst", 1510 "MetricName": "pteg_from_rl2l3_shr_rate_percent" 1511 }, 1512 { 1513 "BriefDescription": "% of DERAT reloads from Remote L4 per inst", 1514 "MetricExpr": "PM_DPTEG_FROM_RL4 * 100 / PM_RUN_INST_CMPL", 1515 "MetricGroup": "pteg_reloads_percent_per_inst", 1516 "MetricName": "pteg_from_rl4_rate_percent" 1517 }, 1518 { 1519 "BriefDescription": "% of DERAT reloads from Remote Memory per inst", 1520 "MetricExpr": "PM_DPTEG_FROM_RMEM * 100 / PM_RUN_INST_CMPL", 1521 "MetricGroup": "pteg_reloads_percent_per_inst", 1522 "MetricName": "pteg_from_rmem_rate_percent" 1523 }, 1524 { 1525 "BriefDescription": "% of DERAT misses that result in an ERAT reload", 1526 "MetricExpr": "PM_DTLB_MISS * 100 / PM_LSU_DERAT_MISS", 1527 "MetricGroup": "pteg_reloads_percent_per_ref", 1528 "MetricName": "derat_miss_reload_percent" 1529 }, 1530 { 1531 "BriefDescription": "% of DERAT reloads from Distant L2 or L3 (Modified)", 1532 "MetricExpr": "PM_DPTEG_FROM_DL2L3_MOD * 100 / PM_DTLB_MISS", 1533 "MetricGroup": "pteg_reloads_percent_per_ref", 1534 "MetricName": "pteg_from_dl2l3_mod_percent" 1535 }, 1536 { 1537 "BriefDescription": "% of DERAT reloads from Distant L2 or L3 (Shared)", 1538 "MetricExpr": "PM_DPTEG_FROM_DL2L3_SHR * 100 / PM_DTLB_MISS", 1539 "MetricGroup": "pteg_reloads_percent_per_ref", 1540 "MetricName": "pteg_from_dl2l3_shr_percent" 1541 }, 1542 { 1543 "BriefDescription": "% of DERAT reloads from Distant L4", 1544 "MetricExpr": "PM_DPTEG_FROM_DL4 * 100 / PM_DTLB_MISS", 1545 "MetricGroup": "pteg_reloads_percent_per_ref", 1546 "MetricName": "pteg_from_dl4_percent" 1547 }, 1548 { 1549 "BriefDescription": "% of DERAT reloads from Distant Memory", 1550 "MetricExpr": "PM_DPTEG_FROM_DMEM * 100 / PM_DTLB_MISS", 1551 "MetricGroup": "pteg_reloads_percent_per_ref", 1552 "MetricName": "pteg_from_dmem_percent" 1553 }, 1554 { 1555 "BriefDescription": "% of DERAT reloads from Private L2, other core", 1556 "MetricExpr": "PM_DPTEG_FROM_L21_MOD * 100 / PM_DTLB_MISS", 1557 "MetricGroup": "pteg_reloads_percent_per_ref", 1558 "MetricName": "pteg_from_l21_mod_percent" 1559 }, 1560 { 1561 "BriefDescription": "% of DERAT reloads from Private L2, other core", 1562 "MetricExpr": "PM_DPTEG_FROM_L21_SHR * 100 / PM_DTLB_MISS", 1563 "MetricGroup": "pteg_reloads_percent_per_ref", 1564 "MetricName": "pteg_from_l21_shr_percent" 1565 }, 1566 { 1567 "BriefDescription": "% of DERAT reloads from L2", 1568 "MetricExpr": "PM_DPTEG_FROM_L2 * 100 / PM_DTLB_MISS", 1569 "MetricGroup": "pteg_reloads_percent_per_ref", 1570 "MetricName": "pteg_from_l2_percent" 1571 }, 1572 { 1573 "BriefDescription": "% of DERAT reloads from Private L3, other core", 1574 "MetricExpr": "PM_DPTEG_FROM_L31_MOD * 100 / PM_DTLB_MISS", 1575 "MetricGroup": "pteg_reloads_percent_per_ref", 1576 "MetricName": "pteg_from_l31_mod_percent" 1577 }, 1578 { 1579 "BriefDescription": "% of DERAT reloads from Private L3, other core", 1580 "MetricExpr": "PM_DPTEG_FROM_L31_SHR * 100 / PM_DTLB_MISS", 1581 "MetricGroup": "pteg_reloads_percent_per_ref", 1582 "MetricName": "pteg_from_l31_shr_percent" 1583 }, 1584 { 1585 "BriefDescription": "% of DERAT reloads from L3", 1586 "MetricExpr": "PM_DPTEG_FROM_L3 * 100 / PM_DTLB_MISS", 1587 "MetricGroup": "pteg_reloads_percent_per_ref", 1588 "MetricName": "pteg_from_l3_percent" 1589 }, 1590 { 1591 "BriefDescription": "% of DERAT reloads from Local L4", 1592 "MetricExpr": "PM_DPTEG_FROM_LL4 * 100 / PM_DTLB_MISS", 1593 "MetricGroup": "pteg_reloads_percent_per_ref", 1594 "MetricName": "pteg_from_ll4_percent" 1595 }, 1596 { 1597 "BriefDescription": "% of DERAT reloads from Local Memory", 1598 "MetricExpr": "PM_DPTEG_FROM_LMEM * 100 / PM_DTLB_MISS", 1599 "MetricGroup": "pteg_reloads_percent_per_ref", 1600 "MetricName": "pteg_from_lmem_percent" 1601 }, 1602 { 1603 "BriefDescription": "% of DERAT reloads from Remote L2 or L3 (Modified)", 1604 "MetricExpr": "PM_DPTEG_FROM_RL2L3_MOD * 100 / PM_DTLB_MISS", 1605 "MetricGroup": "pteg_reloads_percent_per_ref", 1606 "MetricName": "pteg_from_rl2l3_mod_percent" 1607 }, 1608 { 1609 "BriefDescription": "% of DERAT reloads from Remote L2 or L3 (Shared)", 1610 "MetricExpr": "PM_DPTEG_FROM_RL2L3_SHR * 100 / PM_DTLB_MISS", 1611 "MetricGroup": "pteg_reloads_percent_per_ref", 1612 "MetricName": "pteg_from_rl2l3_shr_percent" 1613 }, 1614 { 1615 "BriefDescription": "% of DERAT reloads from Remote L4", 1616 "MetricExpr": "PM_DPTEG_FROM_RL4 * 100 / PM_DTLB_MISS", 1617 "MetricGroup": "pteg_reloads_percent_per_ref", 1618 "MetricName": "pteg_from_rl4_percent" 1619 }, 1620 { 1621 "BriefDescription": "% of DERAT reloads from Remote Memory", 1622 "MetricExpr": "PM_DPTEG_FROM_RMEM * 100 / PM_DTLB_MISS", 1623 "MetricGroup": "pteg_reloads_percent_per_ref", 1624 "MetricName": "pteg_from_rmem_percent" 1625 }, 1626 { 1627 "BriefDescription": "% DERAT miss rate for 4K page per inst", 1628 "MetricExpr": "PM_DERAT_MISS_4K * 100 / PM_RUN_INST_CMPL", 1629 "MetricGroup": "translation", 1630 "MetricName": "derat_4k_miss_rate_percent" 1631 }, 1632 { 1633 "BriefDescription": "DERAT miss ratio for 4K page", 1634 "MetricExpr": "PM_DERAT_MISS_4K / PM_LSU_DERAT_MISS", 1635 "MetricGroup": "translation", 1636 "MetricName": "derat_4k_miss_ratio" 1637 }, 1638 { 1639 "BriefDescription": "% DERAT miss ratio for 64K page per inst", 1640 "MetricExpr": "PM_DERAT_MISS_64K * 100 / PM_RUN_INST_CMPL", 1641 "MetricGroup": "translation", 1642 "MetricName": "derat_64k_miss_rate_percent" 1643 }, 1644 { 1645 "BriefDescription": "DERAT miss ratio for 64K page", 1646 "MetricExpr": "PM_DERAT_MISS_64K / PM_LSU_DERAT_MISS", 1647 "MetricGroup": "translation", 1648 "MetricName": "derat_64k_miss_ratio" 1649 }, 1650 { 1651 "BriefDescription": "DERAT miss ratio", 1652 "MetricExpr": "PM_LSU_DERAT_MISS / PM_LSU_DERAT_MISS", 1653 "MetricGroup": "translation", 1654 "MetricName": "derat_miss_ratio" 1655 }, 1656 { 1657 "BriefDescription": "% DSLB_Miss_Rate per inst", 1658 "MetricExpr": "PM_DSLB_MISS * 100 / PM_RUN_INST_CMPL", 1659 "MetricGroup": "translation", 1660 "MetricName": "dslb_miss_rate_percent" 1661 }, 1662 { 1663 "BriefDescription": "% ISLB miss rate per inst", 1664 "MetricExpr": "PM_ISLB_MISS * 100 / PM_RUN_INST_CMPL", 1665 "MetricGroup": "translation", 1666 "MetricName": "islb_miss_rate_percent" 1667 }, 1668 { 1669 "BriefDescription": "ANY_SYNC_STALL_CPI", 1670 "MetricExpr": "PM_CMPLU_STALL_ANY_SYNC / PM_RUN_INST_CMPL", 1671 "MetricName": "any_sync_stall_cpi" 1672 }, 1673 { 1674 "BriefDescription": "Avg. more than 1 instructions completed", 1675 "MetricExpr": "PM_INST_CMPL / PM_1PLUS_PPC_CMPL", 1676 "MetricName": "average_completed_instruction_set_size" 1677 }, 1678 { 1679 "BriefDescription": "% Branches per instruction", 1680 "MetricExpr": "PM_BRU_FIN / PM_RUN_INST_CMPL", 1681 "MetricName": "branches_per_inst" 1682 }, 1683 { 1684 "BriefDescription": "Cycles in which at least one instruction completes in this thread", 1685 "MetricExpr": "PM_1PLUS_PPC_CMPL/PM_RUN_INST_CMPL", 1686 "MetricName": "completion_cpi" 1687 }, 1688 { 1689 "BriefDescription": "cycles", 1690 "MetricExpr": "PM_RUN_CYC", 1691 "MetricName": "custom_secs" 1692 }, 1693 { 1694 "BriefDescription": "Percentage Cycles at least one instruction dispatched", 1695 "MetricExpr": "PM_1PLUS_PPC_DISP / PM_CYC * 100", 1696 "MetricName": "cycles_atleast_one_inst_dispatched_percent" 1697 }, 1698 { 1699 "BriefDescription": "Cycles per instruction group", 1700 "MetricExpr": "PM_CYC / PM_1PLUS_PPC_CMPL", 1701 "MetricName": "cycles_per_completed_instructions_set" 1702 }, 1703 { 1704 "BriefDescription": "% of DL1 dL1_Reloads from Distant L4", 1705 "MetricExpr": "PM_DATA_FROM_DL4 * 100 / PM_L1_DCACHE_RELOAD_VALID", 1706 "MetricName": "dl1_reload_from_dl4_percent" 1707 }, 1708 { 1709 "BriefDescription": "% of DL1 Reloads from Distant L4 per Inst", 1710 "MetricExpr": "PM_DATA_FROM_DL4 * 100 / PM_RUN_INST_CMPL", 1711 "MetricName": "dl1_reload_from_dl4_rate_percent" 1712 }, 1713 { 1714 "BriefDescription": "% of DL1 reloads from Private L3, other core per Inst", 1715 "MetricExpr": "dl1_reload_from_l31_mod_rate_percent + dl1_reload_from_l31_shr_rate_percent", 1716 "MetricName": "dl1_reload_from_l31_rate_percent" 1717 }, 1718 { 1719 "BriefDescription": "% of DL1 dL1_Reloads from Local L4", 1720 "MetricExpr": "PM_DATA_FROM_LL4 * 100 / PM_L1_DCACHE_RELOAD_VALID", 1721 "MetricName": "dl1_reload_from_ll4_percent" 1722 }, 1723 { 1724 "BriefDescription": "% of DL1 Reloads from Local L4 per Inst", 1725 "MetricExpr": "PM_DATA_FROM_LL4 * 100 / PM_RUN_INST_CMPL", 1726 "MetricName": "dl1_reload_from_ll4_rate_percent" 1727 }, 1728 { 1729 "BriefDescription": "% of DL1 dL1_Reloads from Remote L4", 1730 "MetricExpr": "PM_DATA_FROM_RL4 * 100 / PM_L1_DCACHE_RELOAD_VALID", 1731 "MetricName": "dl1_reload_from_rl4_percent" 1732 }, 1733 { 1734 "BriefDescription": "% of DL1 Reloads from Remote Memory per Inst", 1735 "MetricExpr": "PM_DATA_FROM_RL4 * 100 / PM_RUN_INST_CMPL", 1736 "MetricName": "dl1_reload_from_rl4_rate_percent" 1737 }, 1738 { 1739 "BriefDescription": "Rate of DERAT reloads from L2", 1740 "MetricExpr": "PM_DPTEG_FROM_L2 * 100 / PM_RUN_INST_CMPL", 1741 "MetricName": "dpteg_from_l2_rate_percent" 1742 }, 1743 { 1744 "BriefDescription": "Rate of DERAT reloads from L3", 1745 "MetricExpr": "PM_DPTEG_FROM_L3 * 100 / PM_RUN_INST_CMPL", 1746 "MetricName": "dpteg_from_l3_rate_percent" 1747 }, 1748 { 1749 "BriefDescription": "Cycles in which the oldest instruction is finished and ready to complete for waiting to get through the completion pipe", 1750 "MetricExpr": "PM_NTC_ALL_FIN / PM_RUN_INST_CMPL", 1751 "MetricName": "finish_to_cmpl_cpi" 1752 }, 1753 { 1754 "BriefDescription": "Total Fixed point operations", 1755 "MetricExpr": "PM_FXU_FIN/PM_RUN_INST_CMPL", 1756 "MetricName": "fixed_per_inst" 1757 }, 1758 { 1759 "BriefDescription": "All FXU Busy", 1760 "MetricExpr": "PM_FXU_BUSY / PM_CYC", 1761 "MetricName": "fxu_all_busy" 1762 }, 1763 { 1764 "BriefDescription": "All FXU Idle", 1765 "MetricExpr": "PM_FXU_IDLE / PM_CYC", 1766 "MetricName": "fxu_all_idle" 1767 }, 1768 { 1769 "BriefDescription": "Rate of IERAT reloads from L2", 1770 "MetricExpr": "PM_IPTEG_FROM_L2 * 100 / PM_RUN_INST_CMPL", 1771 "MetricName": "ipteg_from_l2_rate_percent" 1772 }, 1773 { 1774 "BriefDescription": "Rate of IERAT reloads from L3", 1775 "MetricExpr": "PM_IPTEG_FROM_L3 * 100 / PM_RUN_INST_CMPL", 1776 "MetricName": "ipteg_from_l3_rate_percent" 1777 }, 1778 { 1779 "BriefDescription": "Rate of IERAT reloads from local memory", 1780 "MetricExpr": "PM_IPTEG_FROM_LL4 * 100 / PM_RUN_INST_CMPL", 1781 "MetricName": "ipteg_from_ll4_rate_percent" 1782 }, 1783 { 1784 "BriefDescription": "Rate of IERAT reloads from local memory", 1785 "MetricExpr": "PM_IPTEG_FROM_LMEM * 100 / PM_RUN_INST_CMPL", 1786 "MetricName": "ipteg_from_lmem_rate_percent" 1787 }, 1788 { 1789 "BriefDescription": "Average number of Castout machines used. 1 of 16 CO machines is sampled every L2 cycle", 1790 "MetricExpr": "PM_CO_USAGE / PM_RUN_CYC * 16", 1791 "MetricName": "l2_co_usage" 1792 }, 1793 { 1794 "BriefDescription": "Percent of instruction reads out of all L2 commands", 1795 "MetricExpr": "PM_ISIDE_DISP * 100 / (PM_L2_ST + PM_L2_LD + PM_ISIDE_DISP)", 1796 "MetricName": "l2_instr_commands_percent" 1797 }, 1798 { 1799 "BriefDescription": "Percent of loads out of all L2 commands", 1800 "MetricExpr": "PM_L2_LD * 100 / (PM_L2_ST + PM_L2_LD + PM_ISIDE_DISP)", 1801 "MetricName": "l2_ld_commands_percent" 1802 }, 1803 { 1804 "BriefDescription": "Rate of L2 store dispatches that failed per core", 1805 "MetricExpr": "100 * (PM_L2_RCST_DISP_FAIL_ADDR + PM_L2_RCST_DISP_FAIL_OTHER)/2 / PM_RUN_INST_CMPL", 1806 "MetricName": "l2_rc_st_disp_fail_rate_percent" 1807 }, 1808 { 1809 "BriefDescription": "Average number of Read/Claim machines used. 1 of 16 RC machines is sampled every L2 cycle", 1810 "MetricExpr": "PM_RC_USAGE / PM_RUN_CYC * 16", 1811 "MetricName": "l2_rc_usage" 1812 }, 1813 { 1814 "BriefDescription": "Average number of Snoop machines used. 1 of 8 SN machines is sampled every L2 cycle", 1815 "MetricExpr": "PM_SN_USAGE / PM_RUN_CYC * 8", 1816 "MetricName": "l2_sn_usage" 1817 }, 1818 { 1819 "BriefDescription": "Percent of stores out of all L2 commands", 1820 "MetricExpr": "PM_L2_ST * 100 / (PM_L2_ST + PM_L2_LD + PM_ISIDE_DISP)", 1821 "MetricName": "l2_st_commands_percent" 1822 }, 1823 { 1824 "BriefDescription": "Rate of L2 store dispatches that failed per core", 1825 "MetricExpr": "100 * (PM_L2_RCST_DISP_FAIL_ADDR + PM_L2_RCST_DISP_FAIL_OTHER)/2 / PM_RUN_INST_CMPL", 1826 "MetricName": "l2_st_disp_fail_rate_percent" 1827 }, 1828 { 1829 "BriefDescription": "Rate of L2 dispatches per core", 1830 "MetricExpr": "100 * PM_L2_RCST_DISP/2 / PM_RUN_INST_CMPL", 1831 "MetricName": "l2_st_disp_rate_percent" 1832 }, 1833 { 1834 "BriefDescription": "Marked L31 Load latency", 1835 "MetricExpr": "(PM_MRK_DATA_FROM_L31_SHR_CYC + PM_MRK_DATA_FROM_L31_MOD_CYC) / (PM_MRK_DATA_FROM_L31_SHR + PM_MRK_DATA_FROM_L31_MOD)", 1836 "MetricName": "l31_latency" 1837 }, 1838 { 1839 "BriefDescription": "PCT instruction loads", 1840 "MetricExpr": "PM_LD_REF_L1 / PM_RUN_INST_CMPL", 1841 "MetricName": "loads_per_inst" 1842 }, 1843 { 1844 "BriefDescription": "Cycles stalled by D-Cache Misses", 1845 "MetricExpr": "PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL", 1846 "MetricName": "lsu_stall_dcache_miss_cpi" 1847 }, 1848 { 1849 "BriefDescription": "Completion stall because a different thread was using the completion pipe", 1850 "MetricExpr": "thread_block_stall_cpi - exception_stall_cpi - any_sync_stall_cpi - sync_pmu_int_stall_cpi - spec_finish_stall_cpi - flush_any_thread_stall_cpi - lsu_flush_next_stall_cpi - nested_tbegin_stall_cpi - nested_tend_stall_cpi - mtfpscr_stall_cpi", 1851 "MetricName": "other_thread_cmpl_stall" 1852 }, 1853 { 1854 "BriefDescription": "PCT instruction stores", 1855 "MetricExpr": "PM_ST_FIN / PM_RUN_INST_CMPL", 1856 "MetricName": "stores_per_inst" 1857 }, 1858 { 1859 "BriefDescription": "ANY_SYNC_STALL_CPI", 1860 "MetricExpr": "PM_CMPLU_STALL_SYNC_PMU_INT / PM_RUN_INST_CMPL", 1861 "MetricName": "sync_pmu_int_stall_cpi" 1862 } 1863] 1864