powerpc/power10/memory.json

[
  {
    "EventCode": "0x1C040",
    "EventName": "PM_XFER_FROM_SRC_PMC1",
    "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
  },
  {
    "EventCode": "0x1C056",
    "EventName": "PM_DERAT_MISS_4K",
    "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
  },
  {
    "EventCode": "0x1C058",
    "EventName": "PM_DTLB_MISS_16G",
    "BriefDescription": "Data TLB reload (after a miss) page size 16G. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
  },
  {
    "EventCode": "0x1C05C",
    "EventName": "PM_DTLB_MISS_2M",
    "BriefDescription": "Data TLB reload (after a miss) page size 2M. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
  },
  {
    "EventCode": "0x10062",
    "EventName": "PM_LD_L3MISS_PEND_CYC",
    "BriefDescription": "Cycles in which an L3 miss was pending for this thread."
  },
  {
    "EventCode": "0x2001A",
    "EventName": "PM_ITLB_HIT",
    "BriefDescription": "The PTE required to translate the instruction address was resident in the TLB (instruction TLB access/IERAT reload). Applies to both HPT and RPT. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches."
  },
  {
    "EventCode": "0x2003E",
    "EventName": "PM_PTESYNC_FIN",
    "BriefDescription": "Ptesync instruction finished in the store unit. Only one ptesync can finish at a time."
  },
  {
    "EventCode": "0x2C040",
    "EventName": "PM_XFER_FROM_SRC_PMC2",
    "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
  },
  {
    "EventCode": "0x2C054",
    "EventName": "PM_DERAT_MISS_64K",
    "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
  },
  {
    "EventCode": "0x2C056",
    "EventName": "PM_DTLB_MISS_4K",
    "BriefDescription": "Data TLB reload (after a miss) page size 4K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
  },
  {
    "EventCode": "0x2C05A",
    "EventName": "PM_DERAT_MISS_1G",
    "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 1G. Implies radix translation. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
  },
  {
    "EventCode": "0x200F6",
    "EventName": "PM_DERAT_MISS",
    "BriefDescription": "DERAT Reloaded to satisfy a DERAT miss. All page sizes are counted by this event. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
  },
  {
    "EventCode": "0x34044",
    "EventName": "PM_DERAT_MISS_PREF",
    "BriefDescription": "DERAT miss (TLB access) while servicing a data prefetch."
  },
  {
    "EventCode": "0x3C040",
    "EventName": "PM_XFER_FROM_SRC_PMC3",
    "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
  },
  {
    "EventCode": "0x3F04A",
    "EventName": "PM_LSU_ST5_FIN",
    "BriefDescription": "LSU Finished an internal operation in ST2 port."
  },
  {
    "EventCode": "0x3C054",
    "EventName": "PM_DERAT_MISS_16M",
    "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
  },
  {
    "EventCode": "0x3C056",
    "EventName": "PM_DTLB_MISS_64K",
    "BriefDescription": "Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
  },
  {
    "EventCode": "0x3C058",
    "EventName": "PM_LARX_FIN",
    "BriefDescription": "Load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock."
  },
  {
    "EventCode": "0x300FC",
    "EventName": "PM_DTLB_MISS",
    "BriefDescription": "The DPTEG required for the load/store instruction in execution was missing from the TLB. This event only counts for demand misses."
  },
  {
    "EventCode": "0x4003E",
    "EventName": "PM_LD_CMPL",
    "BriefDescription": "Load instruction completed."
  },
  {
    "EventCode": "0x4C040",
    "EventName": "PM_XFER_FROM_SRC_PMC4",
    "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
  },
  {
    "EventCode": "0x4C056",
    "EventName": "PM_DTLB_MISS_16M",
    "BriefDescription": "Data TLB reload (after a miss) page size 16M. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
  },
  {
    "EventCode": "0x4C05A",
    "EventName": "PM_DTLB_MISS_1G",
    "BriefDescription": "Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
  },
  {
    "EventCode": "0x000000F880",
    "EventName": "PM_SNOOP_TLBIE_CYC",
    "BriefDescription": "Cycles in which TLBIE snoops are executed in the LSU."
  },
  {
    "EventCode": "0x000000F084",
    "EventName": "PM_SNOOP_TLBIE_CACHE_WALK_CYC",
    "BriefDescription": "TLBIE snoop cycles in which the data cache is being walked."
  },
  {
    "EventCode": "0x000000F884",
    "EventName": "PM_SNOOP_TLBIE_WAIT_ST_CYC",
    "BriefDescription": "TLBIE snoop cycles in which older stores are still draining."
  },
  {
    "EventCode": "0x000000F088",
    "EventName": "PM_SNOOP_TLBIE_WAIT_LD_CYC",
    "BriefDescription": "TLBIE snoop cycles in which older loads are still draining."
  },
  {
    "EventCode": "0x000000F08C",
    "EventName": "PM_SNOOP_TLBIE_WAIT_MMU_CYC",
    "BriefDescription": "TLBIE snoop cycles in which the Load-Store unit is waiting for the MMU to finish invalidation."
  }
]