1[ 2 { 3 "ArchStdEvent": "L1I_CACHE_REFILL", 4 "PublicDescription": "Counts cache line refills in the level 1 instruction cache caused by a missed instruction fetch. Instruction fetches may include accessing multiple instructions, but the single cache line allocation is counted once." 5 }, 6 { 7 "ArchStdEvent": "L1I_CACHE", 8 "PublicDescription": "Counts instruction fetches which access the level 1 instruction cache. Instruction cache accesses caused by cache maintenance operations are not counted." 9 }, 10 { 11 "ArchStdEvent": "L1I_CACHE_LMISS", 12 "PublicDescription": "Counts cache line refills into the level 1 instruction cache, that incurred additional latency." 13 } 14] 15