xref: /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json (revision 34dc1baba215b826e454b8d19e4f24adbeb7d00d) 
1[
2    {
3        "ArchStdEvent": "L3D_CACHE_ALLOCATE",
4        "PublicDescription": "Counts level 3 cache line allocates that do not fetch data from outside the level 3 data or unified cache. For example, allocates due to streaming stores."
5    },
6    {
7        "ArchStdEvent": "L3D_CACHE_REFILL",
8        "PublicDescription": "Counts level 3 accesses that receive data from outside the L3 cache."
9    },
10    {
11        "ArchStdEvent": "L3D_CACHE",
12        "PublicDescription": "Counts level 3 cache accesses. level 3 cache is a unified cache for data and instruction accesses. Accesses are for misses in the lower level caches or translation resolutions due to accesses."
13    },
14    {
15        "ArchStdEvent": "L3D_CACHE_RD",
16        "PublicDescription": "TBD"
17    },
18    {
19        "ArchStdEvent": "L3D_CACHE_LMISS_RD",
20        "PublicDescription": "Counts any cache line refill into the level 3 cache from memory read operations that incurred additional latency."
21    }
22]
23