1[ 2 { 3 "ArchStdEvent": "LD_RETIRED" 4 }, 5 { 6 "ArchStdEvent": "MEM_ACCESS_RD" 7 }, 8 { 9 "ArchStdEvent": "MEM_ACCESS_WR" 10 }, 11 { 12 "ArchStdEvent": "LD_ALIGN_LAT" 13 }, 14 { 15 "ArchStdEvent": "ST_ALIGN_LAT" 16 }, 17 { 18 "ArchStdEvent": "MEM_ACCESS" 19 }, 20 { 21 "ArchStdEvent": "MEMORY_ERROR" 22 }, 23 { 24 "ArchStdEvent": "LDST_ALIGN_LAT" 25 }, 26 { 27 "ArchStdEvent": "MEM_ACCESS_CHECKED" 28 }, 29 { 30 "ArchStdEvent": "MEM_ACCESS_CHECKED_RD" 31 }, 32 { 33 "ArchStdEvent": "MEM_ACCESS_CHECKED_WR" 34 }, 35 { 36 "PublicDescription": "Flushes due to memory hazards", 37 "EventCode": "0x121", 38 "EventName": "BPU_FLUSH_MEM_FAULT", 39 "BriefDescription": "Flushes due to memory hazards" 40 } 41] 42