1[ 2 { 3 "MetricName": "branch_miss_pred_rate", 4 "MetricExpr": "BR_MIS_PRED / BR_PRED", 5 "BriefDescription": "Branch predictor misprediction rate. May not count branches that are never resolved because they are in the misprediction shadow of an earlier branch", 6 "MetricGroup": "branch", 7 "ScaleUnit": "100%" 8 }, 9 { 10 "MetricName": "bus_utilization", 11 "MetricExpr": "((BUS_ACCESS / (BUS_CYCLES * 1)) * 100)", 12 "BriefDescription": "Core-to-uncore bus utilization", 13 "MetricGroup": "Bus", 14 "ScaleUnit": "1percent of bus cycles" 15 }, 16 { 17 "MetricName": "l1d_cache_miss_ratio", 18 "MetricExpr": "(L1D_CACHE_REFILL / L1D_CACHE)", 19 "BriefDescription": "This metric measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gives an indication of the effectiveness of the level 1 data cache.", 20 "MetricGroup": "Miss_Ratio;L1D_Cache_Effectiveness", 21 "ScaleUnit": "1per cache access" 22 }, 23 { 24 "MetricName": "l1i_cache_miss_ratio", 25 "MetricExpr": "(L1I_CACHE_REFILL / L1I_CACHE)", 26 "BriefDescription": "This metric measures the ratio of level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesses. This gives an indication of the effectiveness of the level 1 instruction cache.", 27 "MetricGroup": "Miss_Ratio;L1I_Cache_Effectiveness", 28 "ScaleUnit": "1per cache access" 29 }, 30 { 31 "MetricName": "Miss_Ratio;l1d_cache_read_miss", 32 "MetricExpr": "L1D_CACHE_LMISS_RD / L1D_CACHE_RD", 33 "BriefDescription": "L1D cache read miss rate", 34 "MetricGroup": "Cache", 35 "ScaleUnit": "1per cache read access" 36 }, 37 { 38 "MetricName": "l2_cache_miss_ratio", 39 "MetricExpr": "(L2D_CACHE_REFILL / L2D_CACHE)", 40 "BriefDescription": "This metric measures the ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This gives an indication of the effectiveness of the level 2 cache, which is a unified cache that stores both data and instruction. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.", 41 "MetricGroup": "Miss_Ratio;L2_Cache_Effectiveness", 42 "ScaleUnit": "1per cache access" 43 }, 44 { 45 "MetricName": "l1i_cache_read_miss_rate", 46 "MetricExpr": "L1I_CACHE_LMISS / L1I_CACHE", 47 "BriefDescription": "L1I cache read miss rate", 48 "MetricGroup": "Cache", 49 "ScaleUnit": "1per cache access" 50 }, 51 { 52 "MetricName": "l2d_cache_read_miss_rate", 53 "MetricExpr": "L2D_CACHE_LMISS_RD / L2D_CACHE_RD", 54 "BriefDescription": "L2 cache read miss rate", 55 "MetricGroup": "Cache", 56 "ScaleUnit": "1per cache read access" 57 }, 58 { 59 "MetricName": "l1d_cache_miss_mpki", 60 "MetricExpr": "(L1D_CACHE_LMISS_RD * 1e3) / INST_RETIRED", 61 "BriefDescription": "Misses per thousand instructions (data)", 62 "MetricGroup": "Cache", 63 "ScaleUnit": "1MPKI" 64 }, 65 { 66 "MetricName": "l1i_cache_miss_mpki", 67 "MetricExpr": "(L1I_CACHE_LMISS * 1e3) / INST_RETIRED", 68 "BriefDescription": "Misses per thousand instructions (instruction)", 69 "MetricGroup": "Cache", 70 "ScaleUnit": "1MPKI" 71 }, 72 { 73 "MetricName": "simd_percentage", 74 "MetricExpr": "((ASE_SPEC / INST_SPEC) * 100)", 75 "BriefDescription": "This metric measures advanced SIMD operations as a percentage of total operations speculatively executed.", 76 "MetricGroup": "Operation_Mix", 77 "ScaleUnit": "1percent of operations" 78 }, 79 { 80 "MetricName": "crypto_percentage", 81 "MetricExpr": "((CRYPTO_SPEC / INST_SPEC) * 100)", 82 "BriefDescription": "This metric measures crypto operations as a percentage of operations speculatively executed.", 83 "MetricGroup": "Operation_Mix", 84 "ScaleUnit": "1percent of operations" 85 }, 86 { 87 "MetricName": "gflops", 88 "MetricExpr": "VFP_SPEC / (duration_time * 1e9)", 89 "BriefDescription": "Giga-floating point operations per second", 90 "MetricGroup": "InstructionMix" 91 }, 92 { 93 "MetricName": "integer_dp_percentage", 94 "MetricExpr": "((DP_SPEC / INST_SPEC) * 100)", 95 "BriefDescription": "This metric measures scalar integer operations as a percentage of operations speculatively executed.", 96 "MetricGroup": "Operation_Mix", 97 "ScaleUnit": "1percent of operations" 98 }, 99 { 100 "MetricName": "ipc", 101 "MetricExpr": "(INST_RETIRED / CPU_CYCLES)", 102 "BriefDescription": "This metric measures the number of instructions retired per cycle.", 103 "MetricGroup": "General", 104 "ScaleUnit": "1per cycle" 105 }, 106 { 107 "MetricName": "load_percentage", 108 "MetricExpr": "((LD_SPEC / INST_SPEC) * 100)", 109 "BriefDescription": "This metric measures load operations as a percentage of operations speculatively executed.", 110 "MetricGroup": "Operation_Mix", 111 "ScaleUnit": "1percent of operations" 112 }, 113 { 114 "MetricName": "load_store_spec_rate", 115 "MetricExpr": "((LDST_SPEC / INST_SPEC) * 100)", 116 "BriefDescription": "The rate of load or store instructions speculatively executed to overall instructions speclatively executed", 117 "MetricGroup": "Operation_Mix", 118 "ScaleUnit": "1percent of operations" 119 }, 120 { 121 "MetricName": "retired_mips", 122 "MetricExpr": "INST_RETIRED / (duration_time * 1e6)", 123 "BriefDescription": "Millions of instructions per second", 124 "MetricGroup": "InstructionMix" 125 }, 126 { 127 "MetricName": "spec_utilization_mips", 128 "MetricExpr": "INST_SPEC / (duration_time * 1e6)", 129 "BriefDescription": "Millions of instructions per second", 130 "MetricGroup": "PEutilization" 131 }, 132 { 133 "MetricName": "pc_write_spec_rate", 134 "MetricExpr": "((PC_WRITE_SPEC / INST_SPEC) * 100)", 135 "BriefDescription": "The rate of software change of the PC speculatively executed to overall instructions speclatively executed", 136 "MetricGroup": "Operation_Mix", 137 "ScaleUnit": "1percent of operations" 138 }, 139 { 140 "MetricName": "store_percentage", 141 "MetricExpr": "((ST_SPEC / INST_SPEC) * 100)", 142 "BriefDescription": "This metric measures store operations as a percentage of operations speculatively executed.", 143 "MetricGroup": "Operation_Mix", 144 "ScaleUnit": "1percent of operations" 145 }, 146 { 147 "MetricName": "scalar_fp_percentage", 148 "MetricExpr": "((VFP_SPEC / INST_SPEC) * 100)", 149 "BriefDescription": "This metric measures scalar floating point operations as a percentage of operations speculatively executed.", 150 "MetricGroup": "Operation_Mix", 151 "ScaleUnit": "1percent of operations" 152 }, 153 { 154 "MetricName": "retired_rate", 155 "MetricExpr": "OP_RETIRED / OP_SPEC", 156 "BriefDescription": "Of all the micro-operations issued, what percentage are retired(committed)", 157 "MetricGroup": "General", 158 "ScaleUnit": "100%" 159 }, 160 { 161 "MetricName": "wasted", 162 "MetricExpr": "1 - (OP_RETIRED / (CPU_CYCLES * #slots))", 163 "BriefDescription": "Of all the micro-operations issued, what proportion are lost", 164 "MetricGroup": "General", 165 "ScaleUnit": "100%" 166 }, 167 { 168 "MetricName": "wasted_rate", 169 "MetricExpr": "1 - OP_RETIRED / OP_SPEC", 170 "BriefDescription": "Of all the micro-operations issued, what percentage are not retired(committed)", 171 "MetricGroup": "General", 172 "ScaleUnit": "100%" 173 }, 174 { 175 "MetricName": "stall_backend_cache_rate", 176 "MetricExpr": "((STALL_BACKEND_CACHE / CPU_CYCLES) * 100)", 177 "BriefDescription": "Proportion of cycles stalled and no operations issued to backend and cache miss", 178 "MetricGroup": "Stall", 179 "ScaleUnit": "1percent of cycles" 180 }, 181 { 182 "MetricName": "stall_backend_resource_rate", 183 "MetricExpr": "((STALL_BACKEND_RESOURCE / CPU_CYCLES) * 100)", 184 "BriefDescription": "Proportion of cycles stalled and no operations issued to backend and resource full", 185 "MetricGroup": "Stall", 186 "ScaleUnit": "1percent of cycles" 187 }, 188 { 189 "MetricName": "stall_backend_tlb_rate", 190 "MetricExpr": "((STALL_BACKEND_TLB / CPU_CYCLES) * 100)", 191 "BriefDescription": "Proportion of cycles stalled and no operations issued to backend and TLB miss", 192 "MetricGroup": "Stall", 193 "ScaleUnit": "1percent of cycles" 194 }, 195 { 196 "MetricName": "stall_frontend_cache_rate", 197 "MetricExpr": "((STALL_FRONTEND_CACHE / CPU_CYCLES) * 100)", 198 "BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and cache miss", 199 "MetricGroup": "Stall", 200 "ScaleUnit": "1percent of cycles" 201 }, 202 { 203 "MetricName": "stall_frontend_tlb_rate", 204 "MetricExpr": "((STALL_FRONTEND_TLB / CPU_CYCLES) * 100)", 205 "BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and TLB miss", 206 "MetricGroup": "Stall", 207 "ScaleUnit": "1percent of cycles" 208 }, 209 { 210 "MetricName": "dtlb_walk_ratio", 211 "MetricExpr": "(DTLB_WALK / L1D_TLB)", 212 "BriefDescription": "This metric measures the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication of the effectiveness of the data TLB accesses.", 213 "MetricGroup": "Miss_Ratio;DTLB_Effectiveness", 214 "ScaleUnit": "1per TLB access" 215 }, 216 { 217 "MetricName": "itlb_walk_ratio", 218 "MetricExpr": "(ITLB_WALK / L1I_TLB)", 219 "BriefDescription": "This metric measures the ratio of instruction TLB Walks to the total number of instruction TLB accesses. This gives an indication of the effectiveness of the instruction TLB accesses.", 220 "MetricGroup": "Miss_Ratio;ITLB_Effectiveness", 221 "ScaleUnit": "1per TLB access" 222 }, 223 { 224 "ArchStdEvent": "backend_bound" 225 }, 226 { 227 "ArchStdEvent": "frontend_bound", 228 "MetricExpr": "100 - (retired_fraction + slots_lost_misspeculation_fraction + backend_bound)" 229 }, 230 { 231 "MetricName": "slots_lost_misspeculation_fraction", 232 "MetricExpr": "100 * ((OP_SPEC - OP_RETIRED) / (CPU_CYCLES * #slots))", 233 "BriefDescription": "Fraction of slots lost due to misspeculation", 234 "DefaultMetricgroupName": "TopdownL1", 235 "MetricGroup": "Default;TopdownL1", 236 "ScaleUnit": "1percent of slots" 237 }, 238 { 239 "MetricName": "retired_fraction", 240 "MetricExpr": "100 * (OP_RETIRED / (CPU_CYCLES * #slots))", 241 "BriefDescription": "Fraction of slots retiring, useful work", 242 "DefaultMetricgroupName": "TopdownL1", 243 "MetricGroup": "Default;TopdownL1", 244 "ScaleUnit": "1percent of slots" 245 }, 246 { 247 "MetricName": "backend_core", 248 "MetricExpr": "(backend_bound / 100) - backend_memory", 249 "BriefDescription": "Fraction of slots the CPU was stalled due to backend non-memory subsystem issues", 250 "MetricGroup": "TopdownL2", 251 "ScaleUnit": "100%" 252 }, 253 { 254 "MetricName": "backend_memory", 255 "MetricExpr": "(STALL_BACKEND_TLB + STALL_BACKEND_CACHE) / CPU_CYCLES", 256 "BriefDescription": "Fraction of slots the CPU was stalled due to backend memory subsystem issues (cache/tlb miss)", 257 "MetricGroup": "TopdownL2", 258 "ScaleUnit": "100%" 259 }, 260 { 261 "MetricName": "branch_mispredict", 262 "MetricExpr": "(BR_MIS_PRED_RETIRED / GPC_FLUSH) * slots_lost_misspeculation_fraction", 263 "BriefDescription": "Fraction of slots lost due to branch misprediciton", 264 "MetricGroup": "TopdownL2", 265 "ScaleUnit": "1percent of slots" 266 }, 267 { 268 "MetricName": "frontend_bandwidth", 269 "MetricExpr": "frontend_bound - frontend_latency", 270 "BriefDescription": "Fraction of slots the CPU did not dispatch at full bandwidth - able to dispatch partial slots only (1, 2, or 3 uops)", 271 "MetricGroup": "TopdownL2", 272 "ScaleUnit": "1percent of slots" 273 }, 274 { 275 "MetricName": "frontend_latency", 276 "MetricExpr": "((STALL_FRONTEND - ((STALL_SLOT_FRONTEND - ((frontend_bound / 100) * CPU_CYCLES * #slots)) / #slots)) / CPU_CYCLES) * 100", 277 "BriefDescription": "Fraction of slots the CPU was stalled due to frontend latency issues (cache/tlb miss); nothing to dispatch", 278 "MetricGroup": "TopdownL2", 279 "ScaleUnit": "1percent of slots" 280 }, 281 { 282 "MetricName": "other_miss_pred", 283 "MetricExpr": "slots_lost_misspeculation_fraction - branch_mispredict", 284 "BriefDescription": "Fraction of slots lost due to other/non-branch misprediction misspeculation", 285 "MetricGroup": "TopdownL2", 286 "ScaleUnit": "1percent of slots" 287 }, 288 { 289 "MetricName": "pipe_utilization", 290 "MetricExpr": "100 * ((IXU_NUM_UOPS_ISSUED + FSU_ISSUED) / (CPU_CYCLES * 6))", 291 "BriefDescription": "Fraction of execute slots utilized", 292 "MetricGroup": "TopdownL2", 293 "ScaleUnit": "1percent of slots" 294 }, 295 { 296 "MetricName": "d_cache_l2_miss_rate", 297 "MetricExpr": "((STALL_BACKEND_MEM / CPU_CYCLES) * 100)", 298 "BriefDescription": "Fraction of cycles the CPU was stalled due to data L2 cache miss", 299 "MetricGroup": "TopdownL3", 300 "ScaleUnit": "1percent of cycles" 301 }, 302 { 303 "MetricName": "d_cache_miss_rate", 304 "MetricExpr": "((STALL_BACKEND_CACHE / CPU_CYCLES) * 100)", 305 "BriefDescription": "Fraction of cycles the CPU was stalled due to data cache miss", 306 "MetricGroup": "TopdownL3", 307 "ScaleUnit": "1percent of cycles" 308 }, 309 { 310 "MetricName": "d_tlb_miss_rate", 311 "MetricExpr": "((STALL_BACKEND_TLB / CPU_CYCLES) * 100)", 312 "BriefDescription": "Fraction of cycles the CPU was stalled due to data TLB miss", 313 "MetricGroup": "TopdownL3", 314 "ScaleUnit": "1percent of cycles" 315 }, 316 { 317 "MetricName": "fsu_pipe_utilization", 318 "MetricExpr": "((FSU_ISSUED / (CPU_CYCLES * 2)) * 100)", 319 "BriefDescription": "Fraction of FSU execute slots utilized", 320 "MetricGroup": "TopdownL3", 321 "ScaleUnit": "1percent of slots" 322 }, 323 { 324 "MetricName": "i_cache_miss_rate", 325 "MetricExpr": "((STALL_FRONTEND_CACHE / CPU_CYCLES) * 100)", 326 "BriefDescription": "Fraction of cycles the CPU was stalled due to instruction cache miss", 327 "MetricGroup": "TopdownL3", 328 "ScaleUnit": "1percent of slots" 329 }, 330 { 331 "MetricName": "i_tlb_miss_rate", 332 "MetricExpr": "((STALL_FRONTEND_TLB / CPU_CYCLES) * 100)", 333 "BriefDescription": "Fraction of cycles the CPU was stalled due to instruction TLB miss", 334 "MetricGroup": "TopdownL3", 335 "ScaleUnit": "1percent of slots" 336 }, 337 { 338 "MetricName": "ixu_pipe_utilization", 339 "MetricExpr": "((IXU_NUM_UOPS_ISSUED / (CPU_CYCLES * #slots)) * 100)", 340 "BriefDescription": "Fraction of IXU execute slots utilized", 341 "MetricGroup": "TopdownL3", 342 "ScaleUnit": "1percent of slots" 343 }, 344 { 345 "MetricName": "stall_recovery_rate", 346 "MetricExpr": "((IDR_STALL_FLUSH / CPU_CYCLES) * 100)", 347 "BriefDescription": "Fraction of cycles the CPU was stalled due to flush recovery", 348 "MetricGroup": "TopdownL3", 349 "ScaleUnit": "1percent of slots" 350 }, 351 { 352 "MetricName": "stall_fsu_sched_rate", 353 "MetricExpr": "((IDR_STALL_FSU_SCHED / CPU_CYCLES) * 100)", 354 "BriefDescription": "Fraction of cycles the CPU was stalled and FSU was full", 355 "MetricGroup": "TopdownL4", 356 "ScaleUnit": "1percent of cycles" 357 }, 358 { 359 "MetricName": "stall_ixu_sched_rate", 360 "MetricExpr": "((IDR_STALL_IXU_SCHED / CPU_CYCLES) * 100)", 361 "BriefDescription": "Fraction of cycles the CPU was stalled and IXU was full", 362 "MetricGroup": "TopdownL4", 363 "ScaleUnit": "1percent of cycles" 364 }, 365 { 366 "MetricName": "stall_lob_id_rate", 367 "MetricExpr": "((IDR_STALL_LOB_ID / CPU_CYCLES) * 100)", 368 "BriefDescription": "Fraction of cycles the CPU was stalled and LOB was full", 369 "MetricGroup": "TopdownL4", 370 "ScaleUnit": "1percent of cycles" 371 }, 372 { 373 "MetricName": "stall_rob_id_rate", 374 "MetricExpr": "((IDR_STALL_ROB_ID / CPU_CYCLES) * 100)", 375 "BriefDescription": "Fraction of cycles the CPU was stalled and ROB was full", 376 "MetricGroup": "TopdownL4", 377 "ScaleUnit": "1percent of cycles" 378 }, 379 { 380 "MetricName": "stall_sob_id_rate", 381 "MetricExpr": "((IDR_STALL_SOB_ID / CPU_CYCLES) * 100)", 382 "BriefDescription": "Fraction of cycles the CPU was stalled and SOB was full", 383 "MetricGroup": "TopdownL4", 384 "ScaleUnit": "1percent of cycles" 385 } 386] 387