1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * x86 instruction nmemonic table to parse disasm lines for annotate. 4 * This table is searched twice - one for exact match and another for 5 * match without a size suffix (b, w, l, q) in case of AT&T syntax. 6 * 7 * So this table should not have entries with the suffix unless it's 8 * a complete different instruction than ones without the suffix. 9 */ 10 static struct ins x86__instructions[] = { 11 { .name = "adc", .ops = &mov_ops, }, 12 { .name = "add", .ops = &mov_ops, }, 13 { .name = "addsd", .ops = &mov_ops, }, 14 { .name = "and", .ops = &mov_ops, }, 15 { .name = "andpd", .ops = &mov_ops, }, 16 { .name = "andps", .ops = &mov_ops, }, 17 { .name = "bsr", .ops = &mov_ops, }, 18 { .name = "bt", .ops = &mov_ops, }, 19 { .name = "btr", .ops = &mov_ops, }, 20 { .name = "bts", .ops = &mov_ops, }, 21 { .name = "call", .ops = &call_ops, }, 22 { .name = "cmovbe", .ops = &mov_ops, }, 23 { .name = "cmove", .ops = &mov_ops, }, 24 { .name = "cmovae", .ops = &mov_ops, }, 25 { .name = "cmp", .ops = &mov_ops, }, 26 { .name = "cmpxch", .ops = &mov_ops, }, 27 { .name = "cmpxchg", .ops = &mov_ops, }, 28 { .name = "cs", .ops = &mov_ops, }, 29 { .name = "dec", .ops = &dec_ops, }, 30 { .name = "divsd", .ops = &mov_ops, }, 31 { .name = "divss", .ops = &mov_ops, }, 32 { .name = "gs", .ops = &mov_ops, }, 33 { .name = "imul", .ops = &mov_ops, }, 34 { .name = "inc", .ops = &dec_ops, }, 35 { .name = "ja", .ops = &jump_ops, }, 36 { .name = "jae", .ops = &jump_ops, }, 37 { .name = "jb", .ops = &jump_ops, }, 38 { .name = "jbe", .ops = &jump_ops, }, 39 { .name = "jc", .ops = &jump_ops, }, 40 { .name = "jcxz", .ops = &jump_ops, }, 41 { .name = "je", .ops = &jump_ops, }, 42 { .name = "jecxz", .ops = &jump_ops, }, 43 { .name = "jg", .ops = &jump_ops, }, 44 { .name = "jge", .ops = &jump_ops, }, 45 { .name = "jl", .ops = &jump_ops, }, 46 { .name = "jle", .ops = &jump_ops, }, 47 { .name = "jmp", .ops = &jump_ops, }, 48 { .name = "jna", .ops = &jump_ops, }, 49 { .name = "jnae", .ops = &jump_ops, }, 50 { .name = "jnb", .ops = &jump_ops, }, 51 { .name = "jnbe", .ops = &jump_ops, }, 52 { .name = "jnc", .ops = &jump_ops, }, 53 { .name = "jne", .ops = &jump_ops, }, 54 { .name = "jng", .ops = &jump_ops, }, 55 { .name = "jnge", .ops = &jump_ops, }, 56 { .name = "jnl", .ops = &jump_ops, }, 57 { .name = "jnle", .ops = &jump_ops, }, 58 { .name = "jno", .ops = &jump_ops, }, 59 { .name = "jnp", .ops = &jump_ops, }, 60 { .name = "jns", .ops = &jump_ops, }, 61 { .name = "jnz", .ops = &jump_ops, }, 62 { .name = "jo", .ops = &jump_ops, }, 63 { .name = "jp", .ops = &jump_ops, }, 64 { .name = "jpe", .ops = &jump_ops, }, 65 { .name = "jpo", .ops = &jump_ops, }, 66 { .name = "jrcxz", .ops = &jump_ops, }, 67 { .name = "js", .ops = &jump_ops, }, 68 { .name = "jz", .ops = &jump_ops, }, 69 { .name = "lea", .ops = &mov_ops, }, 70 { .name = "lock", .ops = &lock_ops, }, 71 { .name = "mov", .ops = &mov_ops, }, 72 { .name = "movapd", .ops = &mov_ops, }, 73 { .name = "movaps", .ops = &mov_ops, }, 74 { .name = "movdqa", .ops = &mov_ops, }, 75 { .name = "movdqu", .ops = &mov_ops, }, 76 { .name = "movsd", .ops = &mov_ops, }, 77 { .name = "movss", .ops = &mov_ops, }, 78 { .name = "movsb", .ops = &mov_ops, }, 79 { .name = "movsw", .ops = &mov_ops, }, 80 { .name = "movsl", .ops = &mov_ops, }, 81 { .name = "movupd", .ops = &mov_ops, }, 82 { .name = "movups", .ops = &mov_ops, }, 83 { .name = "movzb", .ops = &mov_ops, }, 84 { .name = "movzw", .ops = &mov_ops, }, 85 { .name = "movzl", .ops = &mov_ops, }, 86 { .name = "mulsd", .ops = &mov_ops, }, 87 { .name = "mulss", .ops = &mov_ops, }, 88 { .name = "nop", .ops = &nop_ops, }, 89 { .name = "or", .ops = &mov_ops, }, 90 { .name = "orps", .ops = &mov_ops, }, 91 { .name = "pand", .ops = &mov_ops, }, 92 { .name = "paddq", .ops = &mov_ops, }, 93 { .name = "pcmpeqb", .ops = &mov_ops, }, 94 { .name = "por", .ops = &mov_ops, }, 95 { .name = "rcl", .ops = &mov_ops, }, 96 { .name = "ret", .ops = &ret_ops, }, 97 { .name = "sbb", .ops = &mov_ops, }, 98 { .name = "sete", .ops = &mov_ops, }, 99 { .name = "sub", .ops = &mov_ops, }, 100 { .name = "subsd", .ops = &mov_ops, }, 101 { .name = "test", .ops = &mov_ops, }, 102 { .name = "tzcnt", .ops = &mov_ops, }, 103 { .name = "ucomisd", .ops = &mov_ops, }, 104 { .name = "ucomiss", .ops = &mov_ops, }, 105 { .name = "vaddsd", .ops = &mov_ops, }, 106 { .name = "vandpd", .ops = &mov_ops, }, 107 { .name = "vmovdqa", .ops = &mov_ops, }, 108 { .name = "vmovq", .ops = &mov_ops, }, 109 { .name = "vmovsd", .ops = &mov_ops, }, 110 { .name = "vmulsd", .ops = &mov_ops, }, 111 { .name = "vorpd", .ops = &mov_ops, }, 112 { .name = "vsubsd", .ops = &mov_ops, }, 113 { .name = "vucomisd", .ops = &mov_ops, }, 114 { .name = "xadd", .ops = &mov_ops, }, 115 { .name = "xbegin", .ops = &jump_ops, }, 116 { .name = "xchg", .ops = &mov_ops, }, 117 { .name = "xor", .ops = &mov_ops, }, 118 { .name = "xorpd", .ops = &mov_ops, }, 119 { .name = "xorps", .ops = &mov_ops, }, 120 }; 121 122 static bool amd__ins_is_fused(struct arch *arch, const char *ins1, 123 const char *ins2) 124 { 125 if (strstr(ins2, "jmp")) 126 return false; 127 128 /* Family >= 15h supports cmp/test + branch fusion */ 129 if (arch->family >= 0x15 && (strstarts(ins1, "test") || 130 (strstarts(ins1, "cmp") && !strstr(ins1, "xchg")))) { 131 return true; 132 } 133 134 /* Family >= 19h supports some ALU + branch fusion */ 135 if (arch->family >= 0x19 && (strstarts(ins1, "add") || 136 strstarts(ins1, "sub") || strstarts(ins1, "and") || 137 strstarts(ins1, "inc") || strstarts(ins1, "dec") || 138 strstarts(ins1, "or") || strstarts(ins1, "xor"))) { 139 return true; 140 } 141 142 return false; 143 } 144 145 static bool intel__ins_is_fused(struct arch *arch, const char *ins1, 146 const char *ins2) 147 { 148 if (arch->family != 6 || arch->model < 0x1e || strstr(ins2, "jmp")) 149 return false; 150 151 if (arch->model == 0x1e) { 152 /* Nehalem */ 153 if ((strstr(ins1, "cmp") && !strstr(ins1, "xchg")) || 154 strstr(ins1, "test")) { 155 return true; 156 } 157 } else { 158 /* Newer platform */ 159 if ((strstr(ins1, "cmp") && !strstr(ins1, "xchg")) || 160 strstr(ins1, "test") || 161 strstr(ins1, "add") || 162 strstr(ins1, "sub") || 163 strstr(ins1, "and") || 164 strstr(ins1, "inc") || 165 strstr(ins1, "dec")) { 166 return true; 167 } 168 } 169 170 return false; 171 } 172 173 static int x86__cpuid_parse(struct arch *arch, char *cpuid) 174 { 175 unsigned int family, model, stepping; 176 int ret; 177 178 /* 179 * cpuid = "GenuineIntel,family,model,stepping" 180 */ 181 ret = sscanf(cpuid, "%*[^,],%u,%u,%u", &family, &model, &stepping); 182 if (ret == 3) { 183 arch->family = family; 184 arch->model = model; 185 arch->ins_is_fused = strstarts(cpuid, "AuthenticAMD") ? 186 amd__ins_is_fused : 187 intel__ins_is_fused; 188 return 0; 189 } 190 191 return -1; 192 } 193 194 static int x86__annotate_init(struct arch *arch, char *cpuid) 195 { 196 int err = 0; 197 198 if (arch->initialized) 199 return 0; 200 201 if (cpuid) { 202 if (x86__cpuid_parse(arch, cpuid)) 203 err = SYMBOL_ANNOTATE_ERRNO__ARCH_INIT_CPUID_PARSING; 204 } 205 206 arch->initialized = true; 207 return err; 208 } 209 210 #ifdef HAVE_DWARF_SUPPORT 211 static void update_insn_state_x86(struct type_state *state, 212 struct data_loc_info *dloc, Dwarf_Die *cu_die, 213 struct disasm_line *dl) 214 { 215 struct annotated_insn_loc loc; 216 struct annotated_op_loc *src = &loc.ops[INSN_OP_SOURCE]; 217 struct annotated_op_loc *dst = &loc.ops[INSN_OP_TARGET]; 218 struct type_state_reg *tsr; 219 Dwarf_Die type_die; 220 u32 insn_offset = dl->al.offset; 221 int fbreg = dloc->fbreg; 222 int fboff = 0; 223 224 if (annotate_get_insn_location(dloc->arch, dl, &loc) < 0) 225 return; 226 227 if (ins__is_call(&dl->ins)) { 228 struct symbol *func = dl->ops.target.sym; 229 230 if (func == NULL) 231 return; 232 233 /* __fentry__ will preserve all registers */ 234 if (!strcmp(func->name, "__fentry__")) 235 return; 236 237 pr_debug_dtp("call [%x] %s\n", insn_offset, func->name); 238 239 /* Otherwise invalidate caller-saved registers after call */ 240 for (unsigned i = 0; i < ARRAY_SIZE(state->regs); i++) { 241 if (state->regs[i].caller_saved) 242 state->regs[i].ok = false; 243 } 244 245 /* Update register with the return type (if any) */ 246 if (die_find_func_rettype(cu_die, func->name, &type_die)) { 247 tsr = &state->regs[state->ret_reg]; 248 tsr->type = type_die; 249 tsr->kind = TSR_KIND_TYPE; 250 tsr->ok = true; 251 252 pr_debug_dtp("call [%x] return -> reg%d", 253 insn_offset, state->ret_reg); 254 pr_debug_type_name(&type_die, tsr->kind); 255 } 256 return; 257 } 258 259 if (!strncmp(dl->ins.name, "add", 3)) { 260 u64 imm_value = -1ULL; 261 int offset; 262 const char *var_name = NULL; 263 struct map_symbol *ms = dloc->ms; 264 u64 ip = ms->sym->start + dl->al.offset; 265 266 if (!has_reg_type(state, dst->reg1)) 267 return; 268 269 tsr = &state->regs[dst->reg1]; 270 271 if (src->imm) 272 imm_value = src->offset; 273 else if (has_reg_type(state, src->reg1) && 274 state->regs[src->reg1].kind == TSR_KIND_CONST) 275 imm_value = state->regs[src->reg1].imm_value; 276 else if (src->reg1 == DWARF_REG_PC) { 277 u64 var_addr = annotate_calc_pcrel(dloc->ms, ip, 278 src->offset, dl); 279 280 if (get_global_var_info(dloc, var_addr, 281 &var_name, &offset) && 282 !strcmp(var_name, "this_cpu_off") && 283 tsr->kind == TSR_KIND_CONST) { 284 tsr->kind = TSR_KIND_PERCPU_BASE; 285 imm_value = tsr->imm_value; 286 } 287 } 288 else 289 return; 290 291 if (tsr->kind != TSR_KIND_PERCPU_BASE) 292 return; 293 294 if (get_global_var_type(cu_die, dloc, ip, imm_value, &offset, 295 &type_die) && offset == 0) { 296 /* 297 * This is not a pointer type, but it should be treated 298 * as a pointer. 299 */ 300 tsr->type = type_die; 301 tsr->kind = TSR_KIND_POINTER; 302 tsr->ok = true; 303 304 pr_debug_dtp("add [%x] percpu %#"PRIx64" -> reg%d", 305 insn_offset, imm_value, dst->reg1); 306 pr_debug_type_name(&tsr->type, tsr->kind); 307 } 308 return; 309 } 310 311 if (strncmp(dl->ins.name, "mov", 3)) 312 return; 313 314 if (dloc->fb_cfa) { 315 u64 ip = dloc->ms->sym->start + dl->al.offset; 316 u64 pc = map__rip_2objdump(dloc->ms->map, ip); 317 318 if (die_get_cfa(dloc->di->dbg, pc, &fbreg, &fboff) < 0) 319 fbreg = -1; 320 } 321 322 /* Case 1. register to register or segment:offset to register transfers */ 323 if (!src->mem_ref && !dst->mem_ref) { 324 if (!has_reg_type(state, dst->reg1)) 325 return; 326 327 tsr = &state->regs[dst->reg1]; 328 if (dso__kernel(map__dso(dloc->ms->map)) && 329 src->segment == INSN_SEG_X86_GS && src->imm) { 330 u64 ip = dloc->ms->sym->start + dl->al.offset; 331 u64 var_addr; 332 int offset; 333 334 /* 335 * In kernel, %gs points to a per-cpu region for the 336 * current CPU. Access with a constant offset should 337 * be treated as a global variable access. 338 */ 339 var_addr = src->offset; 340 341 if (var_addr == 40) { 342 tsr->kind = TSR_KIND_CANARY; 343 tsr->ok = true; 344 345 pr_debug_dtp("mov [%x] stack canary -> reg%d\n", 346 insn_offset, dst->reg1); 347 return; 348 } 349 350 if (!get_global_var_type(cu_die, dloc, ip, var_addr, 351 &offset, &type_die) || 352 !die_get_member_type(&type_die, offset, &type_die)) { 353 tsr->ok = false; 354 return; 355 } 356 357 tsr->type = type_die; 358 tsr->kind = TSR_KIND_TYPE; 359 tsr->ok = true; 360 361 pr_debug_dtp("mov [%x] this-cpu addr=%#"PRIx64" -> reg%d", 362 insn_offset, var_addr, dst->reg1); 363 pr_debug_type_name(&tsr->type, tsr->kind); 364 return; 365 } 366 367 if (src->imm) { 368 tsr->kind = TSR_KIND_CONST; 369 tsr->imm_value = src->offset; 370 tsr->ok = true; 371 372 pr_debug_dtp("mov [%x] imm=%#x -> reg%d\n", 373 insn_offset, tsr->imm_value, dst->reg1); 374 return; 375 } 376 377 if (!has_reg_type(state, src->reg1) || 378 !state->regs[src->reg1].ok) { 379 tsr->ok = false; 380 return; 381 } 382 383 tsr->type = state->regs[src->reg1].type; 384 tsr->kind = state->regs[src->reg1].kind; 385 tsr->ok = true; 386 387 pr_debug_dtp("mov [%x] reg%d -> reg%d", 388 insn_offset, src->reg1, dst->reg1); 389 pr_debug_type_name(&tsr->type, tsr->kind); 390 } 391 /* Case 2. memory to register transers */ 392 if (src->mem_ref && !dst->mem_ref) { 393 int sreg = src->reg1; 394 395 if (!has_reg_type(state, dst->reg1)) 396 return; 397 398 tsr = &state->regs[dst->reg1]; 399 400 retry: 401 /* Check stack variables with offset */ 402 if (sreg == fbreg) { 403 struct type_state_stack *stack; 404 int offset = src->offset - fboff; 405 406 stack = find_stack_state(state, offset); 407 if (stack == NULL) { 408 tsr->ok = false; 409 return; 410 } else if (!stack->compound) { 411 tsr->type = stack->type; 412 tsr->kind = stack->kind; 413 tsr->ok = true; 414 } else if (die_get_member_type(&stack->type, 415 offset - stack->offset, 416 &type_die)) { 417 tsr->type = type_die; 418 tsr->kind = TSR_KIND_TYPE; 419 tsr->ok = true; 420 } else { 421 tsr->ok = false; 422 return; 423 } 424 425 pr_debug_dtp("mov [%x] -%#x(stack) -> reg%d", 426 insn_offset, -offset, dst->reg1); 427 pr_debug_type_name(&tsr->type, tsr->kind); 428 } 429 /* And then dereference the pointer if it has one */ 430 else if (has_reg_type(state, sreg) && state->regs[sreg].ok && 431 state->regs[sreg].kind == TSR_KIND_TYPE && 432 die_deref_ptr_type(&state->regs[sreg].type, 433 src->offset, &type_die)) { 434 tsr->type = type_die; 435 tsr->kind = TSR_KIND_TYPE; 436 tsr->ok = true; 437 438 pr_debug_dtp("mov [%x] %#x(reg%d) -> reg%d", 439 insn_offset, src->offset, sreg, dst->reg1); 440 pr_debug_type_name(&tsr->type, tsr->kind); 441 } 442 /* Or check if it's a global variable */ 443 else if (sreg == DWARF_REG_PC) { 444 struct map_symbol *ms = dloc->ms; 445 u64 ip = ms->sym->start + dl->al.offset; 446 u64 addr; 447 int offset; 448 449 addr = annotate_calc_pcrel(ms, ip, src->offset, dl); 450 451 if (!get_global_var_type(cu_die, dloc, ip, addr, &offset, 452 &type_die) || 453 !die_get_member_type(&type_die, offset, &type_die)) { 454 tsr->ok = false; 455 return; 456 } 457 458 tsr->type = type_die; 459 tsr->kind = TSR_KIND_TYPE; 460 tsr->ok = true; 461 462 pr_debug_dtp("mov [%x] global addr=%"PRIx64" -> reg%d", 463 insn_offset, addr, dst->reg1); 464 pr_debug_type_name(&type_die, tsr->kind); 465 } 466 /* And check percpu access with base register */ 467 else if (has_reg_type(state, sreg) && 468 state->regs[sreg].kind == TSR_KIND_PERCPU_BASE) { 469 u64 ip = dloc->ms->sym->start + dl->al.offset; 470 u64 var_addr = src->offset; 471 int offset; 472 473 if (src->multi_regs) { 474 int reg2 = (sreg == src->reg1) ? src->reg2 : src->reg1; 475 476 if (has_reg_type(state, reg2) && state->regs[reg2].ok && 477 state->regs[reg2].kind == TSR_KIND_CONST) 478 var_addr += state->regs[reg2].imm_value; 479 } 480 481 /* 482 * In kernel, %gs points to a per-cpu region for the 483 * current CPU. Access with a constant offset should 484 * be treated as a global variable access. 485 */ 486 if (get_global_var_type(cu_die, dloc, ip, var_addr, 487 &offset, &type_die) && 488 die_get_member_type(&type_die, offset, &type_die)) { 489 tsr->type = type_die; 490 tsr->kind = TSR_KIND_TYPE; 491 tsr->ok = true; 492 493 if (src->multi_regs) { 494 pr_debug_dtp("mov [%x] percpu %#x(reg%d,reg%d) -> reg%d", 495 insn_offset, src->offset, src->reg1, 496 src->reg2, dst->reg1); 497 } else { 498 pr_debug_dtp("mov [%x] percpu %#x(reg%d) -> reg%d", 499 insn_offset, src->offset, sreg, dst->reg1); 500 } 501 pr_debug_type_name(&tsr->type, tsr->kind); 502 } else { 503 tsr->ok = false; 504 } 505 } 506 /* And then dereference the calculated pointer if it has one */ 507 else if (has_reg_type(state, sreg) && state->regs[sreg].ok && 508 state->regs[sreg].kind == TSR_KIND_POINTER && 509 die_get_member_type(&state->regs[sreg].type, 510 src->offset, &type_die)) { 511 tsr->type = type_die; 512 tsr->kind = TSR_KIND_TYPE; 513 tsr->ok = true; 514 515 pr_debug_dtp("mov [%x] pointer %#x(reg%d) -> reg%d", 516 insn_offset, src->offset, sreg, dst->reg1); 517 pr_debug_type_name(&tsr->type, tsr->kind); 518 } 519 /* Or try another register if any */ 520 else if (src->multi_regs && sreg == src->reg1 && 521 src->reg1 != src->reg2) { 522 sreg = src->reg2; 523 goto retry; 524 } 525 else { 526 int offset; 527 const char *var_name = NULL; 528 529 /* it might be per-cpu variable (in kernel) access */ 530 if (src->offset < 0) { 531 if (get_global_var_info(dloc, (s64)src->offset, 532 &var_name, &offset) && 533 !strcmp(var_name, "__per_cpu_offset")) { 534 tsr->kind = TSR_KIND_PERCPU_BASE; 535 536 pr_debug_dtp("mov [%x] percpu base reg%d\n", 537 insn_offset, dst->reg1); 538 } 539 } 540 541 tsr->ok = false; 542 } 543 } 544 /* Case 3. register to memory transfers */ 545 if (!src->mem_ref && dst->mem_ref) { 546 if (!has_reg_type(state, src->reg1) || 547 !state->regs[src->reg1].ok) 548 return; 549 550 /* Check stack variables with offset */ 551 if (dst->reg1 == fbreg) { 552 struct type_state_stack *stack; 553 int offset = dst->offset - fboff; 554 555 tsr = &state->regs[src->reg1]; 556 557 stack = find_stack_state(state, offset); 558 if (stack) { 559 /* 560 * The source register is likely to hold a type 561 * of member if it's a compound type. Do not 562 * update the stack variable type since we can 563 * get the member type later by using the 564 * die_get_member_type(). 565 */ 566 if (!stack->compound) 567 set_stack_state(stack, offset, tsr->kind, 568 &tsr->type); 569 } else { 570 findnew_stack_state(state, offset, tsr->kind, 571 &tsr->type); 572 } 573 574 pr_debug_dtp("mov [%x] reg%d -> -%#x(stack)", 575 insn_offset, src->reg1, -offset); 576 pr_debug_type_name(&tsr->type, tsr->kind); 577 } 578 /* 579 * Ignore other transfers since it'd set a value in a struct 580 * and won't change the type. 581 */ 582 } 583 /* Case 4. memory to memory transfers (not handled for now) */ 584 } 585 #endif 586