1perf-list(1) 2============ 3 4NAME 5---- 6perf-list - List all symbolic event types 7 8SYNOPSIS 9-------- 10[verse] 11'perf list' [--no-desc] [--long-desc] 12 [hw|sw|cache|tracepoint|pmu|sdt|metric|metricgroup|event_glob] 13 14DESCRIPTION 15----------- 16This command displays the symbolic event types which can be selected in the 17various perf commands with the -e option. 18 19OPTIONS 20------- 21-d:: 22--desc:: 23Print extra event descriptions. (default) 24 25--no-desc:: 26Don't print descriptions. 27 28-v:: 29--long-desc:: 30Print longer event descriptions. 31 32--debug:: 33Enable debugging output. 34 35--details:: 36Print how named events are resolved internally into perf events, and also 37any extra expressions computed by perf stat. 38 39[[EVENT_MODIFIERS]] 40EVENT MODIFIERS 41--------------- 42 43Events can optionally have a modifier by appending a colon and one or 44more modifiers. Modifiers allow the user to restrict the events to be 45counted. The following modifiers exist: 46 47 u - user-space counting 48 k - kernel counting 49 h - hypervisor counting 50 I - non idle counting 51 G - guest counting (in KVM guests) 52 H - host counting (not in KVM guests) 53 p - precise level 54 P - use maximum detected precise level 55 S - read sample value (PERF_SAMPLE_READ) 56 D - pin the event to the PMU 57 W - group is weak and will fallback to non-group if not schedulable, 58 59The 'p' modifier can be used for specifying how precise the instruction 60address should be. The 'p' modifier can be specified multiple times: 61 62 0 - SAMPLE_IP can have arbitrary skid 63 1 - SAMPLE_IP must have constant skid 64 2 - SAMPLE_IP requested to have 0 skid 65 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid 66 sample shadowing effects. 67 68For Intel systems precise event sampling is implemented with PEBS 69which supports up to precise-level 2, and precise level 3 for 70some special cases 71 72On AMD systems it is implemented using IBS (up to precise-level 2). 73The precise modifier works with event types 0x76 (cpu-cycles, CPU 74clocks not halted) and 0xC1 (micro-ops retired). Both events map to 75IBS execution sampling (IBS op) with the IBS Op Counter Control bit 76(IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s 77Manual Volume 2: System Programming, 13.3 Instruction-Based 78Sampling). Examples to use IBS: 79 80 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles 81 perf record -a -e r076:p ... # same as -e cpu-cycles:p 82 perf record -a -e r0C1:p ... # use ibs op counting micro-ops 83 84RAW HARDWARE EVENT DESCRIPTOR 85----------------------------- 86Even when an event is not available in a symbolic form within perf right now, 87it can be encoded in a per processor specific way. 88 89For instance For x86 CPUs NNN represents the raw register encoding with the 90layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout 91of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344, 92Figure 13-7 Performance Event-Select Register (PerfEvtSeln)). 93 94Note: Only the following bit fields can be set in x86 counter 95registers: event, umask, edge, inv, cmask. Esp. guest/host only and 96OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT 97MODIFIERS>>. 98 99Example: 100 101If the Intel docs for a QM720 Core i7 describe an event as: 102 103 Event Umask Event Mask 104 Num. Value Mnemonic Description Comment 105 106 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and 107 delivered by loop stream detector invert to count 108 cycles 109 110raw encoding of 0x1A8 can be used: 111 112 perf stat -e r1a8 -a sleep 1 113 perf record -e r1a8 ... 114 115You should refer to the processor specific documentation for getting these 116details. Some of them are referenced in the SEE ALSO section below. 117 118ARBITRARY PMUS 119-------------- 120 121perf also supports an extended syntax for specifying raw parameters 122to PMUs. Using this typically requires looking up the specific event 123in the CPU vendor specific documentation. 124 125The available PMUs and their raw parameters can be listed with 126 127 ls /sys/devices/*/format 128 129For example the raw event "LSD.UOPS" core pmu event above could 130be specified as 131 132 perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=0x1/ ... 133 134 or using extended name syntax 135 136 perf stat -e cpu/event=0xa8,umask=0x1,cmask=0x1,name=\'LSD.UOPS_CYCLES:cmask=0x1\'/ ... 137 138PER SOCKET PMUS 139--------------- 140 141Some PMUs are not associated with a core, but with a whole CPU socket. 142Events on these PMUs generally cannot be sampled, but only counted globally 143with perf stat -a. They can be bound to one logical CPU, but will measure 144all the CPUs in the same socket. 145 146This example measures memory bandwidth every second 147on the first memory controller on socket 0 of a Intel Xeon system 148 149 perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ... 150 151Each memory controller has its own PMU. Measuring the complete system 152bandwidth would require specifying all imc PMUs (see perf list output), 153and adding the values together. To simplify creation of multiple events, 154prefix and glob matching is supported in the PMU name, and the prefix 155'uncore_' is also ignored when performing the match. So the command above 156can be expanded to all memory controllers by using the syntaxes: 157 158 perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ... 159 perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ... 160 161This example measures the combined core power every second 162 163 perf stat -I 1000 -e power/energy-cores/ -a 164 165ACCESS RESTRICTIONS 166------------------- 167 168For non root users generally only context switched PMU events are available. 169This is normally only the events in the cpu PMU, the predefined events 170like cycles and instructions and some software events. 171 172Other PMUs and global measurements are normally root only. 173Some event qualifiers, such as "any", are also root only. 174 175This can be overridden by setting the kernel.perf_event_paranoid 176sysctl to -1, which allows non root to use these events. 177 178For accessing trace point events perf needs to have read access to 179/sys/kernel/debug/tracing, even when perf_event_paranoid is in a relaxed 180setting. 181 182TRACING 183------- 184 185Some PMUs control advanced hardware tracing capabilities, such as Intel PT, 186that allows low overhead execution tracing. These are described in a separate 187intel-pt.txt document. 188 189PARAMETERIZED EVENTS 190-------------------- 191 192Some pmu events listed by 'perf-list' will be displayed with '?' in them. For 193example: 194 195 hv_gpci/dtbp_ptitc,phys_processor_idx=?/ 196 197This means that when provided as an event, a value for '?' must 198also be supplied. For example: 199 200 perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ... 201 202EVENT GROUPS 203------------ 204 205Perf supports time based multiplexing of events, when the number of events 206active exceeds the number of hardware performance counters. Multiplexing 207can cause measurement errors when the workload changes its execution 208profile. 209 210When metrics are computed using formulas from event counts, it is useful to 211ensure some events are always measured together as a group to minimize multiplexing 212errors. Event groups can be specified using { }. 213 214 perf stat -e '{instructions,cycles}' ... 215 216The number of available performance counters depend on the CPU. A group 217cannot contain more events than available counters. 218For example Intel Core CPUs typically have four generic performance counters 219for the core, plus three fixed counters for instructions, cycles and 220ref-cycles. Some special events have restrictions on which counter they 221can schedule, and may not support multiple instances in a single group. 222When too many events are specified in the group some of them will not 223be measured. 224 225Globally pinned events can limit the number of counters available for 226other groups. On x86 systems, the NMI watchdog pins a counter by default. 227The nmi watchdog can be disabled as root with 228 229 echo 0 > /proc/sys/kernel/nmi_watchdog 230 231Events from multiple different PMUs cannot be mixed in a group, with 232some exceptions for software events. 233 234LEADER SAMPLING 235--------------- 236 237perf also supports group leader sampling using the :S specifier. 238 239 perf record -e '{cycles,instructions}:S' ... 240 perf report --group 241 242Normally all events in an event group sample, but with :S only 243the first event (the leader) samples, and it only reads the values of the 244other events in the group. 245 246OPTIONS 247------- 248 249Without options all known events will be listed. 250 251To limit the list use: 252 253. 'hw' or 'hardware' to list hardware events such as cache-misses, etc. 254 255. 'sw' or 'software' to list software events such as context switches, etc. 256 257. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc. 258 259. 'tracepoint' to list all tracepoint events, alternatively use 260 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched, 261 block, etc. 262 263. 'pmu' to print the kernel supplied PMU events. 264 265. 'sdt' to list all Statically Defined Tracepoint events. 266 267. 'metric' to list metrics 268 269. 'metricgroup' to list metricgroups with metrics. 270 271. If none of the above is matched, it will apply the supplied glob to all 272 events, printing the ones that match. 273 274. As a last resort, it will do a substring search in all event names. 275 276One or more types can be used at the same time, listing the events for the 277types specified. 278 279Support raw format: 280 281. '--raw-dump', shows the raw-dump of all the events. 282. '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of 283 a certain kind of events. 284 285SEE ALSO 286-------- 287linkperf:perf-stat[1], linkperf:perf-top[1], 288linkperf:perf-record[1], 289http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide], 290http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming] 291