1perf-list(1) 2============ 3 4NAME 5---- 6perf-list - List all symbolic event types 7 8SYNOPSIS 9-------- 10[verse] 11'perf list' 12 13DESCRIPTION 14----------- 15This command displays the symbolic event types which can be selected in the 16various perf commands with the -e option. 17 18RAW HARDWARE EVENT DESCRIPTOR 19----------------------------- 20Even when an event is not available in a symbolic form within perf right now, 21it can be encoded in a per processor specific way. 22 23For instance For x86 CPUs NNN represents the raw register encoding with the 24layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout 25of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344, 26Figure 13-7 Performance Event-Select Register (PerfEvtSeln)). 27 28Example: 29 30If the Intel docs for a QM720 Core i7 describe an event as: 31 32 Event Umask Event Mask 33 Num. Value Mnemonic Description Comment 34 35 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and 36 delivered by loop stream detector invert to count 37 cycles 38 39raw encoding of 0x1A8 can be used: 40 41 perf stat -e r1a8 -a sleep 1 42 perf record -e r1a8 ... 43 44You should refer to the processor specific documentation for getting these 45details. Some of them are referenced in the SEE ALSO section below. 46 47OPTIONS 48------- 49None 50 51SEE ALSO 52-------- 53linkperf:perf-stat[1], linkperf:perf-top[1], 54linkperf:perf-record[1], 55http://www.intel.com/Assets/PDF/manual/253669.pdf[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide], 56http://support.amd.com/us/Processor_TechDocs/24593.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming] 57