1perf-list(1) 2============ 3 4NAME 5---- 6perf-list - List all symbolic event types 7 8SYNOPSIS 9-------- 10[verse] 11'perf list' [<options>] 12 [hw|sw|cache|tracepoint|pmu|sdt|metric|metricgroup|event_glob] 13 14DESCRIPTION 15----------- 16This command displays the symbolic event types which can be selected in the 17various perf commands with the -e option. 18 19OPTIONS 20------- 21-d:: 22--desc:: 23Print extra event descriptions. (default) 24 25--no-desc:: 26Don't print descriptions. 27 28-v:: 29--long-desc:: 30Print longer event descriptions and all similar PMUs with alphanumeric suffixes. 31 32--debug:: 33Enable debugging output. 34 35--details:: 36Print how named events are resolved internally into perf events, and also 37any extra expressions computed by perf stat. 38 39--deprecated:: 40Print deprecated events. By default the deprecated events are hidden. 41 42--unit:: 43Print PMU events and metrics limited to the specific PMU name. 44(e.g. --unit cpu, --unit msr, --unit cpu_core, --unit cpu_atom) 45 46-j:: 47--json:: 48Output in JSON format. 49 50-o:: 51--output=:: 52 Output file name. By default output is written to stdout. 53 54[[EVENT_MODIFIERS]] 55EVENT MODIFIERS 56--------------- 57 58Events can optionally have a modifier by appending a colon and one or 59more modifiers. Modifiers allow the user to restrict the events to be 60counted. The following modifiers exist: 61 62 u - user-space counting 63 k - kernel counting 64 h - hypervisor counting 65 I - non idle counting 66 G - guest counting (in KVM guests) 67 H - host counting (not in KVM guests) 68 p - precise level 69 P - use maximum detected precise level 70 S - read sample value (PERF_SAMPLE_READ) 71 D - pin the event to the PMU 72 W - group is weak and will fallback to non-group if not schedulable, 73 e - group or event are exclusive and do not share the PMU 74 b - use BPF aggregration (see perf stat --bpf-counters) 75 R - retire latency value of the event 76 X - don't regroup the event to match PMUs 77 78The 'p' modifier can be used for specifying how precise the instruction 79address should be. The 'p' modifier can be specified multiple times: 80 81 0 - SAMPLE_IP can have arbitrary skid 82 1 - SAMPLE_IP must have constant skid 83 2 - SAMPLE_IP requested to have 0 skid 84 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid 85 sample shadowing effects. 86 87For Intel systems precise event sampling is implemented with PEBS 88which supports up to precise-level 2, and precise level 3 for 89some special cases 90 91On AMD systems it is implemented using IBS OP (up to precise-level 2). 92Unlike Intel PEBS which provides levels of precision, AMD core pmu is 93inherently non-precise and IBS is inherently precise. (i.e. ibs_op//, 94ibs_op//p, ibs_op//pp and ibs_op//ppp are all same). The precise modifier 95works with event types 0x76 (cpu-cycles, CPU clocks not halted) and 0xC1 96(micro-ops retired). Both events map to IBS execution sampling (IBS op) 97with the IBS Op Counter Control bit (IbsOpCntCtl) set respectively (see the 98Core Complex (CCX) -> Processor x86 Core -> Instruction Based Sampling (IBS) 99section of the [AMD Processor Programming Reference (PPR)] relevant to the 100family, model and stepping of the processor being used). 101 102Manual Volume 2: System Programming, 13.3 Instruction-Based 103Sampling). Examples to use IBS: 104 105 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles 106 perf record -a -e r076:p ... # same as -e cpu-cycles:p 107 perf record -a -e r0C1:p ... # use ibs op counting micro-ops 108 109RAW HARDWARE EVENT DESCRIPTOR 110----------------------------- 111Even when an event is not available in a symbolic form within perf right now, 112it can be encoded in a per processor specific way. 113 114For instance on x86 CPUs, N is a hexadecimal value that represents the raw register encoding with the 115layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout 116of IA32_PERFEVTSELx MSRs) or AMD's PERF_CTL MSRs (see the 117Core Complex (CCX) -> Processor x86 Core -> MSR Registers section of the 118[AMD Processor Programming Reference (PPR)] relevant to the family, model 119and stepping of the processor being used). 120 121Note: Only the following bit fields can be set in x86 counter 122registers: event, umask, edge, inv, cmask. Esp. guest/host only and 123OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT 124MODIFIERS>>. 125 126Example: 127 128If the Intel docs for a QM720 Core i7 describe an event as: 129 130 Event Umask Event Mask 131 Num. Value Mnemonic Description Comment 132 133 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and 134 delivered by loop stream detector invert to count 135 cycles 136 137raw encoding of 0x1A8 can be used: 138 139 perf stat -e r1a8 -a sleep 1 140 perf record -e r1a8 ... 141 142It's also possible to use pmu syntax: 143 144 perf record -e r1a8 -a sleep 1 145 perf record -e cpu/r1a8/ ... 146 perf record -e cpu/r0x1a8/ ... 147 148Some processors, like those from AMD, support event codes and unit masks 149larger than a byte. In such cases, the bits corresponding to the event 150configuration parameters can be seen with: 151 152 cat /sys/bus/event_source/devices/<pmu>/format/<config> 153 154Example: 155 156If the AMD docs for an EPYC 7713 processor describe an event as: 157 158 Event Umask Event Mask 159 Num. Value Mnemonic Description 160 161 28FH 03H op_cache_hit_miss.op_cache_hit Counts Op Cache micro-tag 162 hit events. 163 164raw encoding of 0x0328F cannot be used since the upper nibble of the 165EventSelect bits have to be specified via bits 32-35 as can be seen with: 166 167 cat /sys/bus/event_source/devices/cpu/format/event 168 169raw encoding of 0x20000038F should be used instead: 170 171 perf stat -e r20000038f -a sleep 1 172 perf record -e r20000038f ... 173 174It's also possible to use pmu syntax: 175 176 perf record -e r20000038f -a sleep 1 177 perf record -e cpu/r20000038f/ ... 178 perf record -e cpu/r0x20000038f/ ... 179 180You should refer to the processor specific documentation for getting these 181details. Some of them are referenced in the SEE ALSO section below. 182 183ARBITRARY PMUS 184-------------- 185 186perf also supports an extended syntax for specifying raw parameters 187to PMUs. Using this typically requires looking up the specific event 188in the CPU vendor specific documentation. 189 190The available PMUs and their raw parameters can be listed with 191 192 ls /sys/bus/event_source/devices/*/format 193 194For example the raw event "LSD.UOPS" core pmu event above could 195be specified as 196 197 perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=0x1/ ... 198 199 or using extended name syntax 200 201 perf stat -e cpu/event=0xa8,umask=0x1,cmask=0x1,name=\'LSD.UOPS_CYCLES:cmask=0x1\'/ ... 202 203PER SOCKET PMUS 204--------------- 205 206Some PMUs are not associated with a core, but with a whole CPU socket. 207Events on these PMUs generally cannot be sampled, but only counted globally 208with perf stat -a. They can be bound to one logical CPU, but will measure 209all the CPUs in the same socket. 210 211This example measures memory bandwidth every second 212on the first memory controller on socket 0 of a Intel Xeon system 213 214 perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ... 215 216Each memory controller has its own PMU. Measuring the complete system 217bandwidth would require specifying all imc PMUs (see perf list output), 218and adding the values together. To simplify creation of multiple events, 219prefix and glob matching is supported in the PMU name, and the prefix 220'uncore_' is also ignored when performing the match. So the command above 221can be expanded to all memory controllers by using the syntaxes: 222 223 perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ... 224 perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ... 225 226This example measures the combined core power every second 227 228 perf stat -I 1000 -e power/energy-cores/ -a 229 230ACCESS RESTRICTIONS 231------------------- 232 233For non root users generally only context switched PMU events are available. 234This is normally only the events in the cpu PMU, the predefined events 235like cycles and instructions and some software events. 236 237Other PMUs and global measurements are normally root only. 238Some event qualifiers, such as "any", are also root only. 239 240This can be overridden by setting the kernel.perf_event_paranoid 241sysctl to -1, which allows non root to use these events. 242 243For accessing trace point events perf needs to have read access to 244/sys/kernel/tracing, even when perf_event_paranoid is in a relaxed 245setting. 246 247TOOL/HWMON EVENTS 248----------------- 249 250Some events don't have an associated PMU instead reading values 251available to software without perf_event_open. As these events don't 252support sampling they can only really be read by tools like perf stat. 253 254Tool events provide times and certain system parameters. Examples 255include duration_time, user_time, system_time and num_cpus_online. 256 257Hwmon events provide easy access to hwmon sysfs data typically in 258/sys/class/hwmon. This information includes temperatures, fan speeds 259and energy usage. 260 261 262TRACING 263------- 264 265Some PMUs control advanced hardware tracing capabilities, such as Intel PT, 266that allows low overhead execution tracing. These are described in a separate 267intel-pt.txt document. 268 269PARAMETERIZED EVENTS 270-------------------- 271 272Some pmu events listed by 'perf-list' will be displayed with '?' in them. For 273example: 274 275 hv_gpci/dtbp_ptitc,phys_processor_idx=?/ 276 277This means that when provided as an event, a value for '?' must 278also be supplied. For example: 279 280 perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ... 281 282EVENT QUALIFIERS 283---------------- 284 285It is also possible to add extra qualifiers to an event: 286 287percore: 288 289 Sums up the event counts for all hardware threads in a core, e.g.: 290 perf stat -e cpu/event=0,umask=0x3,percore=1/ 291 292cpu: 293 294 Specifies a CPU or a range of CPUs to open the event upon. It may 295 also reference a PMU to copy the CPU mask from. The value may be 296 repeated to specify opening the event on multiple CPUs. 297 298 Example 1: to open the instructions event on CPUs 0 and 2, the 299 cycles event on CPUs 1 and 2: 300 perf stat -e instructions/cpu=0,cpu=2/,cycles/cpu=1-2/ -a sleep 1 301 302 Example 2: to open the data_read uncore event on CPU 0 and the 303 data_write uncore event on CPU 1: 304 perf stat -e data_read/cpu=0/,data_write/cpu=1/ -a sleep 1 305 306 Example 3: to open the software msr/tsc/ event only on the CPUs 307 matching those from the cpu_core PMU: 308 perf stat -e msr/tsc,cpu=cpu_core/ -a sleep 1 309 310EVENT GROUPS 311------------ 312 313Perf supports time based multiplexing of events, when the number of events 314active exceeds the number of hardware performance counters. Multiplexing 315can cause measurement errors when the workload changes its execution 316profile. 317 318When metrics are computed using formulas from event counts, it is useful to 319ensure some events are always measured together as a group to minimize multiplexing 320errors. Event groups can be specified using { }. 321 322 perf stat -e '{instructions,cycles}' ... 323 324The number of available performance counters depend on the CPU. A group 325cannot contain more events than available counters. 326For example Intel Core CPUs typically have four generic performance counters 327for the core, plus three fixed counters for instructions, cycles and 328ref-cycles. Some special events have restrictions on which counter they 329can schedule, and may not support multiple instances in a single group. 330When too many events are specified in the group some of them will not 331be measured. 332 333Globally pinned events can limit the number of counters available for 334other groups. On x86 systems, the NMI watchdog pins a counter by default. 335The nmi watchdog can be disabled as root with 336 337 echo 0 > /proc/sys/kernel/nmi_watchdog 338 339Events from multiple different PMUs cannot be mixed in a group, with 340some exceptions for software events. 341 342LEADER SAMPLING 343--------------- 344 345perf also supports group leader sampling using the :S specifier. 346 347 perf record -e '{cycles,instructions}:S' ... 348 perf report --group 349 350Normally all events in an event group sample, but with :S only 351the first event (the leader) samples, and it only reads the values of the 352other events in the group. 353 354However, in the case AUX area events (e.g. Intel PT or CoreSight), the AUX 355area event must be the leader, so then the second event samples, not the first. 356 357OPTIONS 358------- 359 360Without options all known events will be listed. 361 362To limit the list use: 363 364. 'hw' or 'hardware' to list hardware events such as cache-misses, etc. 365 366. 'sw' or 'software' to list software events such as context switches, etc. 367 368. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc. 369 370. 'tracepoint' to list all tracepoint events, alternatively use 371 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched, 372 block, etc. 373 374. 'pmu' to print the kernel supplied PMU events. 375 376. 'sdt' to list all Statically Defined Tracepoint events. 377 378. 'metric' to list metrics 379 380. 'metricgroup' to list metricgroups with metrics. 381 382. If none of the above is matched, it will apply the supplied glob to all 383 events, printing the ones that match. 384 385. As a last resort, it will do a substring search in all event names. 386 387One or more types can be used at the same time, listing the events for the 388types specified. 389 390Support raw format: 391 392. '--raw-dump', shows the raw-dump of all the events. 393. '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of 394 a certain kind of events. 395 396include::intel-acr.txt[] 397 398SEE ALSO 399-------- 400linkperf:perf-stat[1], linkperf:perf-top[1], 401linkperf:perf-record[1], 402http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide], 403https://bugzilla.kernel.org/show_bug.cgi?id=206537[AMD Processor Programming Reference (PPR)] 404