1perf-list(1) 2============ 3 4NAME 5---- 6perf-list - List all symbolic event types 7 8SYNOPSIS 9-------- 10[verse] 11'perf list' [<options>] 12 [hw|sw|cache|tracepoint|pmu|sdt|metric|metricgroup|event_glob] 13 14DESCRIPTION 15----------- 16This command displays the symbolic event types which can be selected in the 17various perf commands with the -e option. 18 19OPTIONS 20------- 21-d:: 22--desc:: 23Print extra event descriptions. (default) 24 25--no-desc:: 26Don't print descriptions. 27 28-v:: 29--long-desc:: 30Print longer event descriptions. 31 32--debug:: 33Enable debugging output. 34 35--details:: 36Print how named events are resolved internally into perf events, and also 37any extra expressions computed by perf stat. 38 39--deprecated:: 40Print deprecated events. By default the deprecated events are hidden. 41 42--unit:: 43Print PMU events and metrics limited to the specific PMU name. 44(e.g. --unit cpu, --unit msr, --unit cpu_core, --unit cpu_atom) 45 46-j:: 47--json:: 48Output in JSON format. 49 50-o:: 51--output=:: 52 Output file name. By default output is written to stdout. 53 54[[EVENT_MODIFIERS]] 55EVENT MODIFIERS 56--------------- 57 58Events can optionally have a modifier by appending a colon and one or 59more modifiers. Modifiers allow the user to restrict the events to be 60counted. The following modifiers exist: 61 62 u - user-space counting 63 k - kernel counting 64 h - hypervisor counting 65 I - non idle counting 66 G - guest counting (in KVM guests) 67 H - host counting (not in KVM guests) 68 p - precise level 69 P - use maximum detected precise level 70 S - read sample value (PERF_SAMPLE_READ) 71 D - pin the event to the PMU 72 W - group is weak and will fallback to non-group if not schedulable, 73 e - group or event are exclusive and do not share the PMU 74 b - use BPF aggregration (see perf stat --bpf-counters) 75 R - retire latency value of the event 76 77The 'p' modifier can be used for specifying how precise the instruction 78address should be. The 'p' modifier can be specified multiple times: 79 80 0 - SAMPLE_IP can have arbitrary skid 81 1 - SAMPLE_IP must have constant skid 82 2 - SAMPLE_IP requested to have 0 skid 83 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid 84 sample shadowing effects. 85 86For Intel systems precise event sampling is implemented with PEBS 87which supports up to precise-level 2, and precise level 3 for 88some special cases 89 90On AMD systems it is implemented using IBS OP (up to precise-level 2). 91Unlike Intel PEBS which provides levels of precision, AMD core pmu is 92inherently non-precise and IBS is inherently precise. (i.e. ibs_op//, 93ibs_op//p, ibs_op//pp and ibs_op//ppp are all same). The precise modifier 94works with event types 0x76 (cpu-cycles, CPU clocks not halted) and 0xC1 95(micro-ops retired). Both events map to IBS execution sampling (IBS op) 96with the IBS Op Counter Control bit (IbsOpCntCtl) set respectively (see the 97Core Complex (CCX) -> Processor x86 Core -> Instruction Based Sampling (IBS) 98section of the [AMD Processor Programming Reference (PPR)] relevant to the 99family, model and stepping of the processor being used). 100 101Manual Volume 2: System Programming, 13.3 Instruction-Based 102Sampling). Examples to use IBS: 103 104 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles 105 perf record -a -e r076:p ... # same as -e cpu-cycles:p 106 perf record -a -e r0C1:p ... # use ibs op counting micro-ops 107 108RAW HARDWARE EVENT DESCRIPTOR 109----------------------------- 110Even when an event is not available in a symbolic form within perf right now, 111it can be encoded in a per processor specific way. 112 113For instance on x86 CPUs, N is a hexadecimal value that represents the raw register encoding with the 114layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout 115of IA32_PERFEVTSELx MSRs) or AMD's PERF_CTL MSRs (see the 116Core Complex (CCX) -> Processor x86 Core -> MSR Registers section of the 117[AMD Processor Programming Reference (PPR)] relevant to the family, model 118and stepping of the processor being used). 119 120Note: Only the following bit fields can be set in x86 counter 121registers: event, umask, edge, inv, cmask. Esp. guest/host only and 122OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT 123MODIFIERS>>. 124 125Example: 126 127If the Intel docs for a QM720 Core i7 describe an event as: 128 129 Event Umask Event Mask 130 Num. Value Mnemonic Description Comment 131 132 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and 133 delivered by loop stream detector invert to count 134 cycles 135 136raw encoding of 0x1A8 can be used: 137 138 perf stat -e r1a8 -a sleep 1 139 perf record -e r1a8 ... 140 141It's also possible to use pmu syntax: 142 143 perf record -e r1a8 -a sleep 1 144 perf record -e cpu/r1a8/ ... 145 perf record -e cpu/r0x1a8/ ... 146 147Some processors, like those from AMD, support event codes and unit masks 148larger than a byte. In such cases, the bits corresponding to the event 149configuration parameters can be seen with: 150 151 cat /sys/bus/event_source/devices/<pmu>/format/<config> 152 153Example: 154 155If the AMD docs for an EPYC 7713 processor describe an event as: 156 157 Event Umask Event Mask 158 Num. Value Mnemonic Description 159 160 28FH 03H op_cache_hit_miss.op_cache_hit Counts Op Cache micro-tag 161 hit events. 162 163raw encoding of 0x0328F cannot be used since the upper nibble of the 164EventSelect bits have to be specified via bits 32-35 as can be seen with: 165 166 cat /sys/bus/event_source/devices/cpu/format/event 167 168raw encoding of 0x20000038F should be used instead: 169 170 perf stat -e r20000038f -a sleep 1 171 perf record -e r20000038f ... 172 173It's also possible to use pmu syntax: 174 175 perf record -e r20000038f -a sleep 1 176 perf record -e cpu/r20000038f/ ... 177 perf record -e cpu/r0x20000038f/ ... 178 179You should refer to the processor specific documentation for getting these 180details. Some of them are referenced in the SEE ALSO section below. 181 182ARBITRARY PMUS 183-------------- 184 185perf also supports an extended syntax for specifying raw parameters 186to PMUs. Using this typically requires looking up the specific event 187in the CPU vendor specific documentation. 188 189The available PMUs and their raw parameters can be listed with 190 191 ls /sys/devices/*/format 192 193For example the raw event "LSD.UOPS" core pmu event above could 194be specified as 195 196 perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=0x1/ ... 197 198 or using extended name syntax 199 200 perf stat -e cpu/event=0xa8,umask=0x1,cmask=0x1,name=\'LSD.UOPS_CYCLES:cmask=0x1\'/ ... 201 202PER SOCKET PMUS 203--------------- 204 205Some PMUs are not associated with a core, but with a whole CPU socket. 206Events on these PMUs generally cannot be sampled, but only counted globally 207with perf stat -a. They can be bound to one logical CPU, but will measure 208all the CPUs in the same socket. 209 210This example measures memory bandwidth every second 211on the first memory controller on socket 0 of a Intel Xeon system 212 213 perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ... 214 215Each memory controller has its own PMU. Measuring the complete system 216bandwidth would require specifying all imc PMUs (see perf list output), 217and adding the values together. To simplify creation of multiple events, 218prefix and glob matching is supported in the PMU name, and the prefix 219'uncore_' is also ignored when performing the match. So the command above 220can be expanded to all memory controllers by using the syntaxes: 221 222 perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ... 223 perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ... 224 225This example measures the combined core power every second 226 227 perf stat -I 1000 -e power/energy-cores/ -a 228 229ACCESS RESTRICTIONS 230------------------- 231 232For non root users generally only context switched PMU events are available. 233This is normally only the events in the cpu PMU, the predefined events 234like cycles and instructions and some software events. 235 236Other PMUs and global measurements are normally root only. 237Some event qualifiers, such as "any", are also root only. 238 239This can be overridden by setting the kernel.perf_event_paranoid 240sysctl to -1, which allows non root to use these events. 241 242For accessing trace point events perf needs to have read access to 243/sys/kernel/tracing, even when perf_event_paranoid is in a relaxed 244setting. 245 246TOOL/HWMON EVENTS 247----------------- 248 249Some events don't have an associated PMU instead reading values 250available to software without perf_event_open. As these events don't 251support sampling they can only really be read by tools like perf stat. 252 253Tool events provide times and certain system parameters. Examples 254include duration_time, user_time, system_time and num_cpus_online. 255 256Hwmon events provide easy access to hwmon sysfs data typically in 257/sys/class/hwmon. This information includes temperatures, fan speeds 258and energy usage. 259 260 261TRACING 262------- 263 264Some PMUs control advanced hardware tracing capabilities, such as Intel PT, 265that allows low overhead execution tracing. These are described in a separate 266intel-pt.txt document. 267 268PARAMETERIZED EVENTS 269-------------------- 270 271Some pmu events listed by 'perf-list' will be displayed with '?' in them. For 272example: 273 274 hv_gpci/dtbp_ptitc,phys_processor_idx=?/ 275 276This means that when provided as an event, a value for '?' must 277also be supplied. For example: 278 279 perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ... 280 281EVENT QUALIFIERS: 282 283It is also possible to add extra qualifiers to an event: 284 285percore: 286 287Sums up the event counts for all hardware threads in a core, e.g.: 288 289 290 perf stat -e cpu/event=0,umask=0x3,percore=1/ 291 292 293EVENT GROUPS 294------------ 295 296Perf supports time based multiplexing of events, when the number of events 297active exceeds the number of hardware performance counters. Multiplexing 298can cause measurement errors when the workload changes its execution 299profile. 300 301When metrics are computed using formulas from event counts, it is useful to 302ensure some events are always measured together as a group to minimize multiplexing 303errors. Event groups can be specified using { }. 304 305 perf stat -e '{instructions,cycles}' ... 306 307The number of available performance counters depend on the CPU. A group 308cannot contain more events than available counters. 309For example Intel Core CPUs typically have four generic performance counters 310for the core, plus three fixed counters for instructions, cycles and 311ref-cycles. Some special events have restrictions on which counter they 312can schedule, and may not support multiple instances in a single group. 313When too many events are specified in the group some of them will not 314be measured. 315 316Globally pinned events can limit the number of counters available for 317other groups. On x86 systems, the NMI watchdog pins a counter by default. 318The nmi watchdog can be disabled as root with 319 320 echo 0 > /proc/sys/kernel/nmi_watchdog 321 322Events from multiple different PMUs cannot be mixed in a group, with 323some exceptions for software events. 324 325LEADER SAMPLING 326--------------- 327 328perf also supports group leader sampling using the :S specifier. 329 330 perf record -e '{cycles,instructions}:S' ... 331 perf report --group 332 333Normally all events in an event group sample, but with :S only 334the first event (the leader) samples, and it only reads the values of the 335other events in the group. 336 337However, in the case AUX area events (e.g. Intel PT or CoreSight), the AUX 338area event must be the leader, so then the second event samples, not the first. 339 340OPTIONS 341------- 342 343Without options all known events will be listed. 344 345To limit the list use: 346 347. 'hw' or 'hardware' to list hardware events such as cache-misses, etc. 348 349. 'sw' or 'software' to list software events such as context switches, etc. 350 351. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc. 352 353. 'tracepoint' to list all tracepoint events, alternatively use 354 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched, 355 block, etc. 356 357. 'pmu' to print the kernel supplied PMU events. 358 359. 'sdt' to list all Statically Defined Tracepoint events. 360 361. 'metric' to list metrics 362 363. 'metricgroup' to list metricgroups with metrics. 364 365. If none of the above is matched, it will apply the supplied glob to all 366 events, printing the ones that match. 367 368. As a last resort, it will do a substring search in all event names. 369 370One or more types can be used at the same time, listing the events for the 371types specified. 372 373Support raw format: 374 375. '--raw-dump', shows the raw-dump of all the events. 376. '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of 377 a certain kind of events. 378 379SEE ALSO 380-------- 381linkperf:perf-stat[1], linkperf:perf-top[1], 382linkperf:perf-record[1], 383http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide], 384https://bugzilla.kernel.org/show_bug.cgi?id=206537[AMD Processor Programming Reference (PPR)] 385