1perf-list(1) 2============ 3 4NAME 5---- 6perf-list - List all symbolic event types 7 8SYNOPSIS 9-------- 10[verse] 11'perf list' [hw|sw|cache|tracepoint|pmu|event_glob] 12 13DESCRIPTION 14----------- 15This command displays the symbolic event types which can be selected in the 16various perf commands with the -e option. 17 18[[EVENT_MODIFIERS]] 19EVENT MODIFIERS 20--------------- 21 22Events can optionally have a modifier by appending a colon and one or 23more modifiers. Modifiers allow the user to restrict the events to be 24counted. The following modifiers exist: 25 26 u - user-space counting 27 k - kernel counting 28 h - hypervisor counting 29 I - non idle counting 30 G - guest counting (in KVM guests) 31 H - host counting (not in KVM guests) 32 p - precise level 33 P - use maximum detected precise level 34 S - read sample value (PERF_SAMPLE_READ) 35 D - pin the event to the PMU 36 37The 'p' modifier can be used for specifying how precise the instruction 38address should be. The 'p' modifier can be specified multiple times: 39 40 0 - SAMPLE_IP can have arbitrary skid 41 1 - SAMPLE_IP must have constant skid 42 2 - SAMPLE_IP requested to have 0 skid 43 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid 44 sample shadowing effects. 45 46For Intel systems precise event sampling is implemented with PEBS 47which supports up to precise-level 2, and precise level 3 for 48some special cases 49 50On AMD systems it is implemented using IBS (up to precise-level 2). 51The precise modifier works with event types 0x76 (cpu-cycles, CPU 52clocks not halted) and 0xC1 (micro-ops retired). Both events map to 53IBS execution sampling (IBS op) with the IBS Op Counter Control bit 54(IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s 55Manual Volume 2: System Programming, 13.3 Instruction-Based 56Sampling). Examples to use IBS: 57 58 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles 59 perf record -a -e r076:p ... # same as -e cpu-cycles:p 60 perf record -a -e r0C1:p ... # use ibs op counting micro-ops 61 62RAW HARDWARE EVENT DESCRIPTOR 63----------------------------- 64Even when an event is not available in a symbolic form within perf right now, 65it can be encoded in a per processor specific way. 66 67For instance For x86 CPUs NNN represents the raw register encoding with the 68layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout 69of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344, 70Figure 13-7 Performance Event-Select Register (PerfEvtSeln)). 71 72Note: Only the following bit fields can be set in x86 counter 73registers: event, umask, edge, inv, cmask. Esp. guest/host only and 74OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT 75MODIFIERS>>. 76 77Example: 78 79If the Intel docs for a QM720 Core i7 describe an event as: 80 81 Event Umask Event Mask 82 Num. Value Mnemonic Description Comment 83 84 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and 85 delivered by loop stream detector invert to count 86 cycles 87 88raw encoding of 0x1A8 can be used: 89 90 perf stat -e r1a8 -a sleep 1 91 perf record -e r1a8 ... 92 93You should refer to the processor specific documentation for getting these 94details. Some of them are referenced in the SEE ALSO section below. 95 96ARBITRARY PMUS 97-------------- 98 99perf also supports an extended syntax for specifying raw parameters 100to PMUs. Using this typically requires looking up the specific event 101in the CPU vendor specific documentation. 102 103The available PMUs and their raw parameters can be listed with 104 105 ls /sys/devices/*/format 106 107For example the raw event "LSD.UOPS" core pmu event above could 108be specified as 109 110 perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=1/ ... 111 112PER SOCKET PMUS 113--------------- 114 115Some PMUs are not associated with a core, but with a whole CPU socket. 116Events on these PMUs generally cannot be sampled, but only counted globally 117with perf stat -a. They can be bound to one logical CPU, but will measure 118all the CPUs in the same socket. 119 120This example measures memory bandwidth every second 121on the first memory controller on socket 0 of a Intel Xeon system 122 123 perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ... 124 125Each memory controller has its own PMU. Measuring the complete system 126bandwidth would require specifying all imc PMUs (see perf list output), 127and adding the values together. 128 129This example measures the combined core power every second 130 131 perf stat -I 1000 -e power/energy-cores/ -a 132 133ACCESS RESTRICTIONS 134------------------- 135 136For non root users generally only context switched PMU events are available. 137This is normally only the events in the cpu PMU, the predefined events 138like cycles and instructions and some software events. 139 140Other PMUs and global measurements are normally root only. 141Some event qualifiers, such as "any", are also root only. 142 143This can be overriden by setting the kernel.perf_event_paranoid 144sysctl to -1, which allows non root to use these events. 145 146For accessing trace point events perf needs to have read access to 147/sys/kernel/debug/tracing, even when perf_event_paranoid is in a relaxed 148setting. 149 150TRACING 151------- 152 153Some PMUs control advanced hardware tracing capabilities, such as Intel PT, 154that allows low overhead execution tracing. These are described in a separate 155intel-pt.txt document. 156 157PARAMETERIZED EVENTS 158-------------------- 159 160Some pmu events listed by 'perf-list' will be displayed with '?' in them. For 161example: 162 163 hv_gpci/dtbp_ptitc,phys_processor_idx=?/ 164 165This means that when provided as an event, a value for '?' must 166also be supplied. For example: 167 168 perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ... 169 170EVENT GROUPS 171------------ 172 173Perf supports time based multiplexing of events, when the number of events 174active exceeds the number of hardware performance counters. Multiplexing 175can cause measurement errors when the workload changes its execution 176profile. 177 178When metrics are computed using formulas from event counts, it is useful to 179ensure some events are always measured together as a group to minimize multiplexing 180errors. Event groups can be specified using { }. 181 182 perf stat -e '{instructions,cycles}' ... 183 184The number of available performance counters depend on the CPU. A group 185cannot contain more events than available counters. 186For example Intel Core CPUs typically have four generic performance counters 187for the core, plus three fixed counters for instructions, cycles and 188ref-cycles. Some special events have restrictions on which counter they 189can schedule, and may not support multiple instances in a single group. 190When too many events are specified in the group none of them will not 191be measured. 192 193Globally pinned events can limit the number of counters available for 194other groups. On x86 systems, the NMI watchdog pins a counter by default. 195The nmi watchdog can be disabled as root with 196 197 echo 0 > /proc/sys/kernel/nmi_watchdog 198 199Events from multiple different PMUs cannot be mixed in a group, with 200some exceptions for software events. 201 202LEADER SAMPLING 203--------------- 204 205perf also supports group leader sampling using the :S specifier. 206 207 perf record -e '{cycles,instructions}:S' ... 208 perf report --group 209 210Normally all events in a event group sample, but with :S only 211the first event (the leader) samples, and it only reads the values of the 212other events in the group. 213 214OPTIONS 215------- 216 217Without options all known events will be listed. 218 219To limit the list use: 220 221. 'hw' or 'hardware' to list hardware events such as cache-misses, etc. 222 223. 'sw' or 'software' to list software events such as context switches, etc. 224 225. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc. 226 227. 'tracepoint' to list all tracepoint events, alternatively use 228 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched, 229 block, etc. 230 231. 'pmu' to print the kernel supplied PMU events. 232 233. If none of the above is matched, it will apply the supplied glob to all 234 events, printing the ones that match. 235 236. As a last resort, it will do a substring search in all event names. 237 238One or more types can be used at the same time, listing the events for the 239types specified. 240 241Support raw format: 242 243. '--raw-dump', shows the raw-dump of all the events. 244. '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of 245 a certain kind of events. 246 247SEE ALSO 248-------- 249linkperf:perf-stat[1], linkperf:perf-top[1], 250linkperf:perf-record[1], 251http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide], 252http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming] 253