1perf-c2c(1) 2=========== 3 4NAME 5---- 6perf-c2c - Shared Data C2C/HITM Analyzer. 7 8SYNOPSIS 9-------- 10[verse] 11'perf c2c record' [<options>] <command> 12'perf c2c record' [<options>] \-- [<record command options>] <command> 13'perf c2c report' [<options>] 14 15DESCRIPTION 16----------- 17C2C stands for Cache To Cache. 18 19The perf c2c tool provides means for Shared Data C2C/HITM analysis. It allows 20you to track down the cacheline contentions. 21 22On Intel, the tool is based on load latency and precise store facility events 23provided by Intel CPUs. On PowerPC, the tool uses random instruction sampling 24with thresholding feature. On AMD, the tool uses IBS op pmu (due to hardware 25limitations, perf c2c is not supported on Zen3 cpus). On Arm64 it uses SPE to 26sample load and store operations, therefore hardware and kernel support is 27required. See linkperf:perf-arm-spe[1] for a setup guide. Due to the 28statistical nature of Arm SPE sampling, not every memory operation will be 29sampled. 30 31These events provide: 32 - memory address of the access 33 - type of the access (load and store details) 34 - latency (in cycles) of the load access 35 36The c2c tool provide means to record this data and report back access details 37for cachelines with highest contention - highest number of HITM accesses. 38 39The basic workflow with this tool follows the standard record/report phase. 40User uses the record command to record events data and report command to 41display it. 42 43 44RECORD OPTIONS 45-------------- 46-e:: 47--event=:: 48 Select the PMU event. Use 'perf c2c record -e list' 49 to list available events. 50 51-v:: 52--verbose:: 53 Be more verbose (show counter open errors, etc). 54 55-l:: 56--ldlat:: 57 Configure mem-loads latency. Supported on Intel, Arm64 and some AMD 58 processors. Ignored on other archs. 59 60 On supported AMD processors: 61 - /sys/bus/event_source/devices/ibs_op/caps/ldlat file contains '1'. 62 - Supported latency values are 128 to 2048 (both inclusive). 63 - Latency value which is a multiple of 128 incurs a little less profiling 64 overhead compared to other values. 65 - Load latency filtering is disabled by default. 66 67-k:: 68--all-kernel:: 69 Configure all used events to run in kernel space. 70 71-u:: 72--all-user:: 73 Configure all used events to run in user space. 74 75REPORT OPTIONS 76-------------- 77-k:: 78--vmlinux=<file>:: 79 vmlinux pathname 80 81-v:: 82--verbose:: 83 Be more verbose (show counter open errors, etc). 84 85-i:: 86--input:: 87 Specify the input file to process. 88 89-N:: 90--node-info:: 91 Show extra node info in report (see NODE INFO section) 92 93-c:: 94--coalesce:: 95 Specify sorting fields for single cacheline display. 96 Following fields are available: tid,pid,iaddr,dso 97 (see COALESCE) 98 99-g:: 100--call-graph:: 101 Setup callchains parameters. 102 Please refer to perf-report man page for details. 103 104--stdio:: 105 Force the stdio output (see STDIO OUTPUT) 106 107--stats:: 108 Display only statistic tables and force stdio mode. 109 110--full-symbols:: 111 Display full length of symbols. 112 113--no-source:: 114 Do not display Source:Line column. 115 116--show-all:: 117 Show all captured HITM lines, with no regard to HITM % 0.0005 limit. 118 119-f:: 120--force:: 121 Don't do ownership validation. 122 123-d:: 124--display:: 125 Switch to HITM type (rmt, lcl) or peer snooping type (peer) to display 126 and sort on. Total HITMs (tot) as default, except Arm64 uses peer mode 127 as default. 128 129--stitch-lbr:: 130 Show callgraph with stitched LBRs, which may have more complete 131 callgraph. The perf.data file must have been obtained using 132 perf c2c record --call-graph lbr. 133 Disabled by default. In common cases with call stack overflows, 134 it can recreate better call stacks than the default lbr call stack 135 output. But this approach is not foolproof. There can be cases 136 where it creates incorrect call stacks from incorrect matches. 137 The known limitations include exception handing such as 138 setjmp/longjmp will have calls/returns not match. 139 140--double-cl:: 141 Group the detection of shared cacheline events into double cacheline 142 granularity. Some architectures have an Adjacent Cacheline Prefetch 143 feature, which causes cacheline sharing to behave like the cacheline 144 size is doubled. 145 146-M:: 147--disassembler-style=:: 148 Set disassembler style for objdump. 149 150--objdump=<path>:: 151 Path to objdump binary. 152 153C2C RECORD 154---------- 155The perf c2c record command setup options related to HITM cacheline analysis 156and calls standard perf record command. 157 158Following perf record options are configured by default: 159(check perf record man page for details) 160 161 -W,-d,--phys-data,--sample-cpu 162 163Unless specified otherwise with '-e' option, following events are monitored by 164default on Intel: 165 166 cpu/mem-loads,ldlat=30/P 167 cpu/mem-stores/P 168 169following on AMD: 170 171 ibs_op// 172 173and following on PowerPC: 174 175 cpu/mem-loads/ 176 cpu/mem-stores/ 177 178User can pass any 'perf record' option behind '--' mark, like (to enable 179callchains and system wide monitoring): 180 181 $ perf c2c record -- -g -a 182 183Please check RECORD OPTIONS section for specific c2c record options. 184 185C2C REPORT 186---------- 187The perf c2c report command displays shared data analysis. It comes in two 188display modes: stdio and tui (default). 189 190The report command workflow is following: 191 - sort all the data based on the cacheline address 192 - store access details for each cacheline 193 - sort all cachelines based on user settings 194 - display data 195 196In general perf report output consist of 2 basic views: 197 1) most expensive cachelines list 198 2) offsets details for each cacheline 199 200For each cacheline in the 1) list we display following data: 201(Both stdio and TUI modes follow the same fields output) 202 203 Index 204 - zero based index to identify the cacheline 205 206 Cacheline 207 - cacheline address (hex number) 208 209 Rmt/Lcl Hitm (Display with HITM types) 210 - cacheline percentage of all Remote/Local HITM accesses 211 212 Peer Snoop (Display with peer type) 213 - cacheline percentage of all peer accesses 214 215 LLC Load Hitm - Total, LclHitm, RmtHitm (For display with HITM types) 216 - count of Total/Local/Remote load HITMs 217 218 Load Peer - Total, Local, Remote (For display with peer type) 219 - count of Total/Local/Remote load from peer cache or DRAM 220 221 Total records 222 - sum of all cachelines accesses 223 224 Total loads 225 - sum of all load accesses 226 227 Total stores 228 - sum of all store accesses 229 230 Store Reference - L1Hit, L1Miss, N/A 231 L1Hit - store accesses that hit L1 232 L1Miss - store accesses that missed L1 233 N/A - store accesses with memory level is not available 234 235 Core Load Hit - FB, L1, L2 236 - count of load hits in FB (Fill Buffer), L1 and L2 cache 237 238 LLC Load Hit - LlcHit, LclHitm 239 - count of LLC load accesses, includes LLC hits and LLC HITMs 240 241 RMT Load Hit - RmtHit, RmtHitm 242 - count of remote load accesses, includes remote hits and remote HITMs; 243 on Arm neoverse cores, RmtHit is used to account remote accesses, 244 includes remote DRAM or any upward cache level in remote node 245 246 Load Dram - Lcl, Rmt 247 - count of local and remote DRAM accesses 248 249For each offset in the 2) list we display following data: 250 251 HITM - Rmt, Lcl (Display with HITM types) 252 - % of Remote/Local HITM accesses for given offset within cacheline 253 254 Peer Snoop - Rmt, Lcl (Display with peer type) 255 - % of Remote/Local peer accesses for given offset within cacheline 256 257 Store Refs - L1 Hit, L1 Miss, N/A 258 - % of store accesses that hit L1, missed L1 and N/A (no available) memory 259 level for given offset within cacheline 260 261 Data address - Offset 262 - offset address 263 264 Pid 265 - pid of the process responsible for the accesses 266 267 Tid 268 - tid of the process responsible for the accesses 269 270 Code address 271 - code address responsible for the accesses 272 273 cycles - rmt hitm, lcl hitm, load (Display with HITM types) 274 - sum of cycles for given accesses - Remote/Local HITM and generic load 275 276 cycles - rmt peer, lcl peer, load (Display with peer type) 277 - sum of cycles for given accesses - Remote/Local peer load and generic load 278 279 cpu cnt 280 - number of cpus that participated on the access 281 282 Symbol 283 - code symbol related to the 'Code address' value 284 285 Shared Object 286 - shared object name related to the 'Code address' value 287 288 Source:Line 289 - source information related to the 'Code address' value 290 291 Node 292 - nodes participating on the access (see NODE INFO section) 293 294NODE INFO 295--------- 296The 'Node' field displays nodes that accesses given cacheline 297offset. Its output comes in 3 flavors: 298 - node IDs separated by ',' 299 - node IDs with stats for each ID, in following format: 300 Node{cpus %hitms %stores} (Display with HITM types) 301 Node{cpus %peers %stores} (Display with peer type) 302 - node IDs with list of affected CPUs in following format: 303 Node{cpu list} 304 305User can switch between above flavors with -N option or 306use 'n' key to interactively switch in TUI mode. 307 308COALESCE 309-------- 310User can specify how to sort offsets for cacheline. 311 312Following fields are available and governs the final 313output fields set for cacheline offsets output: 314 315 tid - coalesced by process TIDs 316 pid - coalesced by process PIDs 317 iaddr - coalesced by code address, following fields are displayed: 318 Code address, Code symbol, Shared Object, Source line 319 dso - coalesced by shared object 320 321By default the coalescing is setup with 'pid,iaddr'. 322 323STDIO OUTPUT 324------------ 325The stdio output displays data on standard output. 326 327Following tables are displayed: 328 Trace Event Information 329 - overall statistics of memory accesses 330 331 Global Shared Cache Line Event Information 332 - overall statistics on shared cachelines 333 334 Shared Data Cache Line Table 335 - list of most expensive cachelines 336 337 Shared Cache Line Distribution Pareto 338 - list of all accessed offsets for each cacheline 339 340TUI OUTPUT 341---------- 342The TUI output provides interactive interface to navigate 343through cachelines list and to display offset details. 344 345For details please refer to the help window by pressing '?' key. 346 347CREDITS 348------- 349Although Don Zickus, Dick Fowles and Joe Mario worked together 350to get this implemented, we got lots of early help from Arnaldo 351Carvalho de Melo, Stephane Eranian, Jiri Olsa and Andi Kleen. 352 353C2C BLOG 354-------- 355Check Joe's blog on c2c tool for detailed use case explanation: 356 https://joemario.github.io/blog/2016/09/01/c2c-blog/ 357 358SEE ALSO 359-------- 360linkperf:perf-record[1], linkperf:perf-mem[1], linkperf:perf-arm-spe[1] 361