1*71b7ff5eSAndrea ParriC SB+fencembonceonces 2*71b7ff5eSAndrea Parri 3*71b7ff5eSAndrea Parri(* 4*71b7ff5eSAndrea Parri * Result: Never 5*71b7ff5eSAndrea Parri * 6*71b7ff5eSAndrea Parri * This litmus test demonstrates that full memory barriers suffice to 7*71b7ff5eSAndrea Parri * order the store-buffering pattern, where each process writes to the 8*71b7ff5eSAndrea Parri * variable that the preceding process reads. (Locking and RCU can also 9*71b7ff5eSAndrea Parri * suffice, but not much else.) 10*71b7ff5eSAndrea Parri *) 11*71b7ff5eSAndrea Parri 12*71b7ff5eSAndrea Parri{} 13*71b7ff5eSAndrea Parri 14*71b7ff5eSAndrea ParriP0(int *x, int *y) 15*71b7ff5eSAndrea Parri{ 16*71b7ff5eSAndrea Parri int r0; 17*71b7ff5eSAndrea Parri 18*71b7ff5eSAndrea Parri WRITE_ONCE(*x, 1); 19*71b7ff5eSAndrea Parri smp_mb(); 20*71b7ff5eSAndrea Parri r0 = READ_ONCE(*y); 21*71b7ff5eSAndrea Parri} 22*71b7ff5eSAndrea Parri 23*71b7ff5eSAndrea ParriP1(int *x, int *y) 24*71b7ff5eSAndrea Parri{ 25*71b7ff5eSAndrea Parri int r0; 26*71b7ff5eSAndrea Parri 27*71b7ff5eSAndrea Parri WRITE_ONCE(*y, 1); 28*71b7ff5eSAndrea Parri smp_mb(); 29*71b7ff5eSAndrea Parri r0 = READ_ONCE(*x); 30*71b7ff5eSAndrea Parri} 31*71b7ff5eSAndrea Parri 32*71b7ff5eSAndrea Parriexists (0:r0=0 /\ 1:r0=0) 33