18a9fd832SMathieu Poirier /* SPDX-License-Identifier: GPL-2.0 */ 239ff5263SMathieu Poirier /* 339ff5263SMathieu Poirier * Copyright(C) 2015 Linaro Limited. All rights reserved. 439ff5263SMathieu Poirier * Author: Mathieu Poirier <mathieu.poirier@linaro.org> 539ff5263SMathieu Poirier */ 639ff5263SMathieu Poirier 739ff5263SMathieu Poirier #ifndef _LINUX_CORESIGHT_PMU_H 839ff5263SMathieu Poirier #define _LINUX_CORESIGHT_PMU_H 939ff5263SMathieu Poirier 1039ff5263SMathieu Poirier #define CORESIGHT_ETM_PMU_NAME "cs_etm" 1139ff5263SMathieu Poirier #define CORESIGHT_ETM_PMU_SEED 0x10 1239ff5263SMathieu Poirier 136c0afc57SArnaldo Carvalho de Melo /* 146c0afc57SArnaldo Carvalho de Melo * Below are the definition of bit offsets for perf option, and works as 156c0afc57SArnaldo Carvalho de Melo * arbitrary values for all ETM versions. 166c0afc57SArnaldo Carvalho de Melo * 176c0afc57SArnaldo Carvalho de Melo * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore, 186c0afc57SArnaldo Carvalho de Melo * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and 196c0afc57SArnaldo Carvalho de Melo * directly use below macros as config bits. 206c0afc57SArnaldo Carvalho de Melo */ 21*aca8af3cSJames Clark #define ETM_OPT_BRANCH_BROADCAST 8 2239ff5263SMathieu Poirier #define ETM_OPT_CYCACC 12 2382500a81SMathieu Poirier #define ETM_OPT_CTXTID 14 246c0afc57SArnaldo Carvalho de Melo #define ETM_OPT_CTXTID2 15 2539ff5263SMathieu Poirier #define ETM_OPT_TS 28 26b97971beSMike Leach #define ETM_OPT_RETSTK 29 2739ff5263SMathieu Poirier 28df770ff0SMike Leach /* ETMv4 CONFIGR programming bits for the ETM OPTs */ 29*aca8af3cSJames Clark #define ETM4_CFG_BIT_BB 3 30df770ff0SMike Leach #define ETM4_CFG_BIT_CYCACC 4 3182500a81SMathieu Poirier #define ETM4_CFG_BIT_CTXTID 6 326c0afc57SArnaldo Carvalho de Melo #define ETM4_CFG_BIT_VMID 7 33df770ff0SMike Leach #define ETM4_CFG_BIT_TS 11 34df770ff0SMike Leach #define ETM4_CFG_BIT_RETSTK 12 356c0afc57SArnaldo Carvalho de Melo #define ETM4_CFG_BIT_VMID_OPT 15 36df770ff0SMike Leach 3739ff5263SMathieu Poirier static inline int coresight_get_trace_id(int cpu) 3839ff5263SMathieu Poirier { 3939ff5263SMathieu Poirier /* 4039ff5263SMathieu Poirier * A trace ID of value 0 is invalid, so let's start at some 4139ff5263SMathieu Poirier * random value that fits in 7 bits and go from there. Since 4239ff5263SMathieu Poirier * the common convention is to have data trace IDs be I(N) + 1, 4339ff5263SMathieu Poirier * set instruction trace IDs as a function of the CPU number. 4439ff5263SMathieu Poirier */ 4539ff5263SMathieu Poirier return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); 4639ff5263SMathieu Poirier } 4739ff5263SMathieu Poirier 4839ff5263SMathieu Poirier #endif 49