18a9fd832SMathieu Poirier /* SPDX-License-Identifier: GPL-2.0 */ 239ff5263SMathieu Poirier /* 339ff5263SMathieu Poirier * Copyright(C) 2015 Linaro Limited. All rights reserved. 439ff5263SMathieu Poirier * Author: Mathieu Poirier <mathieu.poirier@linaro.org> 539ff5263SMathieu Poirier */ 639ff5263SMathieu Poirier 739ff5263SMathieu Poirier #ifndef _LINUX_CORESIGHT_PMU_H 839ff5263SMathieu Poirier #define _LINUX_CORESIGHT_PMU_H 939ff5263SMathieu Poirier 10*09277295SMike Leach #include <linux/bits.h> 11*09277295SMike Leach 1239ff5263SMathieu Poirier #define CORESIGHT_ETM_PMU_NAME "cs_etm" 1339ff5263SMathieu Poirier #define CORESIGHT_ETM_PMU_SEED 0x10 1439ff5263SMathieu Poirier 15*09277295SMike Leach /* CoreSight trace ID is currently the bottom 7 bits of the value */ 16*09277295SMike Leach #define CORESIGHT_TRACE_ID_VAL_MASK GENMASK(6, 0) 17*09277295SMike Leach 186c0afc57SArnaldo Carvalho de Melo /* 196c0afc57SArnaldo Carvalho de Melo * Below are the definition of bit offsets for perf option, and works as 206c0afc57SArnaldo Carvalho de Melo * arbitrary values for all ETM versions. 216c0afc57SArnaldo Carvalho de Melo * 226c0afc57SArnaldo Carvalho de Melo * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore, 236c0afc57SArnaldo Carvalho de Melo * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and 246c0afc57SArnaldo Carvalho de Melo * directly use below macros as config bits. 256c0afc57SArnaldo Carvalho de Melo */ 26aca8af3cSJames Clark #define ETM_OPT_BRANCH_BROADCAST 8 2739ff5263SMathieu Poirier #define ETM_OPT_CYCACC 12 2882500a81SMathieu Poirier #define ETM_OPT_CTXTID 14 296c0afc57SArnaldo Carvalho de Melo #define ETM_OPT_CTXTID2 15 3039ff5263SMathieu Poirier #define ETM_OPT_TS 28 31b97971beSMike Leach #define ETM_OPT_RETSTK 29 3239ff5263SMathieu Poirier 33df770ff0SMike Leach /* ETMv4 CONFIGR programming bits for the ETM OPTs */ 34aca8af3cSJames Clark #define ETM4_CFG_BIT_BB 3 35df770ff0SMike Leach #define ETM4_CFG_BIT_CYCACC 4 3682500a81SMathieu Poirier #define ETM4_CFG_BIT_CTXTID 6 376c0afc57SArnaldo Carvalho de Melo #define ETM4_CFG_BIT_VMID 7 38df770ff0SMike Leach #define ETM4_CFG_BIT_TS 11 39df770ff0SMike Leach #define ETM4_CFG_BIT_RETSTK 12 406c0afc57SArnaldo Carvalho de Melo #define ETM4_CFG_BIT_VMID_OPT 15 41df770ff0SMike Leach 4239ff5263SMathieu Poirier static inline int coresight_get_trace_id(int cpu) 4339ff5263SMathieu Poirier { 4439ff5263SMathieu Poirier /* 4539ff5263SMathieu Poirier * A trace ID of value 0 is invalid, so let's start at some 4639ff5263SMathieu Poirier * random value that fits in 7 bits and go from there. Since 4739ff5263SMathieu Poirier * the common convention is to have data trace IDs be I(N) + 1, 4839ff5263SMathieu Poirier * set instruction trace IDs as a function of the CPU number. 4939ff5263SMathieu Poirier */ 5039ff5263SMathieu Poirier return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); 5139ff5263SMathieu Poirier } 5239ff5263SMathieu Poirier 5339ff5263SMathieu Poirier #endif 54