18a9fd832SMathieu Poirier /* SPDX-License-Identifier: GPL-2.0 */ 239ff5263SMathieu Poirier /* 339ff5263SMathieu Poirier * Copyright(C) 2015 Linaro Limited. All rights reserved. 439ff5263SMathieu Poirier * Author: Mathieu Poirier <mathieu.poirier@linaro.org> 539ff5263SMathieu Poirier */ 639ff5263SMathieu Poirier 739ff5263SMathieu Poirier #ifndef _LINUX_CORESIGHT_PMU_H 839ff5263SMathieu Poirier #define _LINUX_CORESIGHT_PMU_H 939ff5263SMathieu Poirier 1009277295SMike Leach #include <linux/bits.h> 1109277295SMike Leach 1239ff5263SMathieu Poirier #define CORESIGHT_ETM_PMU_NAME "cs_etm" 13e5fa5b41SMike Leach 14e5fa5b41SMike Leach /* 15e5fa5b41SMike Leach * The legacy Trace ID system based on fixed calculation from the cpu 16e5fa5b41SMike Leach * number. This has been replaced by drivers using a dynamic allocation 17e5fa5b41SMike Leach * system - but need to retain the legacy algorithm for backward comparibility 18e5fa5b41SMike Leach * in certain situations:- 19e5fa5b41SMike Leach * a) new perf running on older systems that generate the legacy mapping 20e5fa5b41SMike Leach * b) older tools that may not update at the same time as the kernel. 21e5fa5b41SMike Leach */ 22e5fa5b41SMike Leach #define CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) (0x10 + (cpu * 2)) 2339ff5263SMathieu Poirier 24e5fa5b41SMike Leach /* 256c0afc57SArnaldo Carvalho de Melo * Below are the definition of bit offsets for perf option, and works as 266c0afc57SArnaldo Carvalho de Melo * arbitrary values for all ETM versions. 276c0afc57SArnaldo Carvalho de Melo * 286c0afc57SArnaldo Carvalho de Melo * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore, 296c0afc57SArnaldo Carvalho de Melo * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and 306c0afc57SArnaldo Carvalho de Melo * directly use below macros as config bits. 316c0afc57SArnaldo Carvalho de Melo */ 32aca8af3cSJames Clark #define ETM_OPT_BRANCH_BROADCAST 8 3339ff5263SMathieu Poirier #define ETM_OPT_CYCACC 12 3482500a81SMathieu Poirier #define ETM_OPT_CTXTID 14 356c0afc57SArnaldo Carvalho de Melo #define ETM_OPT_CTXTID2 15 3639ff5263SMathieu Poirier #define ETM_OPT_TS 28 37b97971beSMike Leach #define ETM_OPT_RETSTK 29 3839ff5263SMathieu Poirier 39df770ff0SMike Leach /* ETMv4 CONFIGR programming bits for the ETM OPTs */ 40aca8af3cSJames Clark #define ETM4_CFG_BIT_BB 3 41df770ff0SMike Leach #define ETM4_CFG_BIT_CYCACC 4 4282500a81SMathieu Poirier #define ETM4_CFG_BIT_CTXTID 6 436c0afc57SArnaldo Carvalho de Melo #define ETM4_CFG_BIT_VMID 7 44df770ff0SMike Leach #define ETM4_CFG_BIT_TS 11 45df770ff0SMike Leach #define ETM4_CFG_BIT_RETSTK 12 466c0afc57SArnaldo Carvalho de Melo #define ETM4_CFG_BIT_VMID_OPT 15 47df770ff0SMike Leach 48b6521ea2SMike Leach /* 49b6521ea2SMike Leach * Interpretation of the PERF_RECORD_AUX_OUTPUT_HW_ID payload. 50b6521ea2SMike Leach * Used to associate a CPU with the CoreSight Trace ID. 51b6521ea2SMike Leach * [07:00] - Trace ID - uses 8 bits to make value easy to read in file. 52*1506af6dSJames Clark * [39:08] - Sink ID - as reported in /sys/bus/event_source/devices/cs_etm/sinks/ 53*1506af6dSJames Clark * Added in minor version 1. 54*1506af6dSJames Clark * [55:40] - Unused (SBZ) 55*1506af6dSJames Clark * [59:56] - Minor Version - previously existing fields are compatible with 56*1506af6dSJames Clark * all minor versions. 57*1506af6dSJames Clark * [63:60] - Major Version - previously existing fields mean different things 58*1506af6dSJames Clark * in new major versions. 59b6521ea2SMike Leach */ 60b6521ea2SMike Leach #define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0) 61*1506af6dSJames Clark #define CS_AUX_HW_ID_SINK_ID_MASK GENMASK_ULL(39, 8) 62b6521ea2SMike Leach 63*1506af6dSJames Clark #define CS_AUX_HW_ID_MINOR_VERSION_MASK GENMASK_ULL(59, 56) 64*1506af6dSJames Clark #define CS_AUX_HW_ID_MAJOR_VERSION_MASK GENMASK_ULL(63, 60) 65*1506af6dSJames Clark 66*1506af6dSJames Clark #define CS_AUX_HW_ID_MAJOR_VERSION 0 67*1506af6dSJames Clark #define CS_AUX_HW_ID_MINOR_VERSION 1 68b6521ea2SMike Leach 6939ff5263SMathieu Poirier #endif 70