1*1d50c772SHaibo Xu /* SPDX-License-Identifier: GPL-2.0-only */ 2*1d50c772SHaibo Xu #ifndef __ASM_VDSO_PROCESSOR_H 3*1d50c772SHaibo Xu #define __ASM_VDSO_PROCESSOR_H 4*1d50c772SHaibo Xu 5*1d50c772SHaibo Xu #ifndef __ASSEMBLY__ 6*1d50c772SHaibo Xu 7*1d50c772SHaibo Xu #include <asm-generic/barrier.h> 8*1d50c772SHaibo Xu cpu_relax(void)9*1d50c772SHaibo Xustatic inline void cpu_relax(void) 10*1d50c772SHaibo Xu { 11*1d50c772SHaibo Xu #ifdef __riscv_muldiv 12*1d50c772SHaibo Xu int dummy; 13*1d50c772SHaibo Xu /* In lieu of a halt instruction, induce a long-latency stall. */ 14*1d50c772SHaibo Xu __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); 15*1d50c772SHaibo Xu #endif 16*1d50c772SHaibo Xu 17*1d50c772SHaibo Xu #ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE 18*1d50c772SHaibo Xu /* 19*1d50c772SHaibo Xu * Reduce instruction retirement. 20*1d50c772SHaibo Xu * This assumes the PC changes. 21*1d50c772SHaibo Xu */ 22*1d50c772SHaibo Xu __asm__ __volatile__ ("pause"); 23*1d50c772SHaibo Xu #else 24*1d50c772SHaibo Xu /* Encoding of the pause instruction */ 25*1d50c772SHaibo Xu __asm__ __volatile__ (".4byte 0x100000F"); 26*1d50c772SHaibo Xu #endif 27*1d50c772SHaibo Xu barrier(); 28*1d50c772SHaibo Xu } 29*1d50c772SHaibo Xu 30*1d50c772SHaibo Xu #endif /* __ASSEMBLY__ */ 31*1d50c772SHaibo Xu 32*1d50c772SHaibo Xu #endif /* __ASM_VDSO_PROCESSOR_H */ 33