1 #ifndef _UAPI_ASM_POWERPC_PERF_REGS_H 2 #define _UAPI_ASM_POWERPC_PERF_REGS_H 3 4 enum perf_event_powerpc_regs { 5 PERF_REG_POWERPC_R0, 6 PERF_REG_POWERPC_R1, 7 PERF_REG_POWERPC_R2, 8 PERF_REG_POWERPC_R3, 9 PERF_REG_POWERPC_R4, 10 PERF_REG_POWERPC_R5, 11 PERF_REG_POWERPC_R6, 12 PERF_REG_POWERPC_R7, 13 PERF_REG_POWERPC_R8, 14 PERF_REG_POWERPC_R9, 15 PERF_REG_POWERPC_R10, 16 PERF_REG_POWERPC_R11, 17 PERF_REG_POWERPC_R12, 18 PERF_REG_POWERPC_R13, 19 PERF_REG_POWERPC_R14, 20 PERF_REG_POWERPC_R15, 21 PERF_REG_POWERPC_R16, 22 PERF_REG_POWERPC_R17, 23 PERF_REG_POWERPC_R18, 24 PERF_REG_POWERPC_R19, 25 PERF_REG_POWERPC_R20, 26 PERF_REG_POWERPC_R21, 27 PERF_REG_POWERPC_R22, 28 PERF_REG_POWERPC_R23, 29 PERF_REG_POWERPC_R24, 30 PERF_REG_POWERPC_R25, 31 PERF_REG_POWERPC_R26, 32 PERF_REG_POWERPC_R27, 33 PERF_REG_POWERPC_R28, 34 PERF_REG_POWERPC_R29, 35 PERF_REG_POWERPC_R30, 36 PERF_REG_POWERPC_R31, 37 PERF_REG_POWERPC_NIP, 38 PERF_REG_POWERPC_MSR, 39 PERF_REG_POWERPC_ORIG_R3, 40 PERF_REG_POWERPC_CTR, 41 PERF_REG_POWERPC_LINK, 42 PERF_REG_POWERPC_XER, 43 PERF_REG_POWERPC_CCR, 44 PERF_REG_POWERPC_SOFTE, 45 PERF_REG_POWERPC_TRAP, 46 PERF_REG_POWERPC_DAR, 47 PERF_REG_POWERPC_DSISR, 48 PERF_REG_POWERPC_MAX, 49 }; 50 #endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */ 51