1 /* 2 * intel_hdmi_lpe_audio.h - Intel HDMI LPE audio driver 3 * 4 * Copyright (C) 2016 Intel Corp 5 * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com> 6 * Ramesh Babu K V <ramesh.babu@intel.com> 7 * Vaibhav Agarwal <vaibhav.agarwal@intel.com> 8 * Jerome Anand <jerome.anand@intel.com> 9 * Aravind Siddappaji <aravindx.siddappaji@intel.com> 10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; version 2 of the License. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 22 */ 23 #ifndef __INTEL_HDMI_LPE_AUDIO_H 24 #define __INTEL_HDMI_LPE_AUDIO_H 25 26 #define HAD_MIN_CHANNEL 2 27 #define HAD_MAX_CHANNEL 8 28 #define HAD_NUM_OF_RING_BUFS 4 29 30 /* max 20bit address, aligned to 64 */ 31 #define HAD_MAX_BUFFER ((1024 * 1024 - 1) & ~0x3f) 32 #define HAD_DEFAULT_BUFFER (600 * 1024) /* default prealloc size */ 33 #define HAD_MAX_PERIODS 256 /* arbitrary, but should suffice */ 34 #define HAD_MIN_PERIODS 1 35 #define HAD_MAX_PERIOD_BYTES ((HAD_MAX_BUFFER / HAD_MIN_PERIODS) & ~0x3f) 36 #define HAD_MIN_PERIOD_BYTES 1024 /* might be smaller */ 37 #define HAD_FIFO_SIZE 0 /* fifo not being used */ 38 #define MAX_SPEAKERS 8 39 40 #define AUD_SAMPLE_RATE_32 32000 41 #define AUD_SAMPLE_RATE_44_1 44100 42 #define AUD_SAMPLE_RATE_48 48000 43 #define AUD_SAMPLE_RATE_88_2 88200 44 #define AUD_SAMPLE_RATE_96 96000 45 #define AUD_SAMPLE_RATE_176_4 176400 46 #define AUD_SAMPLE_RATE_192 192000 47 48 #define HAD_MIN_RATE AUD_SAMPLE_RATE_32 49 #define HAD_MAX_RATE AUD_SAMPLE_RATE_192 50 51 #define DIS_SAMPLE_RATE_25_2 25200 52 #define DIS_SAMPLE_RATE_27 27000 53 #define DIS_SAMPLE_RATE_54 54000 54 #define DIS_SAMPLE_RATE_74_25 74250 55 #define DIS_SAMPLE_RATE_148_5 148500 56 #define HAD_REG_WIDTH 0x08 57 #define HAD_MAX_DIP_WORDS 16 58 59 /* DP Link Rates */ 60 #define DP_2_7_GHZ 270000 61 #define DP_1_62_GHZ 162000 62 63 /* Maud Values */ 64 #define AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL 1988 65 #define AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL 2740 66 #define AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL 2982 67 #define AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL 5480 68 #define AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL 5965 69 #define AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL 10961 70 #define HAD_MAX_RATE_DP_2_7_MAUD_VAL 11930 71 #define AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL 3314 72 #define AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL 4567 73 #define AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL 4971 74 #define AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL 9134 75 #define AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL 9942 76 #define AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL 18268 77 #define HAD_MAX_RATE_DP_1_62_MAUD_VAL 19884 78 79 /* Naud Value */ 80 #define DP_NAUD_VAL 32768 81 82 /* HDMI Controller register offsets - audio domain common */ 83 /* Base address for below regs = 0x65000 */ 84 enum hdmi_ctrl_reg_offset_common { 85 AUDIO_HDMI_CONFIG_A = 0x000, 86 AUDIO_HDMI_CONFIG_B = 0x800, 87 AUDIO_HDMI_CONFIG_C = 0x900, 88 }; 89 /* HDMI controller register offsets */ 90 enum hdmi_ctrl_reg_offset { 91 AUD_CONFIG = 0x0, 92 AUD_CH_STATUS_0 = 0x08, 93 AUD_CH_STATUS_1 = 0x0C, 94 AUD_HDMI_CTS = 0x10, 95 AUD_N_ENABLE = 0x14, 96 AUD_SAMPLE_RATE = 0x18, 97 AUD_BUF_CONFIG = 0x20, 98 AUD_BUF_CH_SWAP = 0x24, 99 AUD_BUF_A_ADDR = 0x40, 100 AUD_BUF_A_LENGTH = 0x44, 101 AUD_BUF_B_ADDR = 0x48, 102 AUD_BUF_B_LENGTH = 0x4c, 103 AUD_BUF_C_ADDR = 0x50, 104 AUD_BUF_C_LENGTH = 0x54, 105 AUD_BUF_D_ADDR = 0x58, 106 AUD_BUF_D_LENGTH = 0x5c, 107 AUD_CNTL_ST = 0x60, 108 AUD_HDMI_STATUS = 0x64, /* v2 */ 109 AUD_HDMIW_INFOFR = 0x68, /* v2 */ 110 }; 111 112 /* Audio configuration */ 113 union aud_cfg { 114 struct { 115 u32 aud_en:1; 116 u32 layout:1; /* LAYOUT[01], see below */ 117 u32 fmt:2; 118 u32 num_ch:3; 119 u32 set:1; 120 u32 flat:1; 121 u32 val_bit:1; 122 u32 user_bit:1; 123 u32 underrun:1; /* 0: send null packets, 124 * 1: send silence stream 125 */ 126 u32 packet_mode:1; /* 0: 32bit container, 1: 16bit */ 127 u32 left_align:1; /* 0: MSB bits 0-23, 1: bits 8-31 */ 128 u32 bogus_sample:1; /* bogus sample for odd channels */ 129 u32 dp_modei:1; /* 0: HDMI, 1: DP */ 130 u32 rsvd:16; 131 } regx; 132 u32 regval; 133 }; 134 135 #define AUD_CONFIG_VALID_BIT (1 << 9) 136 #define AUD_CONFIG_DP_MODE (1 << 15) 137 #define AUD_CONFIG_CH_MASK 0x70 138 #define LAYOUT0 0 /* interleaved stereo */ 139 #define LAYOUT1 1 /* for channels > 2 */ 140 141 /* Audio Channel Status 0 Attributes */ 142 union aud_ch_status_0 { 143 struct { 144 u32 ch_status:1; 145 u32 lpcm_id:1; 146 u32 cp_info:1; 147 u32 format:3; 148 u32 mode:2; 149 u32 ctg_code:8; 150 u32 src_num:4; 151 u32 ch_num:4; 152 u32 samp_freq:4; /* CH_STATUS_MAP_XXX */ 153 u32 clk_acc:2; 154 u32 rsvd:2; 155 } regx; 156 u32 regval; 157 }; 158 159 /* samp_freq values - Sampling rate as per IEC60958 Ver 3 */ 160 #define CH_STATUS_MAP_32KHZ 0x3 161 #define CH_STATUS_MAP_44KHZ 0x0 162 #define CH_STATUS_MAP_48KHZ 0x2 163 #define CH_STATUS_MAP_88KHZ 0x8 164 #define CH_STATUS_MAP_96KHZ 0xA 165 #define CH_STATUS_MAP_176KHZ 0xC 166 #define CH_STATUS_MAP_192KHZ 0xE 167 168 /* Audio Channel Status 1 Attributes */ 169 union aud_ch_status_1 { 170 struct { 171 u32 max_wrd_len:1; 172 u32 wrd_len:3; 173 u32 rsvd:28; 174 } regx; 175 u32 regval; 176 }; 177 178 #define MAX_SMPL_WIDTH_20 0x0 179 #define MAX_SMPL_WIDTH_24 0x1 180 #define SMPL_WIDTH_16BITS 0x1 181 #define SMPL_WIDTH_24BITS 0x5 182 183 /* CTS register */ 184 union aud_hdmi_cts { 185 struct { 186 u32 cts_val:24; 187 u32 en_cts_prog:1; 188 u32 rsvd:7; 189 } regx; 190 u32 regval; 191 }; 192 193 /* N register */ 194 union aud_hdmi_n_enable { 195 struct { 196 u32 n_val:24; 197 u32 en_n_prog:1; 198 u32 rsvd:7; 199 } regx; 200 u32 regval; 201 }; 202 203 /* Audio Buffer configurations */ 204 union aud_buf_config { 205 struct { 206 u32 audio_fifo_watermark:8; 207 u32 dma_fifo_watermark:3; 208 u32 rsvd0:5; 209 u32 aud_delay:8; 210 u32 rsvd1:8; 211 } regx; 212 u32 regval; 213 }; 214 215 #define FIFO_THRESHOLD 0xFE 216 #define DMA_FIFO_THRESHOLD 0x7 217 218 /* Audio Sample Swapping offset */ 219 union aud_buf_ch_swap { 220 struct { 221 u32 first_0:3; 222 u32 second_0:3; 223 u32 first_1:3; 224 u32 second_1:3; 225 u32 first_2:3; 226 u32 second_2:3; 227 u32 first_3:3; 228 u32 second_3:3; 229 u32 rsvd:8; 230 } regx; 231 u32 regval; 232 }; 233 234 #define SWAP_LFE_CENTER 0x00fac4c8 /* octal 76543210 */ 235 236 /* Address for Audio Buffer */ 237 union aud_buf_addr { 238 struct { 239 u32 valid:1; 240 u32 intr_en:1; 241 u32 rsvd:4; 242 u32 addr:26; 243 } regx; 244 u32 regval; 245 }; 246 247 #define AUD_BUF_VALID (1U << 0) 248 #define AUD_BUF_INTR_EN (1U << 1) 249 250 /* Length of Audio Buffer */ 251 union aud_buf_len { 252 struct { 253 u32 buf_len:20; 254 u32 rsvd:12; 255 } regx; 256 u32 regval; 257 }; 258 259 /* Audio Control State Register offset */ 260 union aud_ctrl_st { 261 struct { 262 u32 ram_addr:4; 263 u32 eld_ack:1; 264 u32 eld_addr:4; 265 u32 eld_buf_size:5; 266 u32 eld_valid:1; 267 u32 cp_ready:1; 268 u32 dip_freq:2; 269 u32 dip_idx:3; 270 u32 dip_en_sta:4; 271 u32 rsvd:7; 272 } regx; 273 u32 regval; 274 }; 275 276 /* Audio HDMI Widget Data Island Packet offset */ 277 union aud_info_frame1 { 278 struct { 279 u32 pkt_type:8; 280 u32 ver_num:8; 281 u32 len:5; 282 u32 rsvd:11; 283 } regx; 284 u32 regval; 285 }; 286 287 #define HDMI_INFO_FRAME_WORD1 0x000a0184 288 #define DP_INFO_FRAME_WORD1 0x00441b84 289 290 /* DIP frame 2 */ 291 union aud_info_frame2 { 292 struct { 293 u32 chksum:8; 294 u32 chnl_cnt:3; 295 u32 rsvd0:1; 296 u32 coding_type:4; 297 u32 smpl_size:2; 298 u32 smpl_freq:3; 299 u32 rsvd1:3; 300 u32 format:8; 301 } regx; 302 u32 regval; 303 }; 304 305 /* DIP frame 3 */ 306 union aud_info_frame3 { 307 struct { 308 u32 chnl_alloc:8; 309 u32 rsvd0:3; 310 u32 lsv:4; 311 u32 dm_inh:1; 312 u32 rsvd1:16; 313 } regx; 314 u32 regval; 315 }; 316 317 #define VALID_DIP_WORDS 3 318 319 /* AUD_HDMI_STATUS bits */ 320 #define HDMI_AUDIO_UNDERRUN (1U << 31) 321 #define HDMI_AUDIO_BUFFER_DONE (1U << 29) 322 323 /* AUD_HDMI_STATUS register mask */ 324 #define AUD_HDMI_STATUS_MASK_UNDERRUN 0xC0000000 325 #define AUD_HDMI_STATUS_MASK_SRDBG 0x00000002 326 #define AUD_HDMI_STATUSG_MASK_FUNCRST 0x00000001 327 328 #endif 329