1287599cfSJerome Anand /* 2287599cfSJerome Anand * intel_hdmi_lpe_audio.h - Intel HDMI LPE audio driver 3287599cfSJerome Anand * 4287599cfSJerome Anand * Copyright (C) 2016 Intel Corp 5287599cfSJerome Anand * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com> 6287599cfSJerome Anand * Ramesh Babu K V <ramesh.babu@intel.com> 7287599cfSJerome Anand * Vaibhav Agarwal <vaibhav.agarwal@intel.com> 8287599cfSJerome Anand * Jerome Anand <jerome.anand@intel.com> 9287599cfSJerome Anand * Aravind Siddappaji <aravindx.siddappaji@intel.com> 10287599cfSJerome Anand * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11287599cfSJerome Anand * 12287599cfSJerome Anand * This program is free software; you can redistribute it and/or modify 13287599cfSJerome Anand * it under the terms of the GNU General Public License as published by 14287599cfSJerome Anand * the Free Software Foundation; version 2 of the License. 15287599cfSJerome Anand * 16287599cfSJerome Anand * This program is distributed in the hope that it will be useful, but 17287599cfSJerome Anand * WITHOUT ANY WARRANTY; without even the implied warranty of 18287599cfSJerome Anand * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19287599cfSJerome Anand * General Public License for more details. 20287599cfSJerome Anand * 21287599cfSJerome Anand * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 22287599cfSJerome Anand */ 23287599cfSJerome Anand #ifndef __INTEL_HDMI_LPE_AUDIO_H 24287599cfSJerome Anand #define __INTEL_HDMI_LPE_AUDIO_H 25287599cfSJerome Anand 26287599cfSJerome Anand #include <linux/types.h> 27287599cfSJerome Anand #include <sound/initval.h> 28287599cfSJerome Anand #include <linux/version.h> 29287599cfSJerome Anand #include <linux/pm_runtime.h> 30da864809STakashi Iwai #include <linux/platform_device.h> 31287599cfSJerome Anand #include <sound/asoundef.h> 32287599cfSJerome Anand #include <sound/control.h> 33287599cfSJerome Anand #include <sound/pcm.h> 34287599cfSJerome Anand 35964ca808SPierre-Louis Bossart #define AUD_CONFIG_VALID_BIT (1<<9) 36964ca808SPierre-Louis Bossart #define AUD_CONFIG_DP_MODE (1<<15) 37964ca808SPierre-Louis Bossart #define AUD_CONFIG_BLOCK_BIT (1<<7) 38964ca808SPierre-Louis Bossart 39287599cfSJerome Anand #define HMDI_LPE_AUDIO_DRIVER_NAME "intel-hdmi-lpe-audio" 40287599cfSJerome Anand #define HAD_MAX_DEVICES 1 41287599cfSJerome Anand #define HAD_MIN_CHANNEL 2 42287599cfSJerome Anand #define HAD_MAX_CHANNEL 8 43287599cfSJerome Anand #define HAD_NUM_OF_RING_BUFS 4 44287599cfSJerome Anand 45287599cfSJerome Anand /* Assume 192KHz, 8channel, 25msec period */ 46287599cfSJerome Anand #define HAD_MAX_BUFFER (600*1024) 47287599cfSJerome Anand #define HAD_MIN_BUFFER (32*1024) 48287599cfSJerome Anand #define HAD_MAX_PERIODS 4 49287599cfSJerome Anand #define HAD_MIN_PERIODS 4 50287599cfSJerome Anand #define HAD_MAX_PERIOD_BYTES (HAD_MAX_BUFFER/HAD_MIN_PERIODS) 51287599cfSJerome Anand #define HAD_MIN_PERIOD_BYTES 256 52287599cfSJerome Anand #define HAD_FIFO_SIZE 0 /* fifo not being used */ 53287599cfSJerome Anand #define MAX_SPEAKERS 8 54287599cfSJerome Anand 55287599cfSJerome Anand #define AUD_SAMPLE_RATE_32 32000 56287599cfSJerome Anand #define AUD_SAMPLE_RATE_44_1 44100 57287599cfSJerome Anand #define AUD_SAMPLE_RATE_48 48000 58287599cfSJerome Anand #define AUD_SAMPLE_RATE_88_2 88200 59287599cfSJerome Anand #define AUD_SAMPLE_RATE_96 96000 60287599cfSJerome Anand #define AUD_SAMPLE_RATE_176_4 176400 61287599cfSJerome Anand #define AUD_SAMPLE_RATE_192 192000 62287599cfSJerome Anand 63287599cfSJerome Anand #define HAD_MIN_RATE AUD_SAMPLE_RATE_32 64287599cfSJerome Anand #define HAD_MAX_RATE AUD_SAMPLE_RATE_192 65287599cfSJerome Anand 66287599cfSJerome Anand #define DIS_SAMPLE_RATE_25_2 25200 67287599cfSJerome Anand #define DIS_SAMPLE_RATE_27 27000 68287599cfSJerome Anand #define DIS_SAMPLE_RATE_54 54000 69287599cfSJerome Anand #define DIS_SAMPLE_RATE_74_25 74250 70287599cfSJerome Anand #define DIS_SAMPLE_RATE_148_5 148500 71287599cfSJerome Anand #define HAD_REG_WIDTH 0x08 72287599cfSJerome Anand #define HAD_MAX_HW_BUFS 0x04 73287599cfSJerome Anand #define HAD_MAX_DIP_WORDS 16 74287599cfSJerome Anand #define INTEL_HAD "IntelHdmiLpeAudio" 75287599cfSJerome Anand 76964ca808SPierre-Louis Bossart /* DP Link Rates */ 77964ca808SPierre-Louis Bossart #define DP_2_7_GHZ 270000 78964ca808SPierre-Louis Bossart #define DP_1_62_GHZ 162000 79964ca808SPierre-Louis Bossart 80964ca808SPierre-Louis Bossart /* Maud Values */ 81964ca808SPierre-Louis Bossart #define AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL 1988 82964ca808SPierre-Louis Bossart #define AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL 2740 83964ca808SPierre-Louis Bossart #define AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL 2982 84964ca808SPierre-Louis Bossart #define AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL 5480 85964ca808SPierre-Louis Bossart #define AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL 5965 86964ca808SPierre-Louis Bossart #define AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL 10961 87964ca808SPierre-Louis Bossart #define HAD_MAX_RATE_DP_2_7_MAUD_VAL 11930 88964ca808SPierre-Louis Bossart #define AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL 3314 89964ca808SPierre-Louis Bossart #define AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL 4567 90964ca808SPierre-Louis Bossart #define AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL 4971 91964ca808SPierre-Louis Bossart #define AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL 9134 92964ca808SPierre-Louis Bossart #define AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL 9942 93964ca808SPierre-Louis Bossart #define AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL 18268 94964ca808SPierre-Louis Bossart #define HAD_MAX_RATE_DP_1_62_MAUD_VAL 19884 95964ca808SPierre-Louis Bossart 96964ca808SPierre-Louis Bossart /* Naud Value */ 97964ca808SPierre-Louis Bossart #define DP_NAUD_VAL 32768 98964ca808SPierre-Louis Bossart 99287599cfSJerome Anand /* _AUD_CONFIG register MASK */ 100287599cfSJerome Anand #define AUD_CONFIG_MASK_UNDERRUN 0xC0000000 101287599cfSJerome Anand #define AUD_CONFIG_MASK_SRDBG 0x00000002 102287599cfSJerome Anand #define AUD_CONFIG_MASK_FUNCRST 0x00000001 103287599cfSJerome Anand 104287599cfSJerome Anand #define MAX_CNT 0xFF 105287599cfSJerome Anand #define HAD_SUSPEND_DELAY 1000 106287599cfSJerome Anand 107287599cfSJerome Anand enum had_drv_status { 108287599cfSJerome Anand HAD_DRV_CONNECTED, 109287599cfSJerome Anand HAD_DRV_RUNNING, 110287599cfSJerome Anand HAD_DRV_DISCONNECTED, 111287599cfSJerome Anand HAD_DRV_SUSPENDED, 112287599cfSJerome Anand HAD_DRV_ERR, 113287599cfSJerome Anand }; 114287599cfSJerome Anand 115287599cfSJerome Anand /* enum intel_had_aud_buf_type - HDMI controller ring buffer types */ 116287599cfSJerome Anand enum intel_had_aud_buf_type { 117287599cfSJerome Anand HAD_BUF_TYPE_A = 0, 118287599cfSJerome Anand HAD_BUF_TYPE_B = 1, 119287599cfSJerome Anand HAD_BUF_TYPE_C = 2, 120287599cfSJerome Anand HAD_BUF_TYPE_D = 3, 121287599cfSJerome Anand }; 122287599cfSJerome Anand 123287599cfSJerome Anand enum num_aud_ch { 124287599cfSJerome Anand CH_STEREO = 0, 125287599cfSJerome Anand CH_THREE_FOUR = 1, 126287599cfSJerome Anand CH_FIVE_SIX = 2, 127287599cfSJerome Anand CH_SEVEN_EIGHT = 3 128287599cfSJerome Anand }; 129287599cfSJerome Anand 130287599cfSJerome Anand /* HDMI Controller register offsets - audio domain common */ 131287599cfSJerome Anand /* Base address for below regs = 0x65000 */ 132287599cfSJerome Anand enum hdmi_ctrl_reg_offset_common { 133287599cfSJerome Anand AUDIO_HDMI_CONFIG_A = 0x000, 134287599cfSJerome Anand AUDIO_HDMI_CONFIG_B = 0x800, 135287599cfSJerome Anand AUDIO_HDMI_CONFIG_C = 0x900, 136287599cfSJerome Anand }; 137287599cfSJerome Anand /* HDMI controller register offsets */ 1384151ee84STakashi Iwai enum hdmi_ctrl_reg_offset { 139287599cfSJerome Anand AUD_CONFIG = 0x0, 140287599cfSJerome Anand AUD_CH_STATUS_0 = 0x08, 141287599cfSJerome Anand AUD_CH_STATUS_1 = 0x0C, 142287599cfSJerome Anand AUD_HDMI_CTS = 0x10, 143287599cfSJerome Anand AUD_N_ENABLE = 0x14, 144287599cfSJerome Anand AUD_SAMPLE_RATE = 0x18, 145287599cfSJerome Anand AUD_BUF_CONFIG = 0x20, 146287599cfSJerome Anand AUD_BUF_CH_SWAP = 0x24, 147287599cfSJerome Anand AUD_BUF_A_ADDR = 0x40, 148287599cfSJerome Anand AUD_BUF_A_LENGTH = 0x44, 149287599cfSJerome Anand AUD_BUF_B_ADDR = 0x48, 150287599cfSJerome Anand AUD_BUF_B_LENGTH = 0x4c, 151287599cfSJerome Anand AUD_BUF_C_ADDR = 0x50, 152287599cfSJerome Anand AUD_BUF_C_LENGTH = 0x54, 153287599cfSJerome Anand AUD_BUF_D_ADDR = 0x58, 154287599cfSJerome Anand AUD_BUF_D_LENGTH = 0x5c, 155287599cfSJerome Anand AUD_CNTL_ST = 0x60, 1564151ee84STakashi Iwai AUD_HDMI_STATUS = 0x64, /* v2 */ 1574151ee84STakashi Iwai AUD_HDMIW_INFOFR = 0x68, /* v2 */ 158287599cfSJerome Anand }; 159287599cfSJerome Anand 160287599cfSJerome Anand /* 161287599cfSJerome Anand * CEA speaker placement: 162287599cfSJerome Anand * 163287599cfSJerome Anand * FL FLC FC FRC FR 164287599cfSJerome Anand * 165287599cfSJerome Anand * LFE 166287599cfSJerome Anand * 167287599cfSJerome Anand * RL RLC RC RRC RR 168287599cfSJerome Anand * 169287599cfSJerome Anand * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M 170287599cfSJerome Anand * corresponds to CEA RL/RR; The SMPTE channel _assignment_ C/LFE is 171287599cfSJerome Anand * swapped to CEA LFE/FC. 172287599cfSJerome Anand */ 173287599cfSJerome Anand enum cea_speaker_placement { 174287599cfSJerome Anand FL = (1 << 0), /* Front Left */ 175287599cfSJerome Anand FC = (1 << 1), /* Front Center */ 176287599cfSJerome Anand FR = (1 << 2), /* Front Right */ 177287599cfSJerome Anand FLC = (1 << 3), /* Front Left Center */ 178287599cfSJerome Anand FRC = (1 << 4), /* Front Right Center */ 179287599cfSJerome Anand RL = (1 << 5), /* Rear Left */ 180287599cfSJerome Anand RC = (1 << 6), /* Rear Center */ 181287599cfSJerome Anand RR = (1 << 7), /* Rear Right */ 182287599cfSJerome Anand RLC = (1 << 8), /* Rear Left Center */ 183287599cfSJerome Anand RRC = (1 << 9), /* Rear Right Center */ 184287599cfSJerome Anand LFE = (1 << 10), /* Low Frequency Effect */ 185287599cfSJerome Anand }; 186287599cfSJerome Anand 187287599cfSJerome Anand struct cea_channel_speaker_allocation { 188287599cfSJerome Anand int ca_index; 189287599cfSJerome Anand int speakers[8]; 190287599cfSJerome Anand 191287599cfSJerome Anand /* derived values, just for convenience */ 192287599cfSJerome Anand int channels; 193287599cfSJerome Anand int spk_mask; 194287599cfSJerome Anand }; 195287599cfSJerome Anand 196287599cfSJerome Anand struct channel_map_table { 197287599cfSJerome Anand unsigned char map; /* ALSA API channel map position */ 198287599cfSJerome Anand unsigned char cea_slot; /* CEA slot value */ 199287599cfSJerome Anand int spk_mask; /* speaker position bit mask */ 200287599cfSJerome Anand }; 201287599cfSJerome Anand 202*7ceba75fSTakashi Iwai /* Audio configuration */ 203287599cfSJerome Anand union aud_cfg { 204287599cfSJerome Anand struct { 205287599cfSJerome Anand u32 aud_en:1; 206287599cfSJerome Anand u32 layout:1; 207287599cfSJerome Anand u32 fmt:2; 208287599cfSJerome Anand u32 num_ch:3; 209287599cfSJerome Anand u32 set:1; 210287599cfSJerome Anand u32 flat:1; 211287599cfSJerome Anand u32 val_bit:1; 212287599cfSJerome Anand u32 user_bit:1; 213287599cfSJerome Anand u32 underrun:1; 214287599cfSJerome Anand u32 packet_mode:1; 215287599cfSJerome Anand u32 left_align:1; 216287599cfSJerome Anand u32 bogus_sample:1; 217287599cfSJerome Anand u32 dp_modei:1; 218287599cfSJerome Anand u32 rsvd:16; 219*7ceba75fSTakashi Iwai } regx; 220*7ceba75fSTakashi Iwai u32 regval; 221287599cfSJerome Anand }; 222287599cfSJerome Anand 223*7ceba75fSTakashi Iwai /* Audio Channel Status 0 Attributes */ 224287599cfSJerome Anand union aud_ch_status_0 { 225287599cfSJerome Anand struct { 226287599cfSJerome Anand u32 ch_status:1; 227287599cfSJerome Anand u32 lpcm_id:1; 228287599cfSJerome Anand u32 cp_info:1; 229287599cfSJerome Anand u32 format:3; 230287599cfSJerome Anand u32 mode:2; 231287599cfSJerome Anand u32 ctg_code:8; 232287599cfSJerome Anand u32 src_num:4; 233287599cfSJerome Anand u32 ch_num:4; 234287599cfSJerome Anand u32 samp_freq:4; 235287599cfSJerome Anand u32 clk_acc:2; 236287599cfSJerome Anand u32 rsvd:2; 237*7ceba75fSTakashi Iwai } regx; 238*7ceba75fSTakashi Iwai u32 regval; 239287599cfSJerome Anand }; 240287599cfSJerome Anand 241*7ceba75fSTakashi Iwai /* Audio Channel Status 1 Attributes */ 242287599cfSJerome Anand union aud_ch_status_1 { 243287599cfSJerome Anand struct { 244287599cfSJerome Anand u32 max_wrd_len:1; 245287599cfSJerome Anand u32 wrd_len:3; 246287599cfSJerome Anand u32 rsvd:28; 247*7ceba75fSTakashi Iwai } regx; 248*7ceba75fSTakashi Iwai u32 regval; 249287599cfSJerome Anand }; 250287599cfSJerome Anand 251*7ceba75fSTakashi Iwai /* CTS register */ 252287599cfSJerome Anand union aud_hdmi_cts { 253287599cfSJerome Anand struct { 254287599cfSJerome Anand u32 cts_val:24; 255287599cfSJerome Anand u32 en_cts_prog:1; 256287599cfSJerome Anand u32 rsvd:7; 257*7ceba75fSTakashi Iwai } regx; 258*7ceba75fSTakashi Iwai u32 regval; 259287599cfSJerome Anand }; 260287599cfSJerome Anand 261*7ceba75fSTakashi Iwai /* N register */ 262287599cfSJerome Anand union aud_hdmi_n_enable { 263287599cfSJerome Anand struct { 264287599cfSJerome Anand u32 n_val:24; 265287599cfSJerome Anand u32 en_n_prog:1; 266287599cfSJerome Anand u32 rsvd:7; 267*7ceba75fSTakashi Iwai } regx; 268*7ceba75fSTakashi Iwai u32 regval; 269287599cfSJerome Anand }; 270287599cfSJerome Anand 271*7ceba75fSTakashi Iwai /* Audio Buffer configurations */ 272287599cfSJerome Anand union aud_buf_config { 273287599cfSJerome Anand struct { 274287599cfSJerome Anand u32 audio_fifo_watermark:8; 275287599cfSJerome Anand u32 dma_fifo_watermark:3; 276287599cfSJerome Anand u32 rsvd0:5; 277287599cfSJerome Anand u32 aud_delay:8; 278287599cfSJerome Anand u32 rsvd1:8; 279*7ceba75fSTakashi Iwai } regx; 280*7ceba75fSTakashi Iwai u32 regval; 281287599cfSJerome Anand }; 282287599cfSJerome Anand 283*7ceba75fSTakashi Iwai /* Audio Sample Swapping offset */ 284287599cfSJerome Anand union aud_buf_ch_swap { 285287599cfSJerome Anand struct { 286287599cfSJerome Anand u32 first_0:3; 287287599cfSJerome Anand u32 second_0:3; 288287599cfSJerome Anand u32 first_1:3; 289287599cfSJerome Anand u32 second_1:3; 290287599cfSJerome Anand u32 first_2:3; 291287599cfSJerome Anand u32 second_2:3; 292287599cfSJerome Anand u32 first_3:3; 293287599cfSJerome Anand u32 second_3:3; 294287599cfSJerome Anand u32 rsvd:8; 295*7ceba75fSTakashi Iwai } regx; 296*7ceba75fSTakashi Iwai u32 regval; 297287599cfSJerome Anand }; 298287599cfSJerome Anand 299*7ceba75fSTakashi Iwai /* Address for Audio Buffer */ 300287599cfSJerome Anand union aud_buf_addr { 301287599cfSJerome Anand struct { 302287599cfSJerome Anand u32 valid:1; 303287599cfSJerome Anand u32 intr_en:1; 304287599cfSJerome Anand u32 rsvd:4; 305287599cfSJerome Anand u32 addr:26; 306*7ceba75fSTakashi Iwai } regx; 307*7ceba75fSTakashi Iwai u32 regval; 308287599cfSJerome Anand }; 309287599cfSJerome Anand 310*7ceba75fSTakashi Iwai /* Length of Audio Buffer */ 311287599cfSJerome Anand union aud_buf_len { 312287599cfSJerome Anand struct { 313287599cfSJerome Anand u32 buf_len:20; 314287599cfSJerome Anand u32 rsvd:12; 315*7ceba75fSTakashi Iwai } regx; 316*7ceba75fSTakashi Iwai u32 regval; 317287599cfSJerome Anand }; 318287599cfSJerome Anand 319*7ceba75fSTakashi Iwai /* Audio Control State Register offset */ 320287599cfSJerome Anand union aud_ctrl_st { 321287599cfSJerome Anand struct { 322287599cfSJerome Anand u32 ram_addr:4; 323287599cfSJerome Anand u32 eld_ack:1; 324287599cfSJerome Anand u32 eld_addr:4; 325287599cfSJerome Anand u32 eld_buf_size:5; 326287599cfSJerome Anand u32 eld_valid:1; 327287599cfSJerome Anand u32 cp_ready:1; 328287599cfSJerome Anand u32 dip_freq:2; 329287599cfSJerome Anand u32 dip_idx:3; 330287599cfSJerome Anand u32 dip_en_sta:4; 331287599cfSJerome Anand u32 rsvd:7; 332*7ceba75fSTakashi Iwai } regx; 333*7ceba75fSTakashi Iwai u32 regval; 334287599cfSJerome Anand }; 335287599cfSJerome Anand 336*7ceba75fSTakashi Iwai /* Audio HDMI Widget Data Island Packet offset */ 337287599cfSJerome Anand union aud_info_frame1 { 338287599cfSJerome Anand struct { 339287599cfSJerome Anand u32 pkt_type:8; 340287599cfSJerome Anand u32 ver_num:8; 341287599cfSJerome Anand u32 len:5; 342287599cfSJerome Anand u32 rsvd:11; 343*7ceba75fSTakashi Iwai } regx; 344*7ceba75fSTakashi Iwai u32 regval; 345287599cfSJerome Anand }; 346287599cfSJerome Anand 347*7ceba75fSTakashi Iwai /* DIP frame 2 */ 348287599cfSJerome Anand union aud_info_frame2 { 349287599cfSJerome Anand struct { 350287599cfSJerome Anand u32 chksum:8; 351287599cfSJerome Anand u32 chnl_cnt:3; 352287599cfSJerome Anand u32 rsvd0:1; 353287599cfSJerome Anand u32 coding_type:4; 354287599cfSJerome Anand u32 smpl_size:2; 355287599cfSJerome Anand u32 smpl_freq:3; 356287599cfSJerome Anand u32 rsvd1:3; 357287599cfSJerome Anand u32 format:8; 358*7ceba75fSTakashi Iwai } regx; 359*7ceba75fSTakashi Iwai u32 regval; 360287599cfSJerome Anand }; 361287599cfSJerome Anand 362*7ceba75fSTakashi Iwai /* DIP frame 3 */ 363287599cfSJerome Anand union aud_info_frame3 { 364287599cfSJerome Anand struct { 365287599cfSJerome Anand u32 chnl_alloc:8; 366287599cfSJerome Anand u32 rsvd0:3; 367287599cfSJerome Anand u32 lsv:4; 368287599cfSJerome Anand u32 dm_inh:1; 369287599cfSJerome Anand u32 rsvd1:16; 370*7ceba75fSTakashi Iwai } regx; 371*7ceba75fSTakashi Iwai u32 regval; 372287599cfSJerome Anand }; 373287599cfSJerome Anand 374287599cfSJerome Anand #define HDMI_AUDIO_UNDERRUN (1UL<<31) 375287599cfSJerome Anand #define HDMI_AUDIO_BUFFER_DONE (1UL<<29) 376287599cfSJerome Anand 377287599cfSJerome Anand 378287599cfSJerome Anand #define PORT_ENABLE (1 << 31) 379287599cfSJerome Anand #define SDVO_AUDIO_ENABLE (1 << 6) 380287599cfSJerome Anand 381287599cfSJerome Anand enum had_caps_list { 382287599cfSJerome Anand HAD_GET_ELD = 1, 383287599cfSJerome Anand HAD_GET_DISPLAY_RATE, 384964ca808SPierre-Louis Bossart HAD_GET_DP_OUTPUT, 385964ca808SPierre-Louis Bossart HAD_GET_LINK_RATE, 386287599cfSJerome Anand HAD_SET_ENABLE_AUDIO, 387287599cfSJerome Anand HAD_SET_DISABLE_AUDIO, 388287599cfSJerome Anand HAD_SET_ENABLE_AUDIO_INT, 389287599cfSJerome Anand HAD_SET_DISABLE_AUDIO_INT, 390287599cfSJerome Anand }; 391287599cfSJerome Anand 392287599cfSJerome Anand enum had_event_type { 393287599cfSJerome Anand HAD_EVENT_HOT_PLUG = 1, 394287599cfSJerome Anand HAD_EVENT_HOT_UNPLUG, 395287599cfSJerome Anand HAD_EVENT_MODE_CHANGING, 396287599cfSJerome Anand HAD_EVENT_AUDIO_BUFFER_DONE, 397287599cfSJerome Anand HAD_EVENT_AUDIO_BUFFER_UNDERRUN, 398287599cfSJerome Anand HAD_EVENT_QUERY_IS_AUDIO_BUSY, 399287599cfSJerome Anand HAD_EVENT_QUERY_IS_AUDIO_SUSPENDED, 400287599cfSJerome Anand }; 401287599cfSJerome Anand 402287599cfSJerome Anand #endif 403