1 /* 2 * intel_hdmi_audio.c - Intel HDMI audio driver 3 * 4 * Copyright (C) 2016 Intel Corp 5 * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com> 6 * Ramesh Babu K V <ramesh.babu@intel.com> 7 * Vaibhav Agarwal <vaibhav.agarwal@intel.com> 8 * Jerome Anand <jerome.anand@intel.com> 9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; version 2 of the License. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 21 * ALSA driver for Intel HDMI audio 22 */ 23 24 #include <linux/types.h> 25 #include <linux/platform_device.h> 26 #include <linux/io.h> 27 #include <linux/slab.h> 28 #include <linux/module.h> 29 #include <linux/interrupt.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/delay.h> 33 #include <asm/set_memory.h> 34 #include <sound/core.h> 35 #include <sound/asoundef.h> 36 #include <sound/pcm.h> 37 #include <sound/pcm_params.h> 38 #include <sound/initval.h> 39 #include <sound/control.h> 40 #include <sound/jack.h> 41 #include <drm/drm_edid.h> 42 #include <drm/intel_lpe_audio.h> 43 #include "intel_hdmi_audio.h" 44 45 #define for_each_pipe(card_ctx, pipe) \ 46 for ((pipe) = 0; (pipe) < (card_ctx)->num_pipes; (pipe)++) 47 #define for_each_port(card_ctx, port) \ 48 for ((port) = 0; (port) < (card_ctx)->num_ports; (port)++) 49 50 /*standard module options for ALSA. This module supports only one card*/ 51 static int hdmi_card_index = SNDRV_DEFAULT_IDX1; 52 static char *hdmi_card_id = SNDRV_DEFAULT_STR1; 53 static bool single_port; 54 55 module_param_named(index, hdmi_card_index, int, 0444); 56 MODULE_PARM_DESC(index, 57 "Index value for INTEL Intel HDMI Audio controller."); 58 module_param_named(id, hdmi_card_id, charp, 0444); 59 MODULE_PARM_DESC(id, 60 "ID string for INTEL Intel HDMI Audio controller."); 61 module_param(single_port, bool, 0444); 62 MODULE_PARM_DESC(single_port, 63 "Single-port mode (for compatibility)"); 64 65 /* 66 * ELD SA bits in the CEA Speaker Allocation data block 67 */ 68 static const int eld_speaker_allocation_bits[] = { 69 [0] = FL | FR, 70 [1] = LFE, 71 [2] = FC, 72 [3] = RL | RR, 73 [4] = RC, 74 [5] = FLC | FRC, 75 [6] = RLC | RRC, 76 /* the following are not defined in ELD yet */ 77 [7] = 0, 78 }; 79 80 /* 81 * This is an ordered list! 82 * 83 * The preceding ones have better chances to be selected by 84 * hdmi_channel_allocation(). 85 */ 86 static struct cea_channel_speaker_allocation channel_allocations[] = { 87 /* channel: 7 6 5 4 3 2 1 0 */ 88 { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } }, 89 /* 2.1 */ 90 { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } }, 91 /* Dolby Surround */ 92 { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } }, 93 /* surround40 */ 94 { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, 95 /* surround41 */ 96 { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, 97 /* surround50 */ 98 { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, 99 /* surround51 */ 100 { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, 101 /* 6.1 */ 102 { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, 103 /* surround71 */ 104 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, 105 106 { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } }, 107 { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } }, 108 { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } }, 109 { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } }, 110 { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } }, 111 { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } }, 112 { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } }, 113 { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } }, 114 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } }, 115 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } }, 116 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } }, 117 { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } }, 118 { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } }, 119 { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } }, 120 { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } }, 121 { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } }, 122 { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } }, 123 { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } }, 124 { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } }, 125 { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } }, 126 { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } }, 127 { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } }, 128 { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } }, 129 }; 130 131 static const struct channel_map_table map_tables[] = { 132 { SNDRV_CHMAP_FL, 0x00, FL }, 133 { SNDRV_CHMAP_FR, 0x01, FR }, 134 { SNDRV_CHMAP_RL, 0x04, RL }, 135 { SNDRV_CHMAP_RR, 0x05, RR }, 136 { SNDRV_CHMAP_LFE, 0x02, LFE }, 137 { SNDRV_CHMAP_FC, 0x03, FC }, 138 { SNDRV_CHMAP_RLC, 0x06, RLC }, 139 { SNDRV_CHMAP_RRC, 0x07, RRC }, 140 {} /* terminator */ 141 }; 142 143 /* hardware capability structure */ 144 static const struct snd_pcm_hardware had_pcm_hardware = { 145 .info = (SNDRV_PCM_INFO_INTERLEAVED | 146 SNDRV_PCM_INFO_MMAP | 147 SNDRV_PCM_INFO_MMAP_VALID | 148 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), 149 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 150 SNDRV_PCM_FMTBIT_S24_LE | 151 SNDRV_PCM_FMTBIT_S32_LE), 152 .rates = SNDRV_PCM_RATE_32000 | 153 SNDRV_PCM_RATE_44100 | 154 SNDRV_PCM_RATE_48000 | 155 SNDRV_PCM_RATE_88200 | 156 SNDRV_PCM_RATE_96000 | 157 SNDRV_PCM_RATE_176400 | 158 SNDRV_PCM_RATE_192000, 159 .rate_min = HAD_MIN_RATE, 160 .rate_max = HAD_MAX_RATE, 161 .channels_min = HAD_MIN_CHANNEL, 162 .channels_max = HAD_MAX_CHANNEL, 163 .buffer_bytes_max = HAD_MAX_BUFFER, 164 .period_bytes_min = HAD_MIN_PERIOD_BYTES, 165 .period_bytes_max = HAD_MAX_PERIOD_BYTES, 166 .periods_min = HAD_MIN_PERIODS, 167 .periods_max = HAD_MAX_PERIODS, 168 .fifo_size = HAD_FIFO_SIZE, 169 }; 170 171 /* Get the active PCM substream; 172 * Call had_substream_put() for unreferecing. 173 * Don't call this inside had_spinlock, as it takes by itself 174 */ 175 static struct snd_pcm_substream * 176 had_substream_get(struct snd_intelhad *intelhaddata) 177 { 178 struct snd_pcm_substream *substream; 179 unsigned long flags; 180 181 spin_lock_irqsave(&intelhaddata->had_spinlock, flags); 182 substream = intelhaddata->stream_info.substream; 183 if (substream) 184 intelhaddata->stream_info.substream_refcount++; 185 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); 186 return substream; 187 } 188 189 /* Unref the active PCM substream; 190 * Don't call this inside had_spinlock, as it takes by itself 191 */ 192 static void had_substream_put(struct snd_intelhad *intelhaddata) 193 { 194 unsigned long flags; 195 196 spin_lock_irqsave(&intelhaddata->had_spinlock, flags); 197 intelhaddata->stream_info.substream_refcount--; 198 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); 199 } 200 201 static u32 had_config_offset(int pipe) 202 { 203 switch (pipe) { 204 default: 205 case 0: 206 return AUDIO_HDMI_CONFIG_A; 207 case 1: 208 return AUDIO_HDMI_CONFIG_B; 209 case 2: 210 return AUDIO_HDMI_CONFIG_C; 211 } 212 } 213 214 /* Register access functions */ 215 static u32 had_read_register_raw(struct snd_intelhad_card *card_ctx, 216 int pipe, u32 reg) 217 { 218 return ioread32(card_ctx->mmio_start + had_config_offset(pipe) + reg); 219 } 220 221 static void had_write_register_raw(struct snd_intelhad_card *card_ctx, 222 int pipe, u32 reg, u32 val) 223 { 224 iowrite32(val, card_ctx->mmio_start + had_config_offset(pipe) + reg); 225 } 226 227 static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val) 228 { 229 if (!ctx->connected) 230 *val = 0; 231 else 232 *val = had_read_register_raw(ctx->card_ctx, ctx->pipe, reg); 233 } 234 235 static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val) 236 { 237 if (ctx->connected) 238 had_write_register_raw(ctx->card_ctx, ctx->pipe, reg, val); 239 } 240 241 /* 242 * enable / disable audio configuration 243 * 244 * The normal read/modify should not directly be used on VLV2 for 245 * updating AUD_CONFIG register. 246 * This is because: 247 * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2 248 * HDMI IP. As a result a read-modify of AUD_CONFIG regiter will always 249 * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the 250 * register. This field should be 1xy binary for configuration with 6 or 251 * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio) 252 * causes the "channels" field to be updated as 0xy binary resulting in 253 * bad audio. The fix is to always write the AUD_CONFIG[6:4] with 254 * appropriate value when doing read-modify of AUD_CONFIG register. 255 */ 256 static void had_enable_audio(struct snd_intelhad *intelhaddata, 257 bool enable) 258 { 259 /* update the cached value */ 260 intelhaddata->aud_config.regx.aud_en = enable; 261 had_write_register(intelhaddata, AUD_CONFIG, 262 intelhaddata->aud_config.regval); 263 } 264 265 /* forcibly ACKs to both BUFFER_DONE and BUFFER_UNDERRUN interrupts */ 266 static void had_ack_irqs(struct snd_intelhad *ctx) 267 { 268 u32 status_reg; 269 270 if (!ctx->connected) 271 return; 272 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg); 273 status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN; 274 had_write_register(ctx, AUD_HDMI_STATUS, status_reg); 275 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg); 276 } 277 278 /* Reset buffer pointers */ 279 static void had_reset_audio(struct snd_intelhad *intelhaddata) 280 { 281 had_write_register(intelhaddata, AUD_HDMI_STATUS, 282 AUD_HDMI_STATUSG_MASK_FUNCRST); 283 had_write_register(intelhaddata, AUD_HDMI_STATUS, 0); 284 } 285 286 /* 287 * initialize audio channel status registers 288 * This function is called in the prepare callback 289 */ 290 static int had_prog_status_reg(struct snd_pcm_substream *substream, 291 struct snd_intelhad *intelhaddata) 292 { 293 union aud_cfg cfg_val = {.regval = 0}; 294 union aud_ch_status_0 ch_stat0 = {.regval = 0}; 295 union aud_ch_status_1 ch_stat1 = {.regval = 0}; 296 297 ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits & 298 IEC958_AES0_NONAUDIO) >> 1; 299 ch_stat0.regx.clk_acc = (intelhaddata->aes_bits & 300 IEC958_AES3_CON_CLOCK) >> 4; 301 cfg_val.regx.val_bit = ch_stat0.regx.lpcm_id; 302 303 switch (substream->runtime->rate) { 304 case AUD_SAMPLE_RATE_32: 305 ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ; 306 break; 307 308 case AUD_SAMPLE_RATE_44_1: 309 ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ; 310 break; 311 case AUD_SAMPLE_RATE_48: 312 ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ; 313 break; 314 case AUD_SAMPLE_RATE_88_2: 315 ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ; 316 break; 317 case AUD_SAMPLE_RATE_96: 318 ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ; 319 break; 320 case AUD_SAMPLE_RATE_176_4: 321 ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ; 322 break; 323 case AUD_SAMPLE_RATE_192: 324 ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ; 325 break; 326 327 default: 328 /* control should never come here */ 329 return -EINVAL; 330 } 331 332 had_write_register(intelhaddata, 333 AUD_CH_STATUS_0, ch_stat0.regval); 334 335 switch (substream->runtime->format) { 336 case SNDRV_PCM_FORMAT_S16_LE: 337 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20; 338 ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS; 339 break; 340 case SNDRV_PCM_FORMAT_S24_LE: 341 case SNDRV_PCM_FORMAT_S32_LE: 342 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24; 343 ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS; 344 break; 345 default: 346 return -EINVAL; 347 } 348 349 had_write_register(intelhaddata, 350 AUD_CH_STATUS_1, ch_stat1.regval); 351 return 0; 352 } 353 354 /* 355 * function to initialize audio 356 * registers and buffer confgiuration registers 357 * This function is called in the prepare callback 358 */ 359 static int had_init_audio_ctrl(struct snd_pcm_substream *substream, 360 struct snd_intelhad *intelhaddata) 361 { 362 union aud_cfg cfg_val = {.regval = 0}; 363 union aud_buf_config buf_cfg = {.regval = 0}; 364 u8 channels; 365 366 had_prog_status_reg(substream, intelhaddata); 367 368 buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD; 369 buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD; 370 buf_cfg.regx.aud_delay = 0; 371 had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval); 372 373 channels = substream->runtime->channels; 374 cfg_val.regx.num_ch = channels - 2; 375 if (channels <= 2) 376 cfg_val.regx.layout = LAYOUT0; 377 else 378 cfg_val.regx.layout = LAYOUT1; 379 380 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE) 381 cfg_val.regx.packet_mode = 1; 382 383 if (substream->runtime->format == SNDRV_PCM_FORMAT_S32_LE) 384 cfg_val.regx.left_align = 1; 385 386 cfg_val.regx.val_bit = 1; 387 388 /* fix up the DP bits */ 389 if (intelhaddata->dp_output) { 390 cfg_val.regx.dp_modei = 1; 391 cfg_val.regx.set = 1; 392 } 393 394 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval); 395 intelhaddata->aud_config = cfg_val; 396 return 0; 397 } 398 399 /* 400 * Compute derived values in channel_allocations[]. 401 */ 402 static void init_channel_allocations(void) 403 { 404 int i, j; 405 struct cea_channel_speaker_allocation *p; 406 407 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 408 p = channel_allocations + i; 409 p->channels = 0; 410 p->spk_mask = 0; 411 for (j = 0; j < ARRAY_SIZE(p->speakers); j++) 412 if (p->speakers[j]) { 413 p->channels++; 414 p->spk_mask |= p->speakers[j]; 415 } 416 } 417 } 418 419 /* 420 * The transformation takes two steps: 421 * 422 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask 423 * spk_mask => (channel_allocations[]) => ai->CA 424 * 425 * TODO: it could select the wrong CA from multiple candidates. 426 */ 427 static int had_channel_allocation(struct snd_intelhad *intelhaddata, 428 int channels) 429 { 430 int i; 431 int ca = 0; 432 int spk_mask = 0; 433 434 /* 435 * CA defaults to 0 for basic stereo audio 436 */ 437 if (channels <= 2) 438 return 0; 439 440 /* 441 * expand ELD's speaker allocation mask 442 * 443 * ELD tells the speaker mask in a compact(paired) form, 444 * expand ELD's notions to match the ones used by Audio InfoFrame. 445 */ 446 447 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { 448 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i)) 449 spk_mask |= eld_speaker_allocation_bits[i]; 450 } 451 452 /* search for the first working match in the CA table */ 453 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 454 if (channels == channel_allocations[i].channels && 455 (spk_mask & channel_allocations[i].spk_mask) == 456 channel_allocations[i].spk_mask) { 457 ca = channel_allocations[i].ca_index; 458 break; 459 } 460 } 461 462 dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels); 463 464 return ca; 465 } 466 467 /* from speaker bit mask to ALSA API channel position */ 468 static int spk_to_chmap(int spk) 469 { 470 const struct channel_map_table *t = map_tables; 471 472 for (; t->map; t++) { 473 if (t->spk_mask == spk) 474 return t->map; 475 } 476 return 0; 477 } 478 479 static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata) 480 { 481 int i, c; 482 int spk_mask = 0; 483 struct snd_pcm_chmap_elem *chmap; 484 u8 eld_high, eld_high_mask = 0xF0; 485 u8 high_msb; 486 487 kfree(intelhaddata->chmap->chmap); 488 intelhaddata->chmap->chmap = NULL; 489 490 chmap = kzalloc(sizeof(*chmap), GFP_KERNEL); 491 if (!chmap) 492 return; 493 494 dev_dbg(intelhaddata->dev, "eld speaker = %x\n", 495 intelhaddata->eld[DRM_ELD_SPEAKER]); 496 497 /* WA: Fix the max channel supported to 8 */ 498 499 /* 500 * Sink may support more than 8 channels, if eld_high has more than 501 * one bit set. SOC supports max 8 channels. 502 * Refer eld_speaker_allocation_bits, for sink speaker allocation 503 */ 504 505 /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */ 506 eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask; 507 if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) { 508 /* eld_high & (eld_high-1): if more than 1 bit set */ 509 /* 0x1F: 7 channels */ 510 for (i = 1; i < 4; i++) { 511 high_msb = eld_high & (0x80 >> i); 512 if (high_msb) { 513 intelhaddata->eld[DRM_ELD_SPEAKER] &= 514 high_msb | 0xF; 515 break; 516 } 517 } 518 } 519 520 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { 521 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i)) 522 spk_mask |= eld_speaker_allocation_bits[i]; 523 } 524 525 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 526 if (spk_mask == channel_allocations[i].spk_mask) { 527 for (c = 0; c < channel_allocations[i].channels; c++) { 528 chmap->map[c] = spk_to_chmap( 529 channel_allocations[i].speakers[ 530 (MAX_SPEAKERS - 1) - c]); 531 } 532 chmap->channels = channel_allocations[i].channels; 533 intelhaddata->chmap->chmap = chmap; 534 break; 535 } 536 } 537 if (i >= ARRAY_SIZE(channel_allocations)) 538 kfree(chmap); 539 } 540 541 /* 542 * ALSA API channel-map control callbacks 543 */ 544 static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol, 545 struct snd_ctl_elem_info *uinfo) 546 { 547 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 548 uinfo->count = HAD_MAX_CHANNEL; 549 uinfo->value.integer.min = 0; 550 uinfo->value.integer.max = SNDRV_CHMAP_LAST; 551 return 0; 552 } 553 554 static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol, 555 struct snd_ctl_elem_value *ucontrol) 556 { 557 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); 558 struct snd_intelhad *intelhaddata = info->private_data; 559 int i; 560 const struct snd_pcm_chmap_elem *chmap; 561 562 memset(ucontrol->value.integer.value, 0, 563 sizeof(long) * HAD_MAX_CHANNEL); 564 mutex_lock(&intelhaddata->mutex); 565 if (!intelhaddata->chmap->chmap) { 566 mutex_unlock(&intelhaddata->mutex); 567 return 0; 568 } 569 570 chmap = intelhaddata->chmap->chmap; 571 for (i = 0; i < chmap->channels; i++) 572 ucontrol->value.integer.value[i] = chmap->map[i]; 573 mutex_unlock(&intelhaddata->mutex); 574 575 return 0; 576 } 577 578 static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata, 579 struct snd_pcm *pcm) 580 { 581 int err; 582 583 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, 584 NULL, 0, (unsigned long)intelhaddata, 585 &intelhaddata->chmap); 586 if (err < 0) 587 return err; 588 589 intelhaddata->chmap->private_data = intelhaddata; 590 intelhaddata->chmap->kctl->info = had_chmap_ctl_info; 591 intelhaddata->chmap->kctl->get = had_chmap_ctl_get; 592 intelhaddata->chmap->chmap = NULL; 593 return 0; 594 } 595 596 /* 597 * Initialize Data Island Packets registers 598 * This function is called in the prepare callback 599 */ 600 static void had_prog_dip(struct snd_pcm_substream *substream, 601 struct snd_intelhad *intelhaddata) 602 { 603 int i; 604 union aud_ctrl_st ctrl_state = {.regval = 0}; 605 union aud_info_frame2 frame2 = {.regval = 0}; 606 union aud_info_frame3 frame3 = {.regval = 0}; 607 u8 checksum = 0; 608 u32 info_frame; 609 int channels; 610 int ca; 611 612 channels = substream->runtime->channels; 613 614 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval); 615 616 ca = had_channel_allocation(intelhaddata, channels); 617 if (intelhaddata->dp_output) { 618 info_frame = DP_INFO_FRAME_WORD1; 619 frame2.regval = (substream->runtime->channels - 1) | (ca << 24); 620 } else { 621 info_frame = HDMI_INFO_FRAME_WORD1; 622 frame2.regx.chnl_cnt = substream->runtime->channels - 1; 623 frame3.regx.chnl_alloc = ca; 624 625 /* Calculte the byte wide checksum for all valid DIP words */ 626 for (i = 0; i < BYTES_PER_WORD; i++) 627 checksum += (info_frame >> (i * 8)) & 0xff; 628 for (i = 0; i < BYTES_PER_WORD; i++) 629 checksum += (frame2.regval >> (i * 8)) & 0xff; 630 for (i = 0; i < BYTES_PER_WORD; i++) 631 checksum += (frame3.regval >> (i * 8)) & 0xff; 632 633 frame2.regx.chksum = -(checksum); 634 } 635 636 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame); 637 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval); 638 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval); 639 640 /* program remaining DIP words with zero */ 641 for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++) 642 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0); 643 644 ctrl_state.regx.dip_freq = 1; 645 ctrl_state.regx.dip_en_sta = 1; 646 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval); 647 } 648 649 static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate) 650 { 651 u32 maud_val; 652 653 /* Select maud according to DP 1.2 spec */ 654 if (link_rate == DP_2_7_GHZ) { 655 switch (aud_samp_freq) { 656 case AUD_SAMPLE_RATE_32: 657 maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL; 658 break; 659 660 case AUD_SAMPLE_RATE_44_1: 661 maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL; 662 break; 663 664 case AUD_SAMPLE_RATE_48: 665 maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL; 666 break; 667 668 case AUD_SAMPLE_RATE_88_2: 669 maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL; 670 break; 671 672 case AUD_SAMPLE_RATE_96: 673 maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL; 674 break; 675 676 case AUD_SAMPLE_RATE_176_4: 677 maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL; 678 break; 679 680 case HAD_MAX_RATE: 681 maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL; 682 break; 683 684 default: 685 maud_val = -EINVAL; 686 break; 687 } 688 } else if (link_rate == DP_1_62_GHZ) { 689 switch (aud_samp_freq) { 690 case AUD_SAMPLE_RATE_32: 691 maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL; 692 break; 693 694 case AUD_SAMPLE_RATE_44_1: 695 maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL; 696 break; 697 698 case AUD_SAMPLE_RATE_48: 699 maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL; 700 break; 701 702 case AUD_SAMPLE_RATE_88_2: 703 maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL; 704 break; 705 706 case AUD_SAMPLE_RATE_96: 707 maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL; 708 break; 709 710 case AUD_SAMPLE_RATE_176_4: 711 maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL; 712 break; 713 714 case HAD_MAX_RATE: 715 maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL; 716 break; 717 718 default: 719 maud_val = -EINVAL; 720 break; 721 } 722 } else 723 maud_val = -EINVAL; 724 725 return maud_val; 726 } 727 728 /* 729 * Program HDMI audio CTS value 730 * 731 * @aud_samp_freq: sampling frequency of audio data 732 * @tmds: sampling frequency of the display data 733 * @link_rate: DP link rate 734 * @n_param: N value, depends on aud_samp_freq 735 * @intelhaddata: substream private data 736 * 737 * Program CTS register based on the audio and display sampling frequency 738 */ 739 static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate, 740 u32 n_param, struct snd_intelhad *intelhaddata) 741 { 742 u32 cts_val; 743 u64 dividend, divisor; 744 745 if (intelhaddata->dp_output) { 746 /* Substitute cts_val with Maud according to DP 1.2 spec*/ 747 cts_val = had_calculate_maud_value(aud_samp_freq, link_rate); 748 } else { 749 /* Calculate CTS according to HDMI 1.3a spec*/ 750 dividend = (u64)tmds * n_param*1000; 751 divisor = 128 * aud_samp_freq; 752 cts_val = div64_u64(dividend, divisor); 753 } 754 dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n", 755 tmds, n_param, cts_val); 756 had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val)); 757 } 758 759 static int had_calculate_n_value(u32 aud_samp_freq) 760 { 761 int n_val; 762 763 /* Select N according to HDMI 1.3a spec*/ 764 switch (aud_samp_freq) { 765 case AUD_SAMPLE_RATE_32: 766 n_val = 4096; 767 break; 768 769 case AUD_SAMPLE_RATE_44_1: 770 n_val = 6272; 771 break; 772 773 case AUD_SAMPLE_RATE_48: 774 n_val = 6144; 775 break; 776 777 case AUD_SAMPLE_RATE_88_2: 778 n_val = 12544; 779 break; 780 781 case AUD_SAMPLE_RATE_96: 782 n_val = 12288; 783 break; 784 785 case AUD_SAMPLE_RATE_176_4: 786 n_val = 25088; 787 break; 788 789 case HAD_MAX_RATE: 790 n_val = 24576; 791 break; 792 793 default: 794 n_val = -EINVAL; 795 break; 796 } 797 return n_val; 798 } 799 800 /* 801 * Program HDMI audio N value 802 * 803 * @aud_samp_freq: sampling frequency of audio data 804 * @n_param: N value, depends on aud_samp_freq 805 * @intelhaddata: substream private data 806 * 807 * This function is called in the prepare callback. 808 * It programs based on the audio and display sampling frequency 809 */ 810 static int had_prog_n(u32 aud_samp_freq, u32 *n_param, 811 struct snd_intelhad *intelhaddata) 812 { 813 int n_val; 814 815 if (intelhaddata->dp_output) { 816 /* 817 * According to DP specs, Maud and Naud values hold 818 * a relationship, which is stated as: 819 * Maud/Naud = 512 * fs / f_LS_Clk 820 * where, fs is the sampling frequency of the audio stream 821 * and Naud is 32768 for Async clock. 822 */ 823 824 n_val = DP_NAUD_VAL; 825 } else 826 n_val = had_calculate_n_value(aud_samp_freq); 827 828 if (n_val < 0) 829 return n_val; 830 831 had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val)); 832 *n_param = n_val; 833 return 0; 834 } 835 836 /* 837 * PCM ring buffer handling 838 * 839 * The hardware provides a ring buffer with the fixed 4 buffer descriptors 840 * (BDs). The driver maps these 4 BDs onto the PCM ring buffer. The mapping 841 * moves at each period elapsed. The below illustrates how it works: 842 * 843 * At time=0 844 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 845 * BD | 0 | 1 | 2 | 3 | 846 * 847 * At time=1 (period elapsed) 848 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 849 * BD | 1 | 2 | 3 | 0 | 850 * 851 * At time=2 (second period elapsed) 852 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 853 * BD | 2 | 3 | 0 | 1 | 854 * 855 * The bd_head field points to the index of the BD to be read. It's also the 856 * position to be filled at next. The pcm_head and the pcm_filled fields 857 * point to the indices of the current position and of the next position to 858 * be filled, respectively. For PCM buffer there are both _head and _filled 859 * because they may be difference when nperiods > 4. For example, in the 860 * example above at t=1, bd_head=1 and pcm_head=1 while pcm_filled=5: 861 * 862 * pcm_head (=1) --v v-- pcm_filled (=5) 863 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 864 * BD | 1 | 2 | 3 | 0 | 865 * bd_head (=1) --^ ^-- next to fill (= bd_head) 866 * 867 * For nperiods < 4, the remaining BDs out of 4 are marked as invalid, so that 868 * the hardware skips those BDs in the loop. 869 * 870 * An exceptional setup is the case with nperiods=1. Since we have to update 871 * BDs after finishing one BD processing, we'd need at least two BDs, where 872 * both BDs point to the same content, the same address, the same size of the 873 * whole PCM buffer. 874 */ 875 876 #define AUD_BUF_ADDR(x) (AUD_BUF_A_ADDR + (x) * HAD_REG_WIDTH) 877 #define AUD_BUF_LEN(x) (AUD_BUF_A_LENGTH + (x) * HAD_REG_WIDTH) 878 879 /* Set up a buffer descriptor at the "filled" position */ 880 static void had_prog_bd(struct snd_pcm_substream *substream, 881 struct snd_intelhad *intelhaddata) 882 { 883 int idx = intelhaddata->bd_head; 884 int ofs = intelhaddata->pcmbuf_filled * intelhaddata->period_bytes; 885 u32 addr = substream->runtime->dma_addr + ofs; 886 887 addr |= AUD_BUF_VALID; 888 if (!substream->runtime->no_period_wakeup) 889 addr |= AUD_BUF_INTR_EN; 890 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), addr); 891 had_write_register(intelhaddata, AUD_BUF_LEN(idx), 892 intelhaddata->period_bytes); 893 894 /* advance the indices to the next */ 895 intelhaddata->bd_head++; 896 intelhaddata->bd_head %= intelhaddata->num_bds; 897 intelhaddata->pcmbuf_filled++; 898 intelhaddata->pcmbuf_filled %= substream->runtime->periods; 899 } 900 901 /* invalidate a buffer descriptor with the given index */ 902 static void had_invalidate_bd(struct snd_intelhad *intelhaddata, 903 int idx) 904 { 905 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), 0); 906 had_write_register(intelhaddata, AUD_BUF_LEN(idx), 0); 907 } 908 909 /* Initial programming of ring buffer */ 910 static void had_init_ringbuf(struct snd_pcm_substream *substream, 911 struct snd_intelhad *intelhaddata) 912 { 913 struct snd_pcm_runtime *runtime = substream->runtime; 914 int i, num_periods; 915 916 num_periods = runtime->periods; 917 intelhaddata->num_bds = min(num_periods, HAD_NUM_OF_RING_BUFS); 918 /* set the minimum 2 BDs for num_periods=1 */ 919 intelhaddata->num_bds = max(intelhaddata->num_bds, 2U); 920 intelhaddata->period_bytes = 921 frames_to_bytes(runtime, runtime->period_size); 922 WARN_ON(intelhaddata->period_bytes & 0x3f); 923 924 intelhaddata->bd_head = 0; 925 intelhaddata->pcmbuf_head = 0; 926 intelhaddata->pcmbuf_filled = 0; 927 928 for (i = 0; i < HAD_NUM_OF_RING_BUFS; i++) { 929 if (i < intelhaddata->num_bds) 930 had_prog_bd(substream, intelhaddata); 931 else /* invalidate the rest */ 932 had_invalidate_bd(intelhaddata, i); 933 } 934 935 intelhaddata->bd_head = 0; /* reset at head again before starting */ 936 } 937 938 /* process a bd, advance to the next */ 939 static void had_advance_ringbuf(struct snd_pcm_substream *substream, 940 struct snd_intelhad *intelhaddata) 941 { 942 int num_periods = substream->runtime->periods; 943 944 /* reprogram the next buffer */ 945 had_prog_bd(substream, intelhaddata); 946 947 /* proceed to next */ 948 intelhaddata->pcmbuf_head++; 949 intelhaddata->pcmbuf_head %= num_periods; 950 } 951 952 /* process the current BD(s); 953 * returns the current PCM buffer byte position, or -EPIPE for underrun. 954 */ 955 static int had_process_ringbuf(struct snd_pcm_substream *substream, 956 struct snd_intelhad *intelhaddata) 957 { 958 int len, processed; 959 unsigned long flags; 960 961 processed = 0; 962 spin_lock_irqsave(&intelhaddata->had_spinlock, flags); 963 for (;;) { 964 /* get the remaining bytes on the buffer */ 965 had_read_register(intelhaddata, 966 AUD_BUF_LEN(intelhaddata->bd_head), 967 &len); 968 if (len < 0 || len > intelhaddata->period_bytes) { 969 dev_dbg(intelhaddata->dev, "Invalid buf length %d\n", 970 len); 971 len = -EPIPE; 972 goto out; 973 } 974 975 if (len > 0) /* OK, this is the current buffer */ 976 break; 977 978 /* len=0 => already empty, check the next buffer */ 979 if (++processed >= intelhaddata->num_bds) { 980 len = -EPIPE; /* all empty? - report underrun */ 981 goto out; 982 } 983 had_advance_ringbuf(substream, intelhaddata); 984 } 985 986 len = intelhaddata->period_bytes - len; 987 len += intelhaddata->period_bytes * intelhaddata->pcmbuf_head; 988 out: 989 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); 990 return len; 991 } 992 993 /* called from irq handler */ 994 static void had_process_buffer_done(struct snd_intelhad *intelhaddata) 995 { 996 struct snd_pcm_substream *substream; 997 998 substream = had_substream_get(intelhaddata); 999 if (!substream) 1000 return; /* no stream? - bail out */ 1001 1002 if (!intelhaddata->connected) { 1003 snd_pcm_stop_xrun(substream); 1004 goto out; /* disconnected? - bail out */ 1005 } 1006 1007 /* process or stop the stream */ 1008 if (had_process_ringbuf(substream, intelhaddata) < 0) 1009 snd_pcm_stop_xrun(substream); 1010 else 1011 snd_pcm_period_elapsed(substream); 1012 1013 out: 1014 had_substream_put(intelhaddata); 1015 } 1016 1017 /* 1018 * The interrupt status 'sticky' bits might not be cleared by 1019 * setting '1' to that bit once... 1020 */ 1021 static void wait_clear_underrun_bit(struct snd_intelhad *intelhaddata) 1022 { 1023 int i; 1024 u32 val; 1025 1026 for (i = 0; i < 100; i++) { 1027 /* clear bit30, 31 AUD_HDMI_STATUS */ 1028 had_read_register(intelhaddata, AUD_HDMI_STATUS, &val); 1029 if (!(val & AUD_HDMI_STATUS_MASK_UNDERRUN)) 1030 return; 1031 udelay(100); 1032 cond_resched(); 1033 had_write_register(intelhaddata, AUD_HDMI_STATUS, val); 1034 } 1035 dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n"); 1036 } 1037 1038 /* Perform some reset procedure but only when need_reset is set; 1039 * this is called from prepare or hw_free callbacks once after trigger STOP 1040 * or underrun has been processed in order to settle down the h/w state. 1041 */ 1042 static void had_do_reset(struct snd_intelhad *intelhaddata) 1043 { 1044 if (!intelhaddata->need_reset || !intelhaddata->connected) 1045 return; 1046 1047 /* Reset buffer pointers */ 1048 had_reset_audio(intelhaddata); 1049 wait_clear_underrun_bit(intelhaddata); 1050 intelhaddata->need_reset = false; 1051 } 1052 1053 /* called from irq handler */ 1054 static void had_process_buffer_underrun(struct snd_intelhad *intelhaddata) 1055 { 1056 struct snd_pcm_substream *substream; 1057 1058 /* Report UNDERRUN error to above layers */ 1059 substream = had_substream_get(intelhaddata); 1060 if (substream) { 1061 snd_pcm_stop_xrun(substream); 1062 had_substream_put(intelhaddata); 1063 } 1064 intelhaddata->need_reset = true; 1065 } 1066 1067 /* 1068 * ALSA PCM open callback 1069 */ 1070 static int had_pcm_open(struct snd_pcm_substream *substream) 1071 { 1072 struct snd_intelhad *intelhaddata; 1073 struct snd_pcm_runtime *runtime; 1074 int retval; 1075 1076 intelhaddata = snd_pcm_substream_chip(substream); 1077 runtime = substream->runtime; 1078 1079 pm_runtime_get_sync(intelhaddata->dev); 1080 1081 /* set the runtime hw parameter with local snd_pcm_hardware struct */ 1082 runtime->hw = had_pcm_hardware; 1083 1084 retval = snd_pcm_hw_constraint_integer(runtime, 1085 SNDRV_PCM_HW_PARAM_PERIODS); 1086 if (retval < 0) 1087 goto error; 1088 1089 /* Make sure, that the period size is always aligned 1090 * 64byte boundary 1091 */ 1092 retval = snd_pcm_hw_constraint_step(substream->runtime, 0, 1093 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64); 1094 if (retval < 0) 1095 goto error; 1096 1097 retval = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 1098 if (retval < 0) 1099 goto error; 1100 1101 /* expose PCM substream */ 1102 spin_lock_irq(&intelhaddata->had_spinlock); 1103 intelhaddata->stream_info.substream = substream; 1104 intelhaddata->stream_info.substream_refcount++; 1105 spin_unlock_irq(&intelhaddata->had_spinlock); 1106 1107 return retval; 1108 error: 1109 pm_runtime_mark_last_busy(intelhaddata->dev); 1110 pm_runtime_put_autosuspend(intelhaddata->dev); 1111 return retval; 1112 } 1113 1114 /* 1115 * ALSA PCM close callback 1116 */ 1117 static int had_pcm_close(struct snd_pcm_substream *substream) 1118 { 1119 struct snd_intelhad *intelhaddata; 1120 1121 intelhaddata = snd_pcm_substream_chip(substream); 1122 1123 /* unreference and sync with the pending PCM accesses */ 1124 spin_lock_irq(&intelhaddata->had_spinlock); 1125 intelhaddata->stream_info.substream = NULL; 1126 intelhaddata->stream_info.substream_refcount--; 1127 while (intelhaddata->stream_info.substream_refcount > 0) { 1128 spin_unlock_irq(&intelhaddata->had_spinlock); 1129 cpu_relax(); 1130 spin_lock_irq(&intelhaddata->had_spinlock); 1131 } 1132 spin_unlock_irq(&intelhaddata->had_spinlock); 1133 1134 pm_runtime_mark_last_busy(intelhaddata->dev); 1135 pm_runtime_put_autosuspend(intelhaddata->dev); 1136 return 0; 1137 } 1138 1139 /* 1140 * ALSA PCM hw_params callback 1141 */ 1142 static int had_pcm_hw_params(struct snd_pcm_substream *substream, 1143 struct snd_pcm_hw_params *hw_params) 1144 { 1145 struct snd_intelhad *intelhaddata; 1146 unsigned long addr; 1147 int pages, buf_size, retval; 1148 1149 intelhaddata = snd_pcm_substream_chip(substream); 1150 buf_size = params_buffer_bytes(hw_params); 1151 retval = snd_pcm_lib_malloc_pages(substream, buf_size); 1152 if (retval < 0) 1153 return retval; 1154 dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n", 1155 __func__, buf_size); 1156 /* mark the pages as uncached region */ 1157 addr = (unsigned long) substream->runtime->dma_area; 1158 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) / PAGE_SIZE; 1159 retval = set_memory_uc(addr, pages); 1160 if (retval) { 1161 dev_err(intelhaddata->dev, "set_memory_uc failed.Error:%d\n", 1162 retval); 1163 return retval; 1164 } 1165 memset(substream->runtime->dma_area, 0, buf_size); 1166 1167 return retval; 1168 } 1169 1170 /* 1171 * ALSA PCM hw_free callback 1172 */ 1173 static int had_pcm_hw_free(struct snd_pcm_substream *substream) 1174 { 1175 struct snd_intelhad *intelhaddata; 1176 unsigned long addr; 1177 u32 pages; 1178 1179 intelhaddata = snd_pcm_substream_chip(substream); 1180 had_do_reset(intelhaddata); 1181 1182 /* mark back the pages as cached/writeback region before the free */ 1183 if (substream->runtime->dma_area != NULL) { 1184 addr = (unsigned long) substream->runtime->dma_area; 1185 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) / 1186 PAGE_SIZE; 1187 set_memory_wb(addr, pages); 1188 return snd_pcm_lib_free_pages(substream); 1189 } 1190 return 0; 1191 } 1192 1193 /* 1194 * ALSA PCM trigger callback 1195 */ 1196 static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1197 { 1198 int retval = 0; 1199 struct snd_intelhad *intelhaddata; 1200 1201 intelhaddata = snd_pcm_substream_chip(substream); 1202 1203 spin_lock(&intelhaddata->had_spinlock); 1204 switch (cmd) { 1205 case SNDRV_PCM_TRIGGER_START: 1206 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1207 case SNDRV_PCM_TRIGGER_RESUME: 1208 /* Enable Audio */ 1209 had_ack_irqs(intelhaddata); /* FIXME: do we need this? */ 1210 had_enable_audio(intelhaddata, true); 1211 break; 1212 1213 case SNDRV_PCM_TRIGGER_STOP: 1214 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1215 /* Disable Audio */ 1216 had_enable_audio(intelhaddata, false); 1217 intelhaddata->need_reset = true; 1218 break; 1219 1220 default: 1221 retval = -EINVAL; 1222 } 1223 spin_unlock(&intelhaddata->had_spinlock); 1224 return retval; 1225 } 1226 1227 /* 1228 * ALSA PCM prepare callback 1229 */ 1230 static int had_pcm_prepare(struct snd_pcm_substream *substream) 1231 { 1232 int retval; 1233 u32 disp_samp_freq, n_param; 1234 u32 link_rate = 0; 1235 struct snd_intelhad *intelhaddata; 1236 struct snd_pcm_runtime *runtime; 1237 1238 intelhaddata = snd_pcm_substream_chip(substream); 1239 runtime = substream->runtime; 1240 1241 dev_dbg(intelhaddata->dev, "period_size=%d\n", 1242 (int)frames_to_bytes(runtime, runtime->period_size)); 1243 dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods); 1244 dev_dbg(intelhaddata->dev, "buffer_size=%d\n", 1245 (int)snd_pcm_lib_buffer_bytes(substream)); 1246 dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate); 1247 dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels); 1248 1249 had_do_reset(intelhaddata); 1250 1251 /* Get N value in KHz */ 1252 disp_samp_freq = intelhaddata->tmds_clock_speed; 1253 1254 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata); 1255 if (retval) { 1256 dev_err(intelhaddata->dev, 1257 "programming N value failed %#x\n", retval); 1258 goto prep_end; 1259 } 1260 1261 if (intelhaddata->dp_output) 1262 link_rate = intelhaddata->link_rate; 1263 1264 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate, 1265 n_param, intelhaddata); 1266 1267 had_prog_dip(substream, intelhaddata); 1268 1269 retval = had_init_audio_ctrl(substream, intelhaddata); 1270 1271 /* Prog buffer address */ 1272 had_init_ringbuf(substream, intelhaddata); 1273 1274 /* 1275 * Program channel mapping in following order: 1276 * FL, FR, C, LFE, RL, RR 1277 */ 1278 1279 had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER); 1280 1281 prep_end: 1282 return retval; 1283 } 1284 1285 /* 1286 * ALSA PCM pointer callback 1287 */ 1288 static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream) 1289 { 1290 struct snd_intelhad *intelhaddata; 1291 int len; 1292 1293 intelhaddata = snd_pcm_substream_chip(substream); 1294 1295 if (!intelhaddata->connected) 1296 return SNDRV_PCM_POS_XRUN; 1297 1298 len = had_process_ringbuf(substream, intelhaddata); 1299 if (len < 0) 1300 return SNDRV_PCM_POS_XRUN; 1301 len = bytes_to_frames(substream->runtime, len); 1302 /* wrapping may happen when periods=1 */ 1303 len %= substream->runtime->buffer_size; 1304 return len; 1305 } 1306 1307 /* 1308 * ALSA PCM mmap callback 1309 */ 1310 static int had_pcm_mmap(struct snd_pcm_substream *substream, 1311 struct vm_area_struct *vma) 1312 { 1313 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1314 return remap_pfn_range(vma, vma->vm_start, 1315 substream->dma_buffer.addr >> PAGE_SHIFT, 1316 vma->vm_end - vma->vm_start, vma->vm_page_prot); 1317 } 1318 1319 /* 1320 * ALSA PCM ops 1321 */ 1322 static const struct snd_pcm_ops had_pcm_ops = { 1323 .open = had_pcm_open, 1324 .close = had_pcm_close, 1325 .ioctl = snd_pcm_lib_ioctl, 1326 .hw_params = had_pcm_hw_params, 1327 .hw_free = had_pcm_hw_free, 1328 .prepare = had_pcm_prepare, 1329 .trigger = had_pcm_trigger, 1330 .pointer = had_pcm_pointer, 1331 .mmap = had_pcm_mmap, 1332 }; 1333 1334 /* process mode change of the running stream; called in mutex */ 1335 static int had_process_mode_change(struct snd_intelhad *intelhaddata) 1336 { 1337 struct snd_pcm_substream *substream; 1338 int retval = 0; 1339 u32 disp_samp_freq, n_param; 1340 u32 link_rate = 0; 1341 1342 substream = had_substream_get(intelhaddata); 1343 if (!substream) 1344 return 0; 1345 1346 /* Disable Audio */ 1347 had_enable_audio(intelhaddata, false); 1348 1349 /* Update CTS value */ 1350 disp_samp_freq = intelhaddata->tmds_clock_speed; 1351 1352 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata); 1353 if (retval) { 1354 dev_err(intelhaddata->dev, 1355 "programming N value failed %#x\n", retval); 1356 goto out; 1357 } 1358 1359 if (intelhaddata->dp_output) 1360 link_rate = intelhaddata->link_rate; 1361 1362 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate, 1363 n_param, intelhaddata); 1364 1365 /* Enable Audio */ 1366 had_enable_audio(intelhaddata, true); 1367 1368 out: 1369 had_substream_put(intelhaddata); 1370 return retval; 1371 } 1372 1373 /* process hot plug, called from wq with mutex locked */ 1374 static void had_process_hot_plug(struct snd_intelhad *intelhaddata) 1375 { 1376 struct snd_pcm_substream *substream; 1377 1378 spin_lock_irq(&intelhaddata->had_spinlock); 1379 if (intelhaddata->connected) { 1380 dev_dbg(intelhaddata->dev, "Device already connected\n"); 1381 spin_unlock_irq(&intelhaddata->had_spinlock); 1382 return; 1383 } 1384 1385 /* Disable Audio */ 1386 had_enable_audio(intelhaddata, false); 1387 1388 intelhaddata->connected = true; 1389 dev_dbg(intelhaddata->dev, 1390 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n", 1391 __func__, __LINE__); 1392 spin_unlock_irq(&intelhaddata->had_spinlock); 1393 1394 had_build_channel_allocation_map(intelhaddata); 1395 1396 /* Report to above ALSA layer */ 1397 substream = had_substream_get(intelhaddata); 1398 if (substream) { 1399 snd_pcm_stop_xrun(substream); 1400 had_substream_put(intelhaddata); 1401 } 1402 1403 snd_jack_report(intelhaddata->jack, SND_JACK_AVOUT); 1404 } 1405 1406 /* process hot unplug, called from wq with mutex locked */ 1407 static void had_process_hot_unplug(struct snd_intelhad *intelhaddata) 1408 { 1409 struct snd_pcm_substream *substream; 1410 1411 spin_lock_irq(&intelhaddata->had_spinlock); 1412 if (!intelhaddata->connected) { 1413 dev_dbg(intelhaddata->dev, "Device already disconnected\n"); 1414 spin_unlock_irq(&intelhaddata->had_spinlock); 1415 return; 1416 1417 } 1418 1419 /* Disable Audio */ 1420 had_enable_audio(intelhaddata, false); 1421 1422 intelhaddata->connected = false; 1423 dev_dbg(intelhaddata->dev, 1424 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n", 1425 __func__, __LINE__); 1426 spin_unlock_irq(&intelhaddata->had_spinlock); 1427 1428 kfree(intelhaddata->chmap->chmap); 1429 intelhaddata->chmap->chmap = NULL; 1430 1431 /* Report to above ALSA layer */ 1432 substream = had_substream_get(intelhaddata); 1433 if (substream) { 1434 snd_pcm_stop_xrun(substream); 1435 had_substream_put(intelhaddata); 1436 } 1437 1438 snd_jack_report(intelhaddata->jack, 0); 1439 } 1440 1441 /* 1442 * ALSA iec958 and ELD controls 1443 */ 1444 1445 static int had_iec958_info(struct snd_kcontrol *kcontrol, 1446 struct snd_ctl_elem_info *uinfo) 1447 { 1448 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1449 uinfo->count = 1; 1450 return 0; 1451 } 1452 1453 static int had_iec958_get(struct snd_kcontrol *kcontrol, 1454 struct snd_ctl_elem_value *ucontrol) 1455 { 1456 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); 1457 1458 mutex_lock(&intelhaddata->mutex); 1459 ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff; 1460 ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff; 1461 ucontrol->value.iec958.status[2] = 1462 (intelhaddata->aes_bits >> 16) & 0xff; 1463 ucontrol->value.iec958.status[3] = 1464 (intelhaddata->aes_bits >> 24) & 0xff; 1465 mutex_unlock(&intelhaddata->mutex); 1466 return 0; 1467 } 1468 1469 static int had_iec958_mask_get(struct snd_kcontrol *kcontrol, 1470 struct snd_ctl_elem_value *ucontrol) 1471 { 1472 ucontrol->value.iec958.status[0] = 0xff; 1473 ucontrol->value.iec958.status[1] = 0xff; 1474 ucontrol->value.iec958.status[2] = 0xff; 1475 ucontrol->value.iec958.status[3] = 0xff; 1476 return 0; 1477 } 1478 1479 static int had_iec958_put(struct snd_kcontrol *kcontrol, 1480 struct snd_ctl_elem_value *ucontrol) 1481 { 1482 unsigned int val; 1483 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); 1484 int changed = 0; 1485 1486 val = (ucontrol->value.iec958.status[0] << 0) | 1487 (ucontrol->value.iec958.status[1] << 8) | 1488 (ucontrol->value.iec958.status[2] << 16) | 1489 (ucontrol->value.iec958.status[3] << 24); 1490 mutex_lock(&intelhaddata->mutex); 1491 if (intelhaddata->aes_bits != val) { 1492 intelhaddata->aes_bits = val; 1493 changed = 1; 1494 } 1495 mutex_unlock(&intelhaddata->mutex); 1496 return changed; 1497 } 1498 1499 static int had_ctl_eld_info(struct snd_kcontrol *kcontrol, 1500 struct snd_ctl_elem_info *uinfo) 1501 { 1502 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 1503 uinfo->count = HDMI_MAX_ELD_BYTES; 1504 return 0; 1505 } 1506 1507 static int had_ctl_eld_get(struct snd_kcontrol *kcontrol, 1508 struct snd_ctl_elem_value *ucontrol) 1509 { 1510 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); 1511 1512 mutex_lock(&intelhaddata->mutex); 1513 memcpy(ucontrol->value.bytes.data, intelhaddata->eld, 1514 HDMI_MAX_ELD_BYTES); 1515 mutex_unlock(&intelhaddata->mutex); 1516 return 0; 1517 } 1518 1519 static const struct snd_kcontrol_new had_controls[] = { 1520 { 1521 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1522 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1523 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK), 1524 .info = had_iec958_info, /* shared */ 1525 .get = had_iec958_mask_get, 1526 }, 1527 { 1528 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1529 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1530 .info = had_iec958_info, 1531 .get = had_iec958_get, 1532 .put = had_iec958_put, 1533 }, 1534 { 1535 .access = (SNDRV_CTL_ELEM_ACCESS_READ | 1536 SNDRV_CTL_ELEM_ACCESS_VOLATILE), 1537 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1538 .name = "ELD", 1539 .info = had_ctl_eld_info, 1540 .get = had_ctl_eld_get, 1541 }, 1542 }; 1543 1544 /* 1545 * audio interrupt handler 1546 */ 1547 static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id) 1548 { 1549 struct snd_intelhad_card *card_ctx = dev_id; 1550 u32 audio_stat[3] = {}; 1551 int pipe, port; 1552 1553 for_each_pipe(card_ctx, pipe) { 1554 /* use raw register access to ack IRQs even while disconnected */ 1555 audio_stat[pipe] = had_read_register_raw(card_ctx, pipe, 1556 AUD_HDMI_STATUS) & 1557 (HDMI_AUDIO_UNDERRUN | HDMI_AUDIO_BUFFER_DONE); 1558 1559 if (audio_stat[pipe]) 1560 had_write_register_raw(card_ctx, pipe, 1561 AUD_HDMI_STATUS, audio_stat[pipe]); 1562 } 1563 1564 for_each_port(card_ctx, port) { 1565 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1566 int pipe = ctx->pipe; 1567 1568 if (pipe < 0) 1569 continue; 1570 1571 if (audio_stat[pipe] & HDMI_AUDIO_BUFFER_DONE) 1572 had_process_buffer_done(ctx); 1573 if (audio_stat[pipe] & HDMI_AUDIO_UNDERRUN) 1574 had_process_buffer_underrun(ctx); 1575 } 1576 1577 return IRQ_HANDLED; 1578 } 1579 1580 /* 1581 * monitor plug/unplug notification from i915; just kick off the work 1582 */ 1583 static void notify_audio_lpe(struct platform_device *pdev, int port) 1584 { 1585 struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev); 1586 struct snd_intelhad *ctx; 1587 1588 ctx = &card_ctx->pcm_ctx[single_port ? 0 : port]; 1589 if (single_port) 1590 ctx->port = port; 1591 1592 schedule_work(&ctx->hdmi_audio_wq); 1593 } 1594 1595 /* the work to handle monitor hot plug/unplug */ 1596 static void had_audio_wq(struct work_struct *work) 1597 { 1598 struct snd_intelhad *ctx = 1599 container_of(work, struct snd_intelhad, hdmi_audio_wq); 1600 struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data; 1601 struct intel_hdmi_lpe_audio_port_pdata *ppdata = &pdata->port[ctx->port]; 1602 1603 pm_runtime_get_sync(ctx->dev); 1604 mutex_lock(&ctx->mutex); 1605 if (ppdata->pipe < 0) { 1606 dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG : port = %d\n", 1607 __func__, ctx->port); 1608 1609 memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */ 1610 1611 ctx->dp_output = false; 1612 ctx->tmds_clock_speed = 0; 1613 ctx->link_rate = 0; 1614 1615 /* Shut down the stream */ 1616 had_process_hot_unplug(ctx); 1617 1618 ctx->pipe = -1; 1619 } else { 1620 dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n", 1621 __func__, ctx->port, ppdata->ls_clock); 1622 1623 memcpy(ctx->eld, ppdata->eld, sizeof(ctx->eld)); 1624 1625 ctx->dp_output = ppdata->dp_output; 1626 if (ctx->dp_output) { 1627 ctx->tmds_clock_speed = 0; 1628 ctx->link_rate = ppdata->ls_clock; 1629 } else { 1630 ctx->tmds_clock_speed = ppdata->ls_clock; 1631 ctx->link_rate = 0; 1632 } 1633 1634 /* 1635 * Shut down the stream before we change 1636 * the pipe assignment for this pcm device 1637 */ 1638 had_process_hot_plug(ctx); 1639 1640 ctx->pipe = ppdata->pipe; 1641 1642 /* Restart the stream if necessary */ 1643 had_process_mode_change(ctx); 1644 } 1645 1646 mutex_unlock(&ctx->mutex); 1647 pm_runtime_mark_last_busy(ctx->dev); 1648 pm_runtime_put_autosuspend(ctx->dev); 1649 } 1650 1651 /* 1652 * Jack interface 1653 */ 1654 static int had_create_jack(struct snd_intelhad *ctx, 1655 struct snd_pcm *pcm) 1656 { 1657 char hdmi_str[32]; 1658 int err; 1659 1660 snprintf(hdmi_str, sizeof(hdmi_str), 1661 "HDMI/DP,pcm=%d", pcm->device); 1662 1663 err = snd_jack_new(ctx->card_ctx->card, hdmi_str, 1664 SND_JACK_AVOUT, &ctx->jack, 1665 true, false); 1666 if (err < 0) 1667 return err; 1668 ctx->jack->private_data = ctx; 1669 return 0; 1670 } 1671 1672 /* 1673 * PM callbacks 1674 */ 1675 1676 static int hdmi_lpe_audio_runtime_suspend(struct device *dev) 1677 { 1678 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev); 1679 int port; 1680 1681 for_each_port(card_ctx, port) { 1682 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1683 struct snd_pcm_substream *substream; 1684 1685 substream = had_substream_get(ctx); 1686 if (substream) { 1687 snd_pcm_suspend(substream); 1688 had_substream_put(ctx); 1689 } 1690 } 1691 1692 return 0; 1693 } 1694 1695 static int __maybe_unused hdmi_lpe_audio_suspend(struct device *dev) 1696 { 1697 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev); 1698 int err; 1699 1700 err = hdmi_lpe_audio_runtime_suspend(dev); 1701 if (!err) 1702 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D3hot); 1703 return err; 1704 } 1705 1706 static int hdmi_lpe_audio_runtime_resume(struct device *dev) 1707 { 1708 pm_runtime_mark_last_busy(dev); 1709 return 0; 1710 } 1711 1712 static int __maybe_unused hdmi_lpe_audio_resume(struct device *dev) 1713 { 1714 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev); 1715 1716 hdmi_lpe_audio_runtime_resume(dev); 1717 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D0); 1718 return 0; 1719 } 1720 1721 /* release resources */ 1722 static void hdmi_lpe_audio_free(struct snd_card *card) 1723 { 1724 struct snd_intelhad_card *card_ctx = card->private_data; 1725 struct intel_hdmi_lpe_audio_pdata *pdata = card_ctx->dev->platform_data; 1726 int port; 1727 1728 spin_lock_irq(&pdata->lpe_audio_slock); 1729 pdata->notify_audio_lpe = NULL; 1730 spin_unlock_irq(&pdata->lpe_audio_slock); 1731 1732 for_each_port(card_ctx, port) { 1733 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1734 1735 cancel_work_sync(&ctx->hdmi_audio_wq); 1736 } 1737 1738 if (card_ctx->mmio_start) 1739 iounmap(card_ctx->mmio_start); 1740 if (card_ctx->irq >= 0) 1741 free_irq(card_ctx->irq, card_ctx); 1742 } 1743 1744 /* 1745 * hdmi_lpe_audio_probe - start bridge with i915 1746 * 1747 * This function is called when the i915 driver creates the 1748 * hdmi-lpe-audio platform device. 1749 */ 1750 static int hdmi_lpe_audio_probe(struct platform_device *pdev) 1751 { 1752 struct snd_card *card; 1753 struct snd_intelhad_card *card_ctx; 1754 struct snd_intelhad *ctx; 1755 struct snd_pcm *pcm; 1756 struct intel_hdmi_lpe_audio_pdata *pdata; 1757 int irq; 1758 struct resource *res_mmio; 1759 int port, ret; 1760 1761 pdata = pdev->dev.platform_data; 1762 if (!pdata) { 1763 dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__); 1764 return -EINVAL; 1765 } 1766 1767 /* get resources */ 1768 irq = platform_get_irq(pdev, 0); 1769 if (irq < 0) { 1770 dev_err(&pdev->dev, "Could not get irq resource: %d\n", irq); 1771 return irq; 1772 } 1773 1774 res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1775 if (!res_mmio) { 1776 dev_err(&pdev->dev, "Could not get IO_MEM resources\n"); 1777 return -ENXIO; 1778 } 1779 1780 /* create a card instance with ALSA framework */ 1781 ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id, 1782 THIS_MODULE, sizeof(*card_ctx), &card); 1783 if (ret) 1784 return ret; 1785 1786 card_ctx = card->private_data; 1787 card_ctx->dev = &pdev->dev; 1788 card_ctx->card = card; 1789 strcpy(card->driver, INTEL_HAD); 1790 strcpy(card->shortname, "Intel HDMI/DP LPE Audio"); 1791 strcpy(card->longname, "Intel HDMI/DP LPE Audio"); 1792 1793 card_ctx->irq = -1; 1794 1795 card->private_free = hdmi_lpe_audio_free; 1796 1797 platform_set_drvdata(pdev, card_ctx); 1798 1799 card_ctx->num_pipes = pdata->num_pipes; 1800 card_ctx->num_ports = single_port ? 1 : pdata->num_ports; 1801 1802 for_each_port(card_ctx, port) { 1803 ctx = &card_ctx->pcm_ctx[port]; 1804 ctx->card_ctx = card_ctx; 1805 ctx->dev = card_ctx->dev; 1806 ctx->port = single_port ? -1 : port; 1807 ctx->pipe = -1; 1808 1809 spin_lock_init(&ctx->had_spinlock); 1810 mutex_init(&ctx->mutex); 1811 INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq); 1812 } 1813 1814 dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n", 1815 __func__, (unsigned int)res_mmio->start, 1816 (unsigned int)res_mmio->end); 1817 1818 card_ctx->mmio_start = ioremap_nocache(res_mmio->start, 1819 (size_t)(resource_size(res_mmio))); 1820 if (!card_ctx->mmio_start) { 1821 dev_err(&pdev->dev, "Could not get ioremap\n"); 1822 ret = -EACCES; 1823 goto err; 1824 } 1825 1826 /* setup interrupt handler */ 1827 ret = request_irq(irq, display_pipe_interrupt_handler, 0, 1828 pdev->name, card_ctx); 1829 if (ret < 0) { 1830 dev_err(&pdev->dev, "request_irq failed\n"); 1831 goto err; 1832 } 1833 1834 card_ctx->irq = irq; 1835 1836 /* only 32bit addressable */ 1837 dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 1838 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 1839 1840 init_channel_allocations(); 1841 1842 card_ctx->num_pipes = pdata->num_pipes; 1843 card_ctx->num_ports = single_port ? 1 : pdata->num_ports; 1844 1845 for_each_port(card_ctx, port) { 1846 int i; 1847 1848 ctx = &card_ctx->pcm_ctx[port]; 1849 ret = snd_pcm_new(card, INTEL_HAD, port, MAX_PB_STREAMS, 1850 MAX_CAP_STREAMS, &pcm); 1851 if (ret) 1852 goto err; 1853 1854 /* setup private data which can be retrieved when required */ 1855 pcm->private_data = ctx; 1856 pcm->info_flags = 0; 1857 strlcpy(pcm->name, card->shortname, strlen(card->shortname)); 1858 /* setup the ops for playabck */ 1859 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops); 1860 1861 /* allocate dma pages; 1862 * try to allocate 600k buffer as default which is large enough 1863 */ 1864 snd_pcm_lib_preallocate_pages_for_all(pcm, 1865 SNDRV_DMA_TYPE_DEV, NULL, 1866 HAD_DEFAULT_BUFFER, HAD_MAX_BUFFER); 1867 1868 /* create controls */ 1869 for (i = 0; i < ARRAY_SIZE(had_controls); i++) { 1870 struct snd_kcontrol *kctl; 1871 1872 kctl = snd_ctl_new1(&had_controls[i], ctx); 1873 if (!kctl) { 1874 ret = -ENOMEM; 1875 goto err; 1876 } 1877 1878 kctl->id.device = pcm->device; 1879 1880 ret = snd_ctl_add(card, kctl); 1881 if (ret < 0) 1882 goto err; 1883 } 1884 1885 /* Register channel map controls */ 1886 ret = had_register_chmap_ctls(ctx, pcm); 1887 if (ret < 0) 1888 goto err; 1889 1890 ret = had_create_jack(ctx, pcm); 1891 if (ret < 0) 1892 goto err; 1893 } 1894 1895 ret = snd_card_register(card); 1896 if (ret) 1897 goto err; 1898 1899 spin_lock_irq(&pdata->lpe_audio_slock); 1900 pdata->notify_audio_lpe = notify_audio_lpe; 1901 spin_unlock_irq(&pdata->lpe_audio_slock); 1902 1903 pm_runtime_use_autosuspend(&pdev->dev); 1904 pm_runtime_mark_last_busy(&pdev->dev); 1905 pm_runtime_set_active(&pdev->dev); 1906 1907 dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__); 1908 for_each_port(card_ctx, port) { 1909 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1910 1911 schedule_work(&ctx->hdmi_audio_wq); 1912 } 1913 1914 return 0; 1915 1916 err: 1917 snd_card_free(card); 1918 return ret; 1919 } 1920 1921 /* 1922 * hdmi_lpe_audio_remove - stop bridge with i915 1923 * 1924 * This function is called when the platform device is destroyed. 1925 */ 1926 static int hdmi_lpe_audio_remove(struct platform_device *pdev) 1927 { 1928 struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev); 1929 1930 snd_card_free(card_ctx->card); 1931 return 0; 1932 } 1933 1934 static const struct dev_pm_ops hdmi_lpe_audio_pm = { 1935 SET_SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume) 1936 SET_RUNTIME_PM_OPS(hdmi_lpe_audio_runtime_suspend, 1937 hdmi_lpe_audio_runtime_resume, NULL) 1938 }; 1939 1940 static struct platform_driver hdmi_lpe_audio_driver = { 1941 .driver = { 1942 .name = "hdmi-lpe-audio", 1943 .pm = &hdmi_lpe_audio_pm, 1944 }, 1945 .probe = hdmi_lpe_audio_probe, 1946 .remove = hdmi_lpe_audio_remove, 1947 }; 1948 1949 module_platform_driver(hdmi_lpe_audio_driver); 1950 MODULE_ALIAS("platform:hdmi_lpe_audio"); 1951 1952 MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>"); 1953 MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>"); 1954 MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>"); 1955 MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>"); 1956 MODULE_DESCRIPTION("Intel HDMI Audio driver"); 1957 MODULE_LICENSE("GPL v2"); 1958 MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}"); 1959