1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Socionext UniPhier AIO ALSA driver. 4 * 5 * Copyright (c) 2016-2018 Socionext Inc. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; version 2 10 * of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef SND_UNIPHIER_AIO_H__ 22 #define SND_UNIPHIER_AIO_H__ 23 24 #include <linux/spinlock.h> 25 #include <linux/types.h> 26 #include <sound/pcm.h> 27 #include <sound/soc.h> 28 #include <sound/soc-dai.h> 29 30 struct platform_device; 31 32 enum ID_PORT_TYPE { 33 PORT_TYPE_UNKNOWN, 34 PORT_TYPE_I2S, 35 PORT_TYPE_SPDIF, 36 PORT_TYPE_EVE, 37 PORT_TYPE_CONV, 38 }; 39 40 enum ID_PORT_DIR { 41 PORT_DIR_OUTPUT, 42 PORT_DIR_INPUT, 43 }; 44 45 enum IEC61937_PC { 46 IEC61937_PC_AC3 = 0x0001, 47 IEC61937_PC_PAUSE = 0x0003, 48 IEC61937_PC_MPA = 0x0004, 49 IEC61937_PC_MP3 = 0x0005, 50 IEC61937_PC_DTS1 = 0x000b, 51 IEC61937_PC_DTS2 = 0x000c, 52 IEC61937_PC_DTS3 = 0x000d, 53 IEC61937_PC_AAC = 0x0007, 54 }; 55 56 /* IEC61937 Repetition period of data-burst in IEC60958 frames */ 57 #define IEC61937_FRM_STR_AC3 1536 58 #define IEC61937_FRM_STR_MPA 1152 59 #define IEC61937_FRM_STR_MP3 1152 60 #define IEC61937_FRM_STR_DTS1 512 61 #define IEC61937_FRM_STR_DTS2 1024 62 #define IEC61937_FRM_STR_DTS3 2048 63 #define IEC61937_FRM_STR_AAC 1024 64 65 /* IEC61937 Repetition period of Pause data-burst in IEC60958 frames */ 66 #define IEC61937_FRM_PAU_AC3 3 67 #define IEC61937_FRM_PAU_MPA 32 68 #define IEC61937_FRM_PAU_MP3 32 69 #define IEC61937_FRM_PAU_DTS1 3 70 #define IEC61937_FRM_PAU_DTS2 3 71 #define IEC61937_FRM_PAU_DTS3 3 72 #define IEC61937_FRM_PAU_AAC 32 73 74 /* IEC61937 Pa and Pb */ 75 #define IEC61937_HEADER_SIGN 0x1f4e72f8 76 77 #define AUD_HW_PCMIN1 0 78 #define AUD_HW_PCMIN2 1 79 #define AUD_HW_PCMIN3 2 80 #define AUD_HW_IECIN1 3 81 #define AUD_HW_DIECIN1 4 82 83 #define AUD_NAME_PCMIN1 "aio-pcmin1" 84 #define AUD_NAME_PCMIN2 "aio-pcmin2" 85 #define AUD_NAME_PCMIN3 "aio-pcmin3" 86 #define AUD_NAME_IECIN1 "aio-iecin1" 87 #define AUD_NAME_DIECIN1 "aio-diecin1" 88 89 #define AUD_HW_HPCMOUT1 0 90 #define AUD_HW_PCMOUT1 1 91 #define AUD_HW_PCMOUT2 2 92 #define AUD_HW_PCMOUT3 3 93 #define AUD_HW_EPCMOUT1 4 94 #define AUD_HW_EPCMOUT2 5 95 #define AUD_HW_EPCMOUT3 6 96 #define AUD_HW_EPCMOUT6 9 97 #define AUD_HW_HIECOUT1 10 98 #define AUD_HW_IECOUT1 11 99 #define AUD_HW_CMASTER 31 100 101 #define AUD_NAME_HPCMOUT1 "aio-hpcmout1" 102 #define AUD_NAME_PCMOUT1 "aio-pcmout1" 103 #define AUD_NAME_PCMOUT2 "aio-pcmout2" 104 #define AUD_NAME_PCMOUT3 "aio-pcmout3" 105 #define AUD_NAME_EPCMOUT1 "aio-epcmout1" 106 #define AUD_NAME_EPCMOUT2 "aio-epcmout2" 107 #define AUD_NAME_EPCMOUT3 "aio-epcmout3" 108 #define AUD_NAME_EPCMOUT6 "aio-epcmout6" 109 #define AUD_NAME_HIECOUT1 "aio-hiecout1" 110 #define AUD_NAME_IECOUT1 "aio-iecout1" 111 #define AUD_NAME_CMASTER "aio-cmaster" 112 #define AUD_NAME_HIECCOMPOUT1 "aio-hieccompout1" 113 114 #define AUD_GNAME_HDMI "aio-hdmi" 115 #define AUD_GNAME_LINE "aio-line" 116 #define AUD_GNAME_IEC "aio-iec" 117 118 #define AUD_CLK_IO 0 119 #define AUD_CLK_A1 1 120 #define AUD_CLK_F1 2 121 #define AUD_CLK_A2 3 122 #define AUD_CLK_F2 4 123 #define AUD_CLK_A 5 124 #define AUD_CLK_F 6 125 #define AUD_CLK_APLL 7 126 #define AUD_CLK_RX0 8 127 #define AUD_CLK_USB0 9 128 #define AUD_CLK_HSC0 10 129 130 #define AUD_PLL_A1 0 131 #define AUD_PLL_F1 1 132 #define AUD_PLL_A2 2 133 #define AUD_PLL_F2 3 134 #define AUD_PLL_APLL 4 135 #define AUD_PLL_RX0 5 136 #define AUD_PLL_USB0 6 137 #define AUD_PLL_HSC0 7 138 139 #define AUD_PLLDIV_1_2 0 140 #define AUD_PLLDIV_1_3 1 141 #define AUD_PLLDIV_1_1 2 142 #define AUD_PLLDIV_2_3 3 143 144 #define AUD_RING_SIZE (128 * 1024) 145 146 #define AUD_MIN_FRAGMENT 4 147 #define AUD_MAX_FRAGMENT 8 148 #define AUD_MIN_FRAGMENT_SIZE (4 * 1024) 149 #define AUD_MAX_FRAGMENT_SIZE (16 * 1024) 150 151 /* 152 * This is a selector for virtual register map of AIO. 153 * 154 * map: Specify the index of virtual register map. 155 * hw : Specify the ID of real register map, selector uses this value. 156 * A meaning of this value depends specification of SoC. 157 */ 158 struct uniphier_aio_selector { 159 int map; 160 int hw; 161 }; 162 163 /** 164 * 'SoftWare MAPping' setting of UniPhier AIO registers. 165 * 166 * We have to setup 'virtual' register maps to access 'real' registers of AIO. 167 * This feature is legacy and meaningless but AIO needs this to work. 168 * 169 * Each hardware blocks have own virtual register maps as following: 170 * 171 * Address Virtual Real 172 * ------- --------- --------------- 173 * 0x12000 DMAC map0 --> [selector] --> DMAC hardware 3 174 * 0x12080 DMAC map1 --> [selector] --> DMAC hardware 1 175 * ... 176 * 0x42000 Port map0 --> [selector] --> Port hardware 1 177 * 0x42400 Port map1 --> [selector] --> Port hardware 2 178 * ... 179 * 180 * ch : Input or output channel of DMAC 181 * rb : Ring buffer 182 * iport: PCM input port 183 * iif : Input interface 184 * oport: PCM output port 185 * oif : Output interface 186 * och : Output channel of DMAC for sampling rate converter 187 * 188 * These are examples for sound data paths: 189 * 190 * For caputure device: 191 * (outer of AIO) -> iport -> iif -> ch -> rb -> (CPU) 192 * For playback device: 193 * (CPU) -> rb -> ch -> oif -> oport -> (outer of AIO) 194 * For sampling rate converter device: 195 * (CPU) -> rb -> ch -> oif -> (HW SRC) -> iif -> och -> orb -> (CPU) 196 */ 197 struct uniphier_aio_swmap { 198 int type; 199 int dir; 200 201 struct uniphier_aio_selector ch; 202 struct uniphier_aio_selector rb; 203 struct uniphier_aio_selector iport; 204 struct uniphier_aio_selector iif; 205 struct uniphier_aio_selector oport; 206 struct uniphier_aio_selector oif; 207 struct uniphier_aio_selector och; 208 }; 209 210 struct uniphier_aio_spec { 211 const char *name; 212 const char *gname; 213 struct uniphier_aio_swmap swm; 214 }; 215 216 struct uniphier_aio_pll { 217 bool enable; 218 unsigned int freq; 219 }; 220 221 struct uniphier_aio_chip_spec { 222 const struct uniphier_aio_spec *specs; 223 int num_specs; 224 const struct uniphier_aio_pll *plls; 225 int num_plls; 226 struct snd_soc_dai_driver *dais; 227 int num_dais; 228 229 /* DMA access mode, this is workaround for DMA hungup */ 230 int addr_ext; 231 }; 232 233 struct uniphier_aio_sub { 234 struct uniphier_aio *aio; 235 236 /* Guard sub->rd_offs and wr_offs from IRQ handler. */ 237 spinlock_t lock; 238 239 const struct uniphier_aio_swmap *swm; 240 const struct uniphier_aio_spec *spec; 241 242 /* For PCM audio */ 243 struct snd_pcm_substream *substream; 244 struct snd_pcm_hw_params params; 245 246 /* For compress audio */ 247 struct snd_compr_stream *cstream; 248 struct snd_compr_params cparams; 249 unsigned char *compr_area; 250 dma_addr_t compr_addr; 251 size_t compr_bytes; 252 int pass_through; 253 enum IEC61937_PC iec_pc; 254 bool iec_header; 255 256 /* Both PCM and compress audio */ 257 bool use_mmap; 258 int setting; 259 int running; 260 u64 rd_offs; 261 u64 wr_offs; 262 u32 threshold; 263 u64 rd_org; 264 u64 wr_org; 265 u64 rd_total; 266 u64 wr_total; 267 }; 268 269 struct uniphier_aio { 270 struct uniphier_aio_chip *chip; 271 272 struct uniphier_aio_sub sub[2]; 273 274 unsigned int fmt; 275 /* Set one of AUD_CLK_X */ 276 int clk_in; 277 int clk_out; 278 /* Set one of AUD_PLL_X */ 279 int pll_in; 280 int pll_out; 281 /* Set one of AUD_PLLDIV_X */ 282 int plldiv; 283 }; 284 285 struct uniphier_aio_chip { 286 struct platform_device *pdev; 287 const struct uniphier_aio_chip_spec *chip_spec; 288 289 struct uniphier_aio *aios; 290 int num_aios; 291 struct uniphier_aio_pll *plls; 292 int num_plls; 293 294 struct clk *clk; 295 struct reset_control *rst; 296 struct regmap *regmap; 297 int active; 298 }; 299 300 static inline struct uniphier_aio *uniphier_priv(struct snd_soc_dai *dai) 301 { 302 struct uniphier_aio_chip *chip = snd_soc_dai_get_drvdata(dai); 303 304 return &chip->aios[dai->id]; 305 } 306 307 int uniphier_aiodma_soc_register_platform(struct platform_device *pdev); 308 extern const struct snd_compr_ops uniphier_aio_compr_ops; 309 310 int uniphier_aio_dai_probe(struct snd_soc_dai *dai); 311 int uniphier_aio_dai_remove(struct snd_soc_dai *dai); 312 int uniphier_aio_dai_suspend(struct snd_soc_dai *dai); 313 int uniphier_aio_dai_resume(struct snd_soc_dai *dai); 314 int uniphier_aio_probe(struct platform_device *pdev); 315 int uniphier_aio_remove(struct platform_device *pdev); 316 extern const struct snd_soc_dai_ops uniphier_aio_i2s_ops; 317 extern const struct snd_soc_dai_ops uniphier_aio_spdif_ops; 318 319 u64 aio_rb_cnt(struct uniphier_aio_sub *sub); 320 u64 aio_rbt_cnt_to_end(struct uniphier_aio_sub *sub); 321 u64 aio_rb_space(struct uniphier_aio_sub *sub); 322 u64 aio_rb_space_to_end(struct uniphier_aio_sub *sub); 323 324 int aio_chip_set_pll(struct uniphier_aio_chip *chip, int pll_id, 325 unsigned int freq); 326 void aio_chip_init(struct uniphier_aio_chip *chip); 327 int aio_init(struct uniphier_aio_sub *sub); 328 void aio_port_reset(struct uniphier_aio_sub *sub); 329 int aio_port_set_rate(struct uniphier_aio_sub *sub, int rate); 330 int aio_port_set_fmt(struct uniphier_aio_sub *sub); 331 int aio_port_set_clk(struct uniphier_aio_sub *sub); 332 int aio_port_set_param(struct uniphier_aio_sub *sub, int pass_through, 333 const struct snd_pcm_hw_params *params); 334 void aio_port_set_enable(struct uniphier_aio_sub *sub, int enable); 335 int aio_if_set_param(struct uniphier_aio_sub *sub, int pass_through); 336 int aio_oport_set_stream_type(struct uniphier_aio_sub *sub, 337 enum IEC61937_PC pc); 338 void aio_src_reset(struct uniphier_aio_sub *sub); 339 int aio_src_set_param(struct uniphier_aio_sub *sub, 340 const struct snd_pcm_hw_params *params); 341 int aio_srcif_set_param(struct uniphier_aio_sub *sub); 342 int aio_srcch_set_param(struct uniphier_aio_sub *sub); 343 void aio_srcch_set_enable(struct uniphier_aio_sub *sub, int enable); 344 345 int aiodma_ch_set_param(struct uniphier_aio_sub *sub); 346 void aiodma_ch_set_enable(struct uniphier_aio_sub *sub, int enable); 347 int aiodma_rb_set_threshold(struct uniphier_aio_sub *sub, u64 size, u32 th); 348 int aiodma_rb_set_buffer(struct uniphier_aio_sub *sub, u64 start, u64 end, 349 int period); 350 void aiodma_rb_sync(struct uniphier_aio_sub *sub, u64 start, u64 size, 351 int period); 352 bool aiodma_rb_is_irq(struct uniphier_aio_sub *sub); 353 void aiodma_rb_clear_irq(struct uniphier_aio_sub *sub); 354 355 #endif /* SND_UNIPHIER_AIO_H__ */ 356