1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port 4 * 5 * Copyright (C) 2008 Nokia Corporation 6 * 7 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com> 8 * Peter Ujfalusi <peter.ujfalusi@ti.com> 9 */ 10 11 #include <linux/init.h> 12 #include <linux/module.h> 13 #include <linux/device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/of.h> 16 #include <sound/core.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <sound/initval.h> 20 #include <sound/soc.h> 21 #include <sound/dmaengine_pcm.h> 22 23 #include "omap-mcbsp-priv.h" 24 #include "omap-mcbsp.h" 25 #include "sdma-pcm.h" 26 27 #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000) 28 29 enum { 30 OMAP_MCBSP_WORD_8 = 0, 31 OMAP_MCBSP_WORD_12, 32 OMAP_MCBSP_WORD_16, 33 OMAP_MCBSP_WORD_20, 34 OMAP_MCBSP_WORD_24, 35 OMAP_MCBSP_WORD_32, 36 }; 37 38 static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp) 39 { 40 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id); 41 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", MCBSP_READ(mcbsp, DRR2)); 42 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", MCBSP_READ(mcbsp, DRR1)); 43 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", MCBSP_READ(mcbsp, DXR2)); 44 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", MCBSP_READ(mcbsp, DXR1)); 45 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", MCBSP_READ(mcbsp, SPCR2)); 46 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", MCBSP_READ(mcbsp, SPCR1)); 47 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n", MCBSP_READ(mcbsp, RCR2)); 48 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n", MCBSP_READ(mcbsp, RCR1)); 49 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n", MCBSP_READ(mcbsp, XCR2)); 50 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n", MCBSP_READ(mcbsp, XCR1)); 51 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", MCBSP_READ(mcbsp, SRGR2)); 52 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", MCBSP_READ(mcbsp, SRGR1)); 53 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n", MCBSP_READ(mcbsp, PCR0)); 54 dev_dbg(mcbsp->dev, "***********************\n"); 55 } 56 57 static int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id) 58 { 59 struct clk *fck_src; 60 const char *src; 61 int r; 62 63 if (fck_src_id == MCBSP_CLKS_PAD_SRC) 64 src = "pad_fck"; 65 else if (fck_src_id == MCBSP_CLKS_PRCM_SRC) 66 src = "prcm_fck"; 67 else 68 return -EINVAL; 69 70 fck_src = clk_get(mcbsp->dev, src); 71 if (IS_ERR(fck_src)) { 72 dev_info(mcbsp->dev, "CLKS: could not clk_get() %s\n", src); 73 return 0; 74 } 75 76 pm_runtime_put_sync(mcbsp->dev); 77 78 r = clk_set_parent(mcbsp->fclk, fck_src); 79 if (r) 80 dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n", 81 src); 82 83 pm_runtime_get_sync(mcbsp->dev); 84 85 clk_put(fck_src); 86 87 return r; 88 } 89 90 static irqreturn_t omap_mcbsp_irq_handler(int irq, void *data) 91 { 92 struct omap_mcbsp *mcbsp = data; 93 u16 irqst; 94 95 irqst = MCBSP_READ(mcbsp, IRQST); 96 dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst); 97 98 if (irqst & RSYNCERREN) 99 dev_err(mcbsp->dev, "RX Frame Sync Error!\n"); 100 if (irqst & RFSREN) 101 dev_dbg(mcbsp->dev, "RX Frame Sync\n"); 102 if (irqst & REOFEN) 103 dev_dbg(mcbsp->dev, "RX End Of Frame\n"); 104 if (irqst & RRDYEN) 105 dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n"); 106 if (irqst & RUNDFLEN) 107 dev_err(mcbsp->dev, "RX Buffer Underflow!\n"); 108 if (irqst & ROVFLEN) 109 dev_err(mcbsp->dev, "RX Buffer Overflow!\n"); 110 111 if (irqst & XSYNCERREN) 112 dev_err(mcbsp->dev, "TX Frame Sync Error!\n"); 113 if (irqst & XFSXEN) 114 dev_dbg(mcbsp->dev, "TX Frame Sync\n"); 115 if (irqst & XEOFEN) 116 dev_dbg(mcbsp->dev, "TX End Of Frame\n"); 117 if (irqst & XRDYEN) 118 dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n"); 119 if (irqst & XUNDFLEN) 120 dev_err(mcbsp->dev, "TX Buffer Underflow!\n"); 121 if (irqst & XOVFLEN) 122 dev_err(mcbsp->dev, "TX Buffer Overflow!\n"); 123 if (irqst & XEMPTYEOFEN) 124 dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n"); 125 126 MCBSP_WRITE(mcbsp, IRQST, irqst); 127 128 return IRQ_HANDLED; 129 } 130 131 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *data) 132 { 133 struct omap_mcbsp *mcbsp = data; 134 u16 irqst_spcr2; 135 136 irqst_spcr2 = MCBSP_READ(mcbsp, SPCR2); 137 dev_dbg(mcbsp->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2); 138 139 if (irqst_spcr2 & XSYNC_ERR) { 140 dev_err(mcbsp->dev, "TX Frame Sync Error! : 0x%x\n", 141 irqst_spcr2); 142 /* Writing zero to XSYNC_ERR clears the IRQ */ 143 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2)); 144 } 145 146 return IRQ_HANDLED; 147 } 148 149 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *data) 150 { 151 struct omap_mcbsp *mcbsp = data; 152 u16 irqst_spcr1; 153 154 irqst_spcr1 = MCBSP_READ(mcbsp, SPCR1); 155 dev_dbg(mcbsp->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1); 156 157 if (irqst_spcr1 & RSYNC_ERR) { 158 dev_err(mcbsp->dev, "RX Frame Sync Error! : 0x%x\n", 159 irqst_spcr1); 160 /* Writing zero to RSYNC_ERR clears the IRQ */ 161 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1)); 162 } 163 164 return IRQ_HANDLED; 165 } 166 167 /* 168 * omap_mcbsp_config simply write a config to the 169 * appropriate McBSP. 170 * You either call this function or set the McBSP registers 171 * by yourself before calling omap_mcbsp_start(). 172 */ 173 static void omap_mcbsp_config(struct omap_mcbsp *mcbsp, 174 const struct omap_mcbsp_reg_cfg *config) 175 { 176 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n", 177 mcbsp->id, mcbsp->phys_base); 178 179 /* We write the given config */ 180 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2); 181 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1); 182 MCBSP_WRITE(mcbsp, RCR2, config->rcr2); 183 MCBSP_WRITE(mcbsp, RCR1, config->rcr1); 184 MCBSP_WRITE(mcbsp, XCR2, config->xcr2); 185 MCBSP_WRITE(mcbsp, XCR1, config->xcr1); 186 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2); 187 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1); 188 MCBSP_WRITE(mcbsp, MCR2, config->mcr2); 189 MCBSP_WRITE(mcbsp, MCR1, config->mcr1); 190 MCBSP_WRITE(mcbsp, PCR0, config->pcr0); 191 if (mcbsp->pdata->has_ccr) { 192 MCBSP_WRITE(mcbsp, XCCR, config->xccr); 193 MCBSP_WRITE(mcbsp, RCCR, config->rccr); 194 } 195 /* Enable wakeup behavior */ 196 if (mcbsp->pdata->has_wakeup) 197 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN); 198 199 /* Enable TX/RX sync error interrupts by default */ 200 if (mcbsp->irq) 201 MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN | 202 RUNDFLEN | ROVFLEN | XUNDFLEN | XOVFLEN); 203 } 204 205 /** 206 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register 207 * @mcbsp: omap_mcbsp struct for the McBSP instance 208 * @stream: Stream direction (playback/capture) 209 * 210 * Returns the address of mcbsp data transmit register or data receive register 211 * to be used by DMA for transferring/receiving data 212 */ 213 static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp, 214 unsigned int stream) 215 { 216 int data_reg; 217 218 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 219 if (mcbsp->pdata->reg_size == 2) 220 data_reg = OMAP_MCBSP_REG_DXR1; 221 else 222 data_reg = OMAP_MCBSP_REG_DXR; 223 } else { 224 if (mcbsp->pdata->reg_size == 2) 225 data_reg = OMAP_MCBSP_REG_DRR1; 226 else 227 data_reg = OMAP_MCBSP_REG_DRR; 228 } 229 230 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step; 231 } 232 233 /* 234 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words. 235 * The threshold parameter is 1 based, and it is converted (threshold - 1) 236 * for the THRSH2 register. 237 */ 238 static void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold) 239 { 240 if (threshold && threshold <= mcbsp->max_tx_thres) 241 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1); 242 } 243 244 /* 245 * omap_mcbsp_set_rx_threshold configures the receive threshold in words. 246 * The threshold parameter is 1 based, and it is converted (threshold - 1) 247 * for the THRSH1 register. 248 */ 249 static void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold) 250 { 251 if (threshold && threshold <= mcbsp->max_rx_thres) 252 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1); 253 } 254 255 /* 256 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO 257 */ 258 static u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp) 259 { 260 u16 buffstat; 261 262 /* Returns the number of free locations in the buffer */ 263 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT); 264 265 /* Number of slots are different in McBSP ports */ 266 return mcbsp->pdata->buffer_size - buffstat; 267 } 268 269 /* 270 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO 271 * to reach the threshold value (when the DMA will be triggered to read it) 272 */ 273 static u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp) 274 { 275 u16 buffstat, threshold; 276 277 /* Returns the number of used locations in the buffer */ 278 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT); 279 /* RX threshold */ 280 threshold = MCBSP_READ(mcbsp, THRSH1); 281 282 /* Return the number of location till we reach the threshold limit */ 283 if (threshold <= buffstat) 284 return 0; 285 else 286 return threshold - buffstat; 287 } 288 289 static int omap_mcbsp_request(struct omap_mcbsp *mcbsp) 290 { 291 void *reg_cache; 292 int err; 293 294 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL); 295 if (!reg_cache) 296 return -ENOMEM; 297 298 spin_lock(&mcbsp->lock); 299 if (!mcbsp->free) { 300 dev_err(mcbsp->dev, "McBSP%d is currently in use\n", mcbsp->id); 301 err = -EBUSY; 302 goto err_kfree; 303 } 304 305 mcbsp->free = false; 306 mcbsp->reg_cache = reg_cache; 307 spin_unlock(&mcbsp->lock); 308 309 if(mcbsp->pdata->ops && mcbsp->pdata->ops->request) 310 mcbsp->pdata->ops->request(mcbsp->id - 1); 311 312 /* 313 * Make sure that transmitter, receiver and sample-rate generator are 314 * not running before activating IRQs. 315 */ 316 MCBSP_WRITE(mcbsp, SPCR1, 0); 317 MCBSP_WRITE(mcbsp, SPCR2, 0); 318 319 if (mcbsp->irq) { 320 err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0, 321 "McBSP", (void *)mcbsp); 322 if (err != 0) { 323 dev_err(mcbsp->dev, "Unable to request IRQ\n"); 324 goto err_clk_disable; 325 } 326 } else { 327 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0, 328 "McBSP TX", (void *)mcbsp); 329 if (err != 0) { 330 dev_err(mcbsp->dev, "Unable to request TX IRQ\n"); 331 goto err_clk_disable; 332 } 333 334 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0, 335 "McBSP RX", (void *)mcbsp); 336 if (err != 0) { 337 dev_err(mcbsp->dev, "Unable to request RX IRQ\n"); 338 goto err_free_irq; 339 } 340 } 341 342 return 0; 343 err_free_irq: 344 free_irq(mcbsp->tx_irq, (void *)mcbsp); 345 err_clk_disable: 346 if(mcbsp->pdata->ops && mcbsp->pdata->ops->free) 347 mcbsp->pdata->ops->free(mcbsp->id - 1); 348 349 /* Disable wakeup behavior */ 350 if (mcbsp->pdata->has_wakeup) 351 MCBSP_WRITE(mcbsp, WAKEUPEN, 0); 352 353 spin_lock(&mcbsp->lock); 354 mcbsp->free = true; 355 mcbsp->reg_cache = NULL; 356 err_kfree: 357 spin_unlock(&mcbsp->lock); 358 kfree(reg_cache); 359 360 return err; 361 } 362 363 static void omap_mcbsp_free(struct omap_mcbsp *mcbsp) 364 { 365 void *reg_cache; 366 367 if(mcbsp->pdata->ops && mcbsp->pdata->ops->free) 368 mcbsp->pdata->ops->free(mcbsp->id - 1); 369 370 /* Disable wakeup behavior */ 371 if (mcbsp->pdata->has_wakeup) 372 MCBSP_WRITE(mcbsp, WAKEUPEN, 0); 373 374 /* Disable interrupt requests */ 375 if (mcbsp->irq) { 376 MCBSP_WRITE(mcbsp, IRQEN, 0); 377 378 free_irq(mcbsp->irq, (void *)mcbsp); 379 } else { 380 free_irq(mcbsp->rx_irq, (void *)mcbsp); 381 free_irq(mcbsp->tx_irq, (void *)mcbsp); 382 } 383 384 reg_cache = mcbsp->reg_cache; 385 386 /* 387 * Select CLKS source from internal source unconditionally before 388 * marking the McBSP port as free. 389 * If the external clock source via MCBSP_CLKS pin has been selected the 390 * system will refuse to enter idle if the CLKS pin source is not reset 391 * back to internal source. 392 */ 393 if (!mcbsp_omap1()) 394 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC); 395 396 spin_lock(&mcbsp->lock); 397 if (mcbsp->free) 398 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id); 399 else 400 mcbsp->free = true; 401 mcbsp->reg_cache = NULL; 402 spin_unlock(&mcbsp->lock); 403 404 kfree(reg_cache); 405 } 406 407 /* 408 * Here we start the McBSP, by enabling transmitter, receiver or both. 409 * If no transmitter or receiver is active prior calling, then sample-rate 410 * generator and frame sync are started. 411 */ 412 static void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int stream) 413 { 414 int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK); 415 int rx = !tx; 416 int enable_srg = 0; 417 u16 w; 418 419 if (mcbsp->st_data) 420 omap_mcbsp_st_start(mcbsp); 421 422 /* Only enable SRG, if McBSP is master */ 423 w = MCBSP_READ_CACHE(mcbsp, PCR0); 424 if (w & (FSXM | FSRM | CLKXM | CLKRM)) 425 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | 426 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); 427 428 if (enable_srg) { 429 /* Start the sample generator */ 430 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 431 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6)); 432 } 433 434 /* Enable transmitter and receiver */ 435 tx &= 1; 436 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 437 MCBSP_WRITE(mcbsp, SPCR2, w | tx); 438 439 rx &= 1; 440 w = MCBSP_READ_CACHE(mcbsp, SPCR1); 441 MCBSP_WRITE(mcbsp, SPCR1, w | rx); 442 443 /* 444 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec 445 * REVISIT: 100us may give enough time for two CLKSRG, however 446 * due to some unknown PM related, clock gating etc. reason it 447 * is now at 500us. 448 */ 449 udelay(500); 450 451 if (enable_srg) { 452 /* Start frame sync */ 453 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 454 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); 455 } 456 457 if (mcbsp->pdata->has_ccr) { 458 /* Release the transmitter and receiver */ 459 w = MCBSP_READ_CACHE(mcbsp, XCCR); 460 w &= ~(tx ? XDISABLE : 0); 461 MCBSP_WRITE(mcbsp, XCCR, w); 462 w = MCBSP_READ_CACHE(mcbsp, RCCR); 463 w &= ~(rx ? RDISABLE : 0); 464 MCBSP_WRITE(mcbsp, RCCR, w); 465 } 466 467 /* Dump McBSP Regs */ 468 omap_mcbsp_dump_reg(mcbsp); 469 } 470 471 static void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int stream) 472 { 473 int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK); 474 int rx = !tx; 475 int idle; 476 u16 w; 477 478 /* Reset transmitter */ 479 tx &= 1; 480 if (mcbsp->pdata->has_ccr) { 481 w = MCBSP_READ_CACHE(mcbsp, XCCR); 482 w |= (tx ? XDISABLE : 0); 483 MCBSP_WRITE(mcbsp, XCCR, w); 484 } 485 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 486 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx); 487 488 /* Reset receiver */ 489 rx &= 1; 490 if (mcbsp->pdata->has_ccr) { 491 w = MCBSP_READ_CACHE(mcbsp, RCCR); 492 w |= (rx ? RDISABLE : 0); 493 MCBSP_WRITE(mcbsp, RCCR, w); 494 } 495 w = MCBSP_READ_CACHE(mcbsp, SPCR1); 496 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx); 497 498 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | 499 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); 500 501 if (idle) { 502 /* Reset the sample rate generator */ 503 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 504 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6)); 505 } 506 507 if (mcbsp->st_data) 508 omap_mcbsp_st_stop(mcbsp); 509 } 510 511 #define max_thres(m) (mcbsp->pdata->buffer_size) 512 #define valid_threshold(m, val) ((val) <= max_thres(m)) 513 #define THRESHOLD_PROP_BUILDER(prop) \ 514 static ssize_t prop##_show(struct device *dev, \ 515 struct device_attribute *attr, char *buf) \ 516 { \ 517 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \ 518 \ 519 return sysfs_emit(buf, "%u\n", mcbsp->prop); \ 520 } \ 521 \ 522 static ssize_t prop##_store(struct device *dev, \ 523 struct device_attribute *attr, \ 524 const char *buf, size_t size) \ 525 { \ 526 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \ 527 unsigned long val; \ 528 int status; \ 529 \ 530 status = kstrtoul(buf, 0, &val); \ 531 if (status) \ 532 return status; \ 533 \ 534 if (!valid_threshold(mcbsp, val)) \ 535 return -EDOM; \ 536 \ 537 mcbsp->prop = val; \ 538 return size; \ 539 } \ 540 \ 541 static DEVICE_ATTR_RW(prop) 542 543 THRESHOLD_PROP_BUILDER(max_tx_thres); 544 THRESHOLD_PROP_BUILDER(max_rx_thres); 545 546 static const char * const dma_op_modes[] = { 547 "element", "threshold", 548 }; 549 550 static ssize_t dma_op_mode_show(struct device *dev, 551 struct device_attribute *attr, char *buf) 552 { 553 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); 554 int dma_op_mode, i = 0; 555 ssize_t len = 0; 556 const char * const *s; 557 558 dma_op_mode = mcbsp->dma_op_mode; 559 560 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) { 561 if (dma_op_mode == i) 562 len += sysfs_emit_at(buf, len, "[%s] ", *s); 563 else 564 len += sysfs_emit_at(buf, len, "%s ", *s); 565 } 566 len += sysfs_emit_at(buf, len, "\n"); 567 568 return len; 569 } 570 571 static ssize_t dma_op_mode_store(struct device *dev, 572 struct device_attribute *attr, const char *buf, 573 size_t size) 574 { 575 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); 576 int i; 577 578 i = sysfs_match_string(dma_op_modes, buf); 579 if (i < 0) 580 return i; 581 582 spin_lock_irq(&mcbsp->lock); 583 if (!mcbsp->free) { 584 size = -EBUSY; 585 goto unlock; 586 } 587 mcbsp->dma_op_mode = i; 588 589 unlock: 590 spin_unlock_irq(&mcbsp->lock); 591 592 return size; 593 } 594 595 static DEVICE_ATTR_RW(dma_op_mode); 596 597 static const struct attribute *additional_attrs[] = { 598 &dev_attr_max_tx_thres.attr, 599 &dev_attr_max_rx_thres.attr, 600 &dev_attr_dma_op_mode.attr, 601 NULL, 602 }; 603 604 static const struct attribute_group additional_attr_group = { 605 .attrs = (struct attribute **)additional_attrs, 606 }; 607 608 /* 609 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510. 610 * 730 has only 2 McBSP, and both of them are MPU peripherals. 611 */ 612 static int omap_mcbsp_init(struct platform_device *pdev) 613 { 614 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev); 615 struct resource *res; 616 int ret; 617 618 spin_lock_init(&mcbsp->lock); 619 mcbsp->free = true; 620 621 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); 622 if (!res) 623 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 624 625 mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res); 626 if (IS_ERR(mcbsp->io_base)) 627 return PTR_ERR(mcbsp->io_base); 628 629 mcbsp->phys_base = res->start; 630 mcbsp->reg_cache_size = resource_size(res); 631 632 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); 633 if (!res) 634 mcbsp->phys_dma_base = mcbsp->phys_base; 635 else 636 mcbsp->phys_dma_base = res->start; 637 638 /* 639 * OMAP1, 2 uses two interrupt lines: TX, RX 640 * OMAP2430, OMAP3 SoC have combined IRQ line as well. 641 * OMAP4 and newer SoC only have the combined IRQ line. 642 * Use the combined IRQ if available since it gives better debugging 643 * possibilities. 644 */ 645 mcbsp->irq = platform_get_irq_byname(pdev, "common"); 646 if (mcbsp->irq == -ENXIO) { 647 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx"); 648 649 if (mcbsp->tx_irq == -ENXIO) { 650 mcbsp->irq = platform_get_irq(pdev, 0); 651 mcbsp->tx_irq = 0; 652 } else { 653 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx"); 654 mcbsp->irq = 0; 655 } 656 } 657 658 if (!pdev->dev.of_node) { 659 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 660 if (!res) { 661 dev_err(&pdev->dev, "invalid tx DMA channel\n"); 662 return -ENODEV; 663 } 664 mcbsp->dma_req[0] = res->start; 665 mcbsp->dma_data[0].filter_data = &mcbsp->dma_req[0]; 666 667 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 668 if (!res) { 669 dev_err(&pdev->dev, "invalid rx DMA channel\n"); 670 return -ENODEV; 671 } 672 mcbsp->dma_req[1] = res->start; 673 mcbsp->dma_data[1].filter_data = &mcbsp->dma_req[1]; 674 } else { 675 mcbsp->dma_data[0].filter_data = "tx"; 676 mcbsp->dma_data[1].filter_data = "rx"; 677 } 678 679 mcbsp->dma_data[0].addr = omap_mcbsp_dma_reg_params(mcbsp, 680 SNDRV_PCM_STREAM_PLAYBACK); 681 mcbsp->dma_data[1].addr = omap_mcbsp_dma_reg_params(mcbsp, 682 SNDRV_PCM_STREAM_CAPTURE); 683 684 mcbsp->fclk = devm_clk_get(&pdev->dev, "fck"); 685 if (IS_ERR(mcbsp->fclk)) { 686 ret = PTR_ERR(mcbsp->fclk); 687 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret); 688 return ret; 689 } 690 691 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT; 692 if (mcbsp->pdata->buffer_size) { 693 /* 694 * Initially configure the maximum thresholds to a safe value. 695 * The McBSP FIFO usage with these values should not go under 696 * 16 locations. 697 * If the whole FIFO without safety buffer is used, than there 698 * is a possibility that the DMA will be not able to push the 699 * new data on time, causing channel shifts in runtime. 700 */ 701 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10; 702 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10; 703 704 ret = devm_device_add_group(mcbsp->dev, &additional_attr_group); 705 if (ret) { 706 dev_err(mcbsp->dev, 707 "Unable to create additional controls\n"); 708 return ret; 709 } 710 } 711 712 return omap_mcbsp_st_init(pdev); 713 } 714 715 /* 716 * Stream DMA parameters. DMA request line and port address are set runtime 717 * since they are different between OMAP1 and later OMAPs 718 */ 719 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream, 720 unsigned int packet_size) 721 { 722 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 723 struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); 724 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 725 int words; 726 727 /* No need to proceed further if McBSP does not have FIFO */ 728 if (mcbsp->pdata->buffer_size == 0) 729 return; 730 731 /* 732 * Configure McBSP threshold based on either: 733 * packet_size, when the sDMA is in packet mode, or based on the 734 * period size in THRESHOLD mode, otherwise use McBSP threshold = 1 735 * for mono streams. 736 */ 737 if (packet_size) 738 words = packet_size; 739 else 740 words = 1; 741 742 /* Configure McBSP internal buffer usage */ 743 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 744 omap_mcbsp_set_tx_threshold(mcbsp, words); 745 else 746 omap_mcbsp_set_rx_threshold(mcbsp, words); 747 } 748 749 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params, 750 struct snd_pcm_hw_rule *rule) 751 { 752 struct snd_interval *buffer_size = hw_param_interval(params, 753 SNDRV_PCM_HW_PARAM_BUFFER_SIZE); 754 struct snd_interval *channels = hw_param_interval(params, 755 SNDRV_PCM_HW_PARAM_CHANNELS); 756 struct omap_mcbsp *mcbsp = rule->private; 757 struct snd_interval frames; 758 int size; 759 760 snd_interval_any(&frames); 761 size = mcbsp->pdata->buffer_size; 762 763 frames.min = size / channels->min; 764 frames.integer = 1; 765 return snd_interval_refine(buffer_size, &frames); 766 } 767 768 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream, 769 struct snd_soc_dai *cpu_dai) 770 { 771 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 772 int err = 0; 773 774 if (!snd_soc_dai_active(cpu_dai)) 775 err = omap_mcbsp_request(mcbsp); 776 777 /* 778 * OMAP3 McBSP FIFO is word structured. 779 * McBSP2 has 1024 + 256 = 1280 word long buffer, 780 * McBSP1,3,4,5 has 128 word long buffer 781 * This means that the size of the FIFO depends on the sample format. 782 * For example on McBSP3: 783 * 16bit samples: size is 128 * 2 = 256 bytes 784 * 32bit samples: size is 128 * 4 = 512 bytes 785 * It is simpler to place constraint for buffer and period based on 786 * channels. 787 * McBSP3 as example again (16 or 32 bit samples): 788 * 1 channel (mono): size is 128 frames (128 words) 789 * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words) 790 * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words) 791 */ 792 if (mcbsp->pdata->buffer_size) { 793 /* 794 * Rule for the buffer size. We should not allow 795 * smaller buffer than the FIFO size to avoid underruns. 796 * This applies only for the playback stream. 797 */ 798 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 799 snd_pcm_hw_rule_add(substream->runtime, 0, 800 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 801 omap_mcbsp_hwrule_min_buffersize, 802 mcbsp, 803 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 804 805 /* Make sure, that the period size is always even */ 806 snd_pcm_hw_constraint_step(substream->runtime, 0, 807 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); 808 } 809 810 return err; 811 } 812 813 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream, 814 struct snd_soc_dai *cpu_dai) 815 { 816 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 817 int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 818 int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE; 819 int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK; 820 821 if (mcbsp->latency[stream2]) 822 cpu_latency_qos_update_request(&mcbsp->pm_qos_req, 823 mcbsp->latency[stream2]); 824 else if (mcbsp->latency[stream1]) 825 cpu_latency_qos_remove_request(&mcbsp->pm_qos_req); 826 827 mcbsp->latency[stream1] = 0; 828 829 if (!snd_soc_dai_active(cpu_dai)) { 830 omap_mcbsp_free(mcbsp); 831 mcbsp->configured = 0; 832 } 833 } 834 835 static int omap_mcbsp_dai_prepare(struct snd_pcm_substream *substream, 836 struct snd_soc_dai *cpu_dai) 837 { 838 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 839 struct pm_qos_request *pm_qos_req = &mcbsp->pm_qos_req; 840 int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 841 int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE; 842 int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK; 843 int latency = mcbsp->latency[stream2]; 844 845 /* Prevent omap hardware from hitting off between FIFO fills */ 846 if (!latency || mcbsp->latency[stream1] < latency) 847 latency = mcbsp->latency[stream1]; 848 849 if (cpu_latency_qos_request_active(pm_qos_req)) 850 cpu_latency_qos_update_request(pm_qos_req, latency); 851 else if (latency) 852 cpu_latency_qos_add_request(pm_qos_req, latency); 853 854 return 0; 855 } 856 857 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd, 858 struct snd_soc_dai *cpu_dai) 859 { 860 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 861 862 switch (cmd) { 863 case SNDRV_PCM_TRIGGER_START: 864 case SNDRV_PCM_TRIGGER_RESUME: 865 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 866 mcbsp->active++; 867 omap_mcbsp_start(mcbsp, substream->stream); 868 break; 869 870 case SNDRV_PCM_TRIGGER_STOP: 871 case SNDRV_PCM_TRIGGER_SUSPEND: 872 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 873 omap_mcbsp_stop(mcbsp, substream->stream); 874 mcbsp->active--; 875 break; 876 default: 877 return -EINVAL; 878 } 879 880 return 0; 881 } 882 883 static snd_pcm_sframes_t omap_mcbsp_dai_delay( 884 struct snd_pcm_substream *substream, 885 struct snd_soc_dai *dai) 886 { 887 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 888 struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); 889 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 890 u16 fifo_use; 891 snd_pcm_sframes_t delay; 892 893 /* No need to proceed further if McBSP does not have FIFO */ 894 if (mcbsp->pdata->buffer_size == 0) 895 return 0; 896 897 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 898 fifo_use = omap_mcbsp_get_tx_delay(mcbsp); 899 else 900 fifo_use = omap_mcbsp_get_rx_delay(mcbsp); 901 902 /* 903 * Divide the used locations with the channel count to get the 904 * FIFO usage in samples (don't care about partial samples in the 905 * buffer). 906 */ 907 delay = fifo_use / substream->runtime->channels; 908 909 return delay; 910 } 911 912 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, 913 struct snd_pcm_hw_params *params, 914 struct snd_soc_dai *cpu_dai) 915 { 916 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 917 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs; 918 struct snd_dmaengine_dai_dma_data *dma_data; 919 int wlen, channels, wpf; 920 int pkt_size = 0; 921 unsigned int format, div, framesize, master; 922 unsigned int buffer_size = mcbsp->pdata->buffer_size; 923 924 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream); 925 channels = params_channels(params); 926 927 switch (params_format(params)) { 928 case SNDRV_PCM_FORMAT_S16_LE: 929 wlen = 16; 930 break; 931 case SNDRV_PCM_FORMAT_S32_LE: 932 wlen = 32; 933 break; 934 default: 935 return -EINVAL; 936 } 937 if (buffer_size) { 938 int latency; 939 940 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) { 941 int period_words, max_thrsh; 942 int divider = 0; 943 944 period_words = params_period_bytes(params) / (wlen / 8); 945 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 946 max_thrsh = mcbsp->max_tx_thres; 947 else 948 max_thrsh = mcbsp->max_rx_thres; 949 /* 950 * Use sDMA packet mode if McBSP is in threshold mode: 951 * If period words less than the FIFO size the packet 952 * size is set to the number of period words, otherwise 953 * Look for the biggest threshold value which divides 954 * the period size evenly. 955 */ 956 divider = period_words / max_thrsh; 957 if (period_words % max_thrsh) 958 divider++; 959 while (period_words % divider && 960 divider < period_words) 961 divider++; 962 if (divider == period_words) 963 return -EINVAL; 964 965 pkt_size = period_words / divider; 966 } else if (channels > 1) { 967 /* Use packet mode for non mono streams */ 968 pkt_size = channels; 969 } 970 971 latency = (buffer_size - pkt_size) / channels; 972 latency = latency * USEC_PER_SEC / 973 (params->rate_num / params->rate_den); 974 mcbsp->latency[substream->stream] = latency; 975 976 omap_mcbsp_set_threshold(substream, pkt_size); 977 } 978 979 dma_data->maxburst = pkt_size; 980 981 if (mcbsp->configured) { 982 /* McBSP already configured by another stream */ 983 return 0; 984 } 985 986 regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7)); 987 regs->xcr2 &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7)); 988 regs->rcr1 &= ~(RFRLEN1(0x7f) | RWDLEN1(7)); 989 regs->xcr1 &= ~(XFRLEN1(0x7f) | XWDLEN1(7)); 990 format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK; 991 wpf = channels; 992 if (channels == 2 && (format == SND_SOC_DAIFMT_I2S || 993 format == SND_SOC_DAIFMT_LEFT_J)) { 994 /* Use dual-phase frames */ 995 regs->rcr2 |= RPHASE; 996 regs->xcr2 |= XPHASE; 997 /* Set 1 word per (McBSP) frame for phase1 and phase2 */ 998 wpf--; 999 regs->rcr2 |= RFRLEN2(wpf - 1); 1000 regs->xcr2 |= XFRLEN2(wpf - 1); 1001 } 1002 1003 regs->rcr1 |= RFRLEN1(wpf - 1); 1004 regs->xcr1 |= XFRLEN1(wpf - 1); 1005 1006 switch (params_format(params)) { 1007 case SNDRV_PCM_FORMAT_S16_LE: 1008 /* Set word lengths */ 1009 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16); 1010 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16); 1011 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16); 1012 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16); 1013 break; 1014 case SNDRV_PCM_FORMAT_S32_LE: 1015 /* Set word lengths */ 1016 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32); 1017 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32); 1018 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32); 1019 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32); 1020 break; 1021 default: 1022 /* Unsupported PCM format */ 1023 return -EINVAL; 1024 } 1025 1026 /* In McBSP master modes, FRAME (i.e. sample rate) is generated 1027 * by _counting_ BCLKs. Calculate frame size in BCLKs */ 1028 master = mcbsp->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK; 1029 if (master == SND_SOC_DAIFMT_BP_FP) { 1030 div = mcbsp->clk_div ? mcbsp->clk_div : 1; 1031 framesize = (mcbsp->in_freq / div) / params_rate(params); 1032 1033 if (framesize < wlen * channels) { 1034 printk(KERN_ERR "%s: not enough bandwidth for desired rate and " 1035 "channels\n", __func__); 1036 return -EINVAL; 1037 } 1038 } else 1039 framesize = wlen * channels; 1040 1041 /* Set FS period and length in terms of bit clock periods */ 1042 regs->srgr2 &= ~FPER(0xfff); 1043 regs->srgr1 &= ~FWID(0xff); 1044 switch (format) { 1045 case SND_SOC_DAIFMT_I2S: 1046 case SND_SOC_DAIFMT_LEFT_J: 1047 regs->srgr2 |= FPER(framesize - 1); 1048 regs->srgr1 |= FWID((framesize >> 1) - 1); 1049 break; 1050 case SND_SOC_DAIFMT_DSP_A: 1051 case SND_SOC_DAIFMT_DSP_B: 1052 regs->srgr2 |= FPER(framesize - 1); 1053 regs->srgr1 |= FWID(0); 1054 break; 1055 } 1056 1057 omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs); 1058 mcbsp->wlen = wlen; 1059 mcbsp->configured = 1; 1060 1061 return 0; 1062 } 1063 1064 /* 1065 * This must be called before _set_clkdiv and _set_sysclk since McBSP register 1066 * cache is initialized here 1067 */ 1068 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai, 1069 unsigned int fmt) 1070 { 1071 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 1072 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs; 1073 bool inv_fs = false; 1074 1075 if (mcbsp->configured) 1076 return 0; 1077 1078 mcbsp->fmt = fmt; 1079 memset(regs, 0, sizeof(*regs)); 1080 /* Generic McBSP register settings */ 1081 regs->spcr2 |= XINTM(3) | FREE; 1082 regs->spcr1 |= RINTM(3); 1083 /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */ 1084 if (!mcbsp->pdata->has_ccr) { 1085 regs->rcr2 |= RFIG; 1086 regs->xcr2 |= XFIG; 1087 } 1088 1089 /* Configure XCCR/RCCR only for revisions which have ccr registers */ 1090 if (mcbsp->pdata->has_ccr) { 1091 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE; 1092 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE; 1093 } 1094 1095 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1096 case SND_SOC_DAIFMT_I2S: 1097 /* 1-bit data delay */ 1098 regs->rcr2 |= RDATDLY(1); 1099 regs->xcr2 |= XDATDLY(1); 1100 break; 1101 case SND_SOC_DAIFMT_LEFT_J: 1102 /* 0-bit data delay */ 1103 regs->rcr2 |= RDATDLY(0); 1104 regs->xcr2 |= XDATDLY(0); 1105 regs->spcr1 |= RJUST(2); 1106 /* Invert FS polarity configuration */ 1107 inv_fs = true; 1108 break; 1109 case SND_SOC_DAIFMT_DSP_A: 1110 /* 1-bit data delay */ 1111 regs->rcr2 |= RDATDLY(1); 1112 regs->xcr2 |= XDATDLY(1); 1113 /* Invert FS polarity configuration */ 1114 inv_fs = true; 1115 break; 1116 case SND_SOC_DAIFMT_DSP_B: 1117 /* 0-bit data delay */ 1118 regs->rcr2 |= RDATDLY(0); 1119 regs->xcr2 |= XDATDLY(0); 1120 /* Invert FS polarity configuration */ 1121 inv_fs = true; 1122 break; 1123 default: 1124 /* Unsupported data format */ 1125 return -EINVAL; 1126 } 1127 1128 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1129 case SND_SOC_DAIFMT_BP_FP: 1130 /* McBSP master. Set FS and bit clocks as outputs */ 1131 regs->pcr0 |= FSXM | FSRM | 1132 CLKXM | CLKRM; 1133 /* Sample rate generator drives the FS */ 1134 regs->srgr2 |= FSGM; 1135 break; 1136 case SND_SOC_DAIFMT_BC_FP: 1137 /* McBSP slave. FS clock as output */ 1138 regs->srgr2 |= FSGM; 1139 regs->pcr0 |= FSXM | FSRM; 1140 break; 1141 case SND_SOC_DAIFMT_BC_FC: 1142 /* McBSP slave */ 1143 break; 1144 default: 1145 /* Unsupported master/slave configuration */ 1146 return -EINVAL; 1147 } 1148 1149 /* Set bit clock (CLKX/CLKR) and FS polarities */ 1150 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1151 case SND_SOC_DAIFMT_NB_NF: 1152 /* 1153 * Normal BCLK + FS. 1154 * FS active low. TX data driven on falling edge of bit clock 1155 * and RX data sampled on rising edge of bit clock. 1156 */ 1157 regs->pcr0 |= FSXP | FSRP | 1158 CLKXP | CLKRP; 1159 break; 1160 case SND_SOC_DAIFMT_NB_IF: 1161 regs->pcr0 |= CLKXP | CLKRP; 1162 break; 1163 case SND_SOC_DAIFMT_IB_NF: 1164 regs->pcr0 |= FSXP | FSRP; 1165 break; 1166 case SND_SOC_DAIFMT_IB_IF: 1167 break; 1168 default: 1169 return -EINVAL; 1170 } 1171 if (inv_fs) 1172 regs->pcr0 ^= FSXP | FSRP; 1173 1174 return 0; 1175 } 1176 1177 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai, 1178 int div_id, int div) 1179 { 1180 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 1181 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs; 1182 1183 if (div_id != OMAP_MCBSP_CLKGDV) 1184 return -ENODEV; 1185 1186 mcbsp->clk_div = div; 1187 regs->srgr1 &= ~CLKGDV(0xff); 1188 regs->srgr1 |= CLKGDV(div - 1); 1189 1190 return 0; 1191 } 1192 1193 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 1194 int clk_id, unsigned int freq, 1195 int dir) 1196 { 1197 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 1198 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs; 1199 int err = 0; 1200 1201 if (mcbsp->active) { 1202 if (freq == mcbsp->in_freq) 1203 return 0; 1204 else 1205 return -EBUSY; 1206 } 1207 1208 mcbsp->in_freq = freq; 1209 regs->srgr2 &= ~CLKSM; 1210 regs->pcr0 &= ~SCLKME; 1211 1212 switch (clk_id) { 1213 case OMAP_MCBSP_SYSCLK_CLK: 1214 regs->srgr2 |= CLKSM; 1215 break; 1216 case OMAP_MCBSP_SYSCLK_CLKS_FCLK: 1217 if (mcbsp_omap1()) { 1218 err = -EINVAL; 1219 break; 1220 } 1221 err = omap2_mcbsp_set_clks_src(mcbsp, 1222 MCBSP_CLKS_PRCM_SRC); 1223 break; 1224 case OMAP_MCBSP_SYSCLK_CLKS_EXT: 1225 if (mcbsp_omap1()) { 1226 err = 0; 1227 break; 1228 } 1229 err = omap2_mcbsp_set_clks_src(mcbsp, 1230 MCBSP_CLKS_PAD_SRC); 1231 break; 1232 1233 case OMAP_MCBSP_SYSCLK_CLKX_EXT: 1234 regs->srgr2 |= CLKSM; 1235 regs->pcr0 |= SCLKME; 1236 /* 1237 * If McBSP is master but yet the CLKX/CLKR pin drives the SRG, 1238 * disable output on those pins. This enables to inject the 1239 * reference clock through CLKX/CLKR. For this to work 1240 * set_dai_sysclk() _needs_ to be called after set_dai_fmt(). 1241 */ 1242 regs->pcr0 &= ~CLKXM; 1243 break; 1244 case OMAP_MCBSP_SYSCLK_CLKR_EXT: 1245 regs->pcr0 |= SCLKME; 1246 /* Disable ouput on CLKR pin in master mode */ 1247 regs->pcr0 &= ~CLKRM; 1248 break; 1249 default: 1250 err = -ENODEV; 1251 } 1252 1253 return err; 1254 } 1255 1256 static int omap_mcbsp_probe(struct snd_soc_dai *dai) 1257 { 1258 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai); 1259 1260 pm_runtime_enable(mcbsp->dev); 1261 1262 snd_soc_dai_init_dma_data(dai, 1263 &mcbsp->dma_data[SNDRV_PCM_STREAM_PLAYBACK], 1264 &mcbsp->dma_data[SNDRV_PCM_STREAM_CAPTURE]); 1265 1266 return 0; 1267 } 1268 1269 static int omap_mcbsp_remove(struct snd_soc_dai *dai) 1270 { 1271 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai); 1272 1273 pm_runtime_disable(mcbsp->dev); 1274 1275 return 0; 1276 } 1277 1278 static const struct snd_soc_dai_ops mcbsp_dai_ops = { 1279 .probe = omap_mcbsp_probe, 1280 .remove = omap_mcbsp_remove, 1281 .startup = omap_mcbsp_dai_startup, 1282 .shutdown = omap_mcbsp_dai_shutdown, 1283 .prepare = omap_mcbsp_dai_prepare, 1284 .trigger = omap_mcbsp_dai_trigger, 1285 .delay = omap_mcbsp_dai_delay, 1286 .hw_params = omap_mcbsp_dai_hw_params, 1287 .set_fmt = omap_mcbsp_dai_set_dai_fmt, 1288 .set_clkdiv = omap_mcbsp_dai_set_clkdiv, 1289 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk, 1290 }; 1291 1292 static struct snd_soc_dai_driver omap_mcbsp_dai = { 1293 .playback = { 1294 .channels_min = 1, 1295 .channels_max = 16, 1296 .rates = OMAP_MCBSP_RATES, 1297 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 1298 }, 1299 .capture = { 1300 .channels_min = 1, 1301 .channels_max = 16, 1302 .rates = OMAP_MCBSP_RATES, 1303 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 1304 }, 1305 .ops = &mcbsp_dai_ops, 1306 }; 1307 1308 static const struct snd_soc_component_driver omap_mcbsp_component = { 1309 .name = "omap-mcbsp", 1310 .legacy_dai_naming = 1, 1311 }; 1312 1313 static struct omap_mcbsp_platform_data omap2420_pdata = { 1314 .reg_step = 4, 1315 .reg_size = 2, 1316 }; 1317 1318 static struct omap_mcbsp_platform_data omap2430_pdata = { 1319 .reg_step = 4, 1320 .reg_size = 4, 1321 .has_ccr = true, 1322 }; 1323 1324 static struct omap_mcbsp_platform_data omap3_pdata = { 1325 .reg_step = 4, 1326 .reg_size = 4, 1327 .has_ccr = true, 1328 .has_wakeup = true, 1329 }; 1330 1331 static struct omap_mcbsp_platform_data omap4_pdata = { 1332 .reg_step = 4, 1333 .reg_size = 4, 1334 .has_ccr = true, 1335 .has_wakeup = true, 1336 }; 1337 1338 static const struct of_device_id omap_mcbsp_of_match[] = { 1339 { 1340 .compatible = "ti,omap2420-mcbsp", 1341 .data = &omap2420_pdata, 1342 }, 1343 { 1344 .compatible = "ti,omap2430-mcbsp", 1345 .data = &omap2430_pdata, 1346 }, 1347 { 1348 .compatible = "ti,omap3-mcbsp", 1349 .data = &omap3_pdata, 1350 }, 1351 { 1352 .compatible = "ti,omap4-mcbsp", 1353 .data = &omap4_pdata, 1354 }, 1355 { }, 1356 }; 1357 MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match); 1358 1359 static int asoc_mcbsp_probe(struct platform_device *pdev) 1360 { 1361 struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev); 1362 const struct omap_mcbsp_platform_data *match_pdata = 1363 device_get_match_data(&pdev->dev); 1364 struct omap_mcbsp *mcbsp; 1365 int ret; 1366 1367 if (match_pdata) { 1368 struct device_node *node = pdev->dev.of_node; 1369 struct omap_mcbsp_platform_data *pdata_quirk = pdata; 1370 int buffer_size; 1371 1372 pdata = devm_kmemdup(&pdev->dev, match_pdata, 1373 sizeof(struct omap_mcbsp_platform_data), 1374 GFP_KERNEL); 1375 if (!pdata) 1376 return -ENOMEM; 1377 1378 if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size)) 1379 pdata->buffer_size = buffer_size; 1380 if (pdata_quirk) 1381 pdata->force_ick_on = pdata_quirk->force_ick_on; 1382 } else if (!pdata) { 1383 dev_err(&pdev->dev, "missing platform data.\n"); 1384 return -EINVAL; 1385 } 1386 mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL); 1387 if (!mcbsp) 1388 return -ENOMEM; 1389 1390 mcbsp->id = pdev->id; 1391 mcbsp->pdata = pdata; 1392 mcbsp->dev = &pdev->dev; 1393 platform_set_drvdata(pdev, mcbsp); 1394 1395 ret = omap_mcbsp_init(pdev); 1396 if (ret) 1397 return ret; 1398 1399 if (mcbsp->pdata->reg_size == 2) { 1400 omap_mcbsp_dai.playback.formats = SNDRV_PCM_FMTBIT_S16_LE; 1401 omap_mcbsp_dai.capture.formats = SNDRV_PCM_FMTBIT_S16_LE; 1402 } 1403 1404 ret = devm_snd_soc_register_component(&pdev->dev, 1405 &omap_mcbsp_component, 1406 &omap_mcbsp_dai, 1); 1407 if (ret) 1408 return ret; 1409 1410 return sdma_pcm_platform_register(&pdev->dev, "tx", "rx"); 1411 } 1412 1413 static void asoc_mcbsp_remove(struct platform_device *pdev) 1414 { 1415 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev); 1416 1417 if (mcbsp->pdata->ops && mcbsp->pdata->ops->free) 1418 mcbsp->pdata->ops->free(mcbsp->id); 1419 1420 if (cpu_latency_qos_request_active(&mcbsp->pm_qos_req)) 1421 cpu_latency_qos_remove_request(&mcbsp->pm_qos_req); 1422 } 1423 1424 static struct platform_driver asoc_mcbsp_driver = { 1425 .driver = { 1426 .name = "omap-mcbsp", 1427 .of_match_table = omap_mcbsp_of_match, 1428 }, 1429 1430 .probe = asoc_mcbsp_probe, 1431 .remove_new = asoc_mcbsp_remove, 1432 }; 1433 1434 module_platform_driver(asoc_mcbsp_driver); 1435 1436 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>"); 1437 MODULE_DESCRIPTION("OMAP I2S SoC Interface"); 1438 MODULE_LICENSE("GPL"); 1439 MODULE_ALIAS("platform:omap-mcbsp"); 1440