1 /* 2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor 3 * 4 * Multi-channel Audio Serial Port Driver 5 * 6 * Author: Nirmal Pandey <n-pandey@ti.com>, 7 * Suresh Rajashekara <suresh.r@ti.com> 8 * Steve Chen <schen@.mvista.com> 9 * 10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> 11 * Copyright: (C) 2009 Texas Instruments, India 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License version 2 as 15 * published by the Free Software Foundation. 16 */ 17 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/device.h> 21 #include <linux/slab.h> 22 #include <linux/delay.h> 23 #include <linux/io.h> 24 #include <linux/clk.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/of.h> 27 #include <linux/of_platform.h> 28 #include <linux/of_device.h> 29 #include <linux/platform_data/davinci_asp.h> 30 #include <linux/math64.h> 31 #include <linux/bitmap.h> 32 #include <linux/gpio/driver.h> 33 34 #include <sound/asoundef.h> 35 #include <sound/core.h> 36 #include <sound/pcm.h> 37 #include <sound/pcm_params.h> 38 #include <sound/initval.h> 39 #include <sound/soc.h> 40 #include <sound/dmaengine_pcm.h> 41 42 #include "edma-pcm.h" 43 #include "sdma-pcm.h" 44 #include "davinci-mcasp.h" 45 46 #define MCASP_MAX_AFIFO_DEPTH 64 47 48 static u32 context_regs[] = { 49 DAVINCI_MCASP_TXFMCTL_REG, 50 DAVINCI_MCASP_RXFMCTL_REG, 51 DAVINCI_MCASP_TXFMT_REG, 52 DAVINCI_MCASP_RXFMT_REG, 53 DAVINCI_MCASP_ACLKXCTL_REG, 54 DAVINCI_MCASP_ACLKRCTL_REG, 55 DAVINCI_MCASP_AHCLKXCTL_REG, 56 DAVINCI_MCASP_AHCLKRCTL_REG, 57 DAVINCI_MCASP_PDIR_REG, 58 DAVINCI_MCASP_PFUNC_REG, 59 DAVINCI_MCASP_RXMASK_REG, 60 DAVINCI_MCASP_TXMASK_REG, 61 DAVINCI_MCASP_RXTDM_REG, 62 DAVINCI_MCASP_TXTDM_REG, 63 }; 64 65 struct davinci_mcasp_context { 66 u32 config_regs[ARRAY_SIZE(context_regs)]; 67 u32 afifo_regs[2]; /* for read/write fifo control registers */ 68 u32 *xrsr_regs; /* for serializer configuration */ 69 bool pm_state; 70 }; 71 72 struct davinci_mcasp_ruledata { 73 struct davinci_mcasp *mcasp; 74 int serializers; 75 }; 76 77 struct davinci_mcasp { 78 struct snd_dmaengine_dai_dma_data dma_data[2]; 79 void __iomem *base; 80 u32 fifo_base; 81 struct device *dev; 82 struct snd_pcm_substream *substreams[2]; 83 unsigned int dai_fmt; 84 85 /* McASP specific data */ 86 int tdm_slots; 87 u32 tdm_mask[2]; 88 int slot_width; 89 u8 op_mode; 90 u8 dismod; 91 u8 num_serializer; 92 u8 *serial_dir; 93 u8 version; 94 u8 bclk_div; 95 int streams; 96 u32 irq_request[2]; 97 int dma_request[2]; 98 99 int sysclk_freq; 100 bool bclk_master; 101 102 unsigned long pdir; /* Pin direction bitfield */ 103 104 /* McASP FIFO related */ 105 u8 txnumevt; 106 u8 rxnumevt; 107 108 bool dat_port; 109 110 /* Used for comstraint setting on the second stream */ 111 u32 channels; 112 113 #ifdef CONFIG_GPIOLIB 114 struct gpio_chip gpio_chip; 115 #endif 116 117 #ifdef CONFIG_PM 118 struct davinci_mcasp_context context; 119 #endif 120 121 struct davinci_mcasp_ruledata ruledata[2]; 122 struct snd_pcm_hw_constraint_list chconstr[2]; 123 }; 124 125 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, 126 u32 val) 127 { 128 void __iomem *reg = mcasp->base + offset; 129 __raw_writel(__raw_readl(reg) | val, reg); 130 } 131 132 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, 133 u32 val) 134 { 135 void __iomem *reg = mcasp->base + offset; 136 __raw_writel((__raw_readl(reg) & ~(val)), reg); 137 } 138 139 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, 140 u32 val, u32 mask) 141 { 142 void __iomem *reg = mcasp->base + offset; 143 __raw_writel((__raw_readl(reg) & ~mask) | val, reg); 144 } 145 146 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, 147 u32 val) 148 { 149 __raw_writel(val, mcasp->base + offset); 150 } 151 152 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) 153 { 154 return (u32)__raw_readl(mcasp->base + offset); 155 } 156 157 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) 158 { 159 int i = 0; 160 161 mcasp_set_bits(mcasp, ctl_reg, val); 162 163 /* programming GBLCTL needs to read back from GBLCTL and verfiy */ 164 /* loop count is to avoid the lock-up */ 165 for (i = 0; i < 1000; i++) { 166 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) 167 break; 168 } 169 170 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) 171 printk(KERN_ERR "GBLCTL write error\n"); 172 } 173 174 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) 175 { 176 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); 177 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); 178 179 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; 180 } 181 182 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable) 183 { 184 u32 bit = PIN_BIT_AMUTE; 185 186 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) { 187 if (enable) 188 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 189 else 190 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 191 } 192 } 193 194 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable) 195 { 196 u32 bit; 197 198 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AFSR) { 199 if (enable) 200 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 201 else 202 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 203 } 204 } 205 206 static void mcasp_start_rx(struct davinci_mcasp *mcasp) 207 { 208 if (mcasp->rxnumevt) { /* enable FIFO */ 209 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 210 211 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 212 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); 213 } 214 215 /* Start clocks */ 216 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); 217 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); 218 /* 219 * When ASYNC == 0 the transmit and receive sections operate 220 * synchronously from the transmit clock and frame sync. We need to make 221 * sure that the TX signlas are enabled when starting reception. 222 */ 223 if (mcasp_is_synchronous(mcasp)) { 224 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 225 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 226 } 227 228 /* Activate serializer(s) */ 229 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 230 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); 231 /* Release RX state machine */ 232 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); 233 /* Release Frame Sync generator */ 234 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); 235 if (mcasp_is_synchronous(mcasp)) 236 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 237 238 /* enable receive IRQs */ 239 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, 240 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); 241 } 242 243 static void mcasp_start_tx(struct davinci_mcasp *mcasp) 244 { 245 u32 cnt; 246 247 if (mcasp->txnumevt) { /* enable FIFO */ 248 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 249 250 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 251 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); 252 } 253 254 /* Start clocks */ 255 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 256 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 257 mcasp_set_clk_pdir(mcasp, true); 258 259 /* Activate serializer(s) */ 260 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 261 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); 262 263 /* wait for XDATA to be cleared */ 264 cnt = 0; 265 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) && 266 (cnt < 100000)) 267 cnt++; 268 269 mcasp_set_axr_pdir(mcasp, true); 270 271 /* Release TX state machine */ 272 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); 273 /* Release Frame Sync generator */ 274 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 275 276 /* enable transmit IRQs */ 277 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, 278 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); 279 } 280 281 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) 282 { 283 mcasp->streams++; 284 285 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 286 mcasp_start_tx(mcasp); 287 else 288 mcasp_start_rx(mcasp); 289 } 290 291 static void mcasp_stop_rx(struct davinci_mcasp *mcasp) 292 { 293 /* disable IRQ sources */ 294 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, 295 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); 296 297 /* 298 * In synchronous mode stop the TX clocks if no other stream is 299 * running 300 */ 301 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) { 302 mcasp_set_clk_pdir(mcasp, false); 303 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); 304 } 305 306 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); 307 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 308 309 if (mcasp->rxnumevt) { /* disable FIFO */ 310 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 311 312 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 313 } 314 } 315 316 static void mcasp_stop_tx(struct davinci_mcasp *mcasp) 317 { 318 u32 val = 0; 319 320 /* disable IRQ sources */ 321 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, 322 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); 323 324 /* 325 * In synchronous mode keep TX clocks running if the capture stream is 326 * still running. 327 */ 328 if (mcasp_is_synchronous(mcasp) && mcasp->streams) 329 val = TXHCLKRST | TXCLKRST | TXFSRST; 330 else 331 mcasp_set_clk_pdir(mcasp, false); 332 333 334 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); 335 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 336 337 if (mcasp->txnumevt) { /* disable FIFO */ 338 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 339 340 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 341 } 342 343 mcasp_set_axr_pdir(mcasp, false); 344 } 345 346 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) 347 { 348 mcasp->streams--; 349 350 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 351 mcasp_stop_tx(mcasp); 352 else 353 mcasp_stop_rx(mcasp); 354 } 355 356 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data) 357 { 358 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 359 struct snd_pcm_substream *substream; 360 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]; 361 u32 handled_mask = 0; 362 u32 stat; 363 364 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG); 365 if (stat & XUNDRN & irq_mask) { 366 dev_warn(mcasp->dev, "Transmit buffer underflow\n"); 367 handled_mask |= XUNDRN; 368 369 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]; 370 if (substream) 371 snd_pcm_stop_xrun(substream); 372 } 373 374 if (!handled_mask) 375 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n", 376 stat); 377 378 if (stat & XRERR) 379 handled_mask |= XRERR; 380 381 /* Ack the handled event only */ 382 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask); 383 384 return IRQ_RETVAL(handled_mask); 385 } 386 387 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data) 388 { 389 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 390 struct snd_pcm_substream *substream; 391 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]; 392 u32 handled_mask = 0; 393 u32 stat; 394 395 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG); 396 if (stat & ROVRN & irq_mask) { 397 dev_warn(mcasp->dev, "Receive buffer overflow\n"); 398 handled_mask |= ROVRN; 399 400 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]; 401 if (substream) 402 snd_pcm_stop_xrun(substream); 403 } 404 405 if (!handled_mask) 406 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n", 407 stat); 408 409 if (stat & XRERR) 410 handled_mask |= XRERR; 411 412 /* Ack the handled event only */ 413 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask); 414 415 return IRQ_RETVAL(handled_mask); 416 } 417 418 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data) 419 { 420 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 421 irqreturn_t ret = IRQ_NONE; 422 423 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]) 424 ret = davinci_mcasp_tx_irq_handler(irq, data); 425 426 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]) 427 ret |= davinci_mcasp_rx_irq_handler(irq, data); 428 429 return ret; 430 } 431 432 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, 433 unsigned int fmt) 434 { 435 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 436 int ret = 0; 437 u32 data_delay; 438 bool fs_pol_rising; 439 bool inv_fs = false; 440 441 if (!fmt) 442 return 0; 443 444 pm_runtime_get_sync(mcasp->dev); 445 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 446 case SND_SOC_DAIFMT_DSP_A: 447 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 448 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 449 /* 1st data bit occur one ACLK cycle after the frame sync */ 450 data_delay = 1; 451 break; 452 case SND_SOC_DAIFMT_DSP_B: 453 case SND_SOC_DAIFMT_AC97: 454 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 455 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 456 /* No delay after FS */ 457 data_delay = 0; 458 break; 459 case SND_SOC_DAIFMT_I2S: 460 /* configure a full-word SYNC pulse (LRCLK) */ 461 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 462 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 463 /* 1st data bit occur one ACLK cycle after the frame sync */ 464 data_delay = 1; 465 /* FS need to be inverted */ 466 inv_fs = true; 467 break; 468 case SND_SOC_DAIFMT_LEFT_J: 469 /* configure a full-word SYNC pulse (LRCLK) */ 470 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 471 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 472 /* No delay after FS */ 473 data_delay = 0; 474 break; 475 default: 476 ret = -EINVAL; 477 goto out; 478 } 479 480 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), 481 FSXDLY(3)); 482 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), 483 FSRDLY(3)); 484 485 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 486 case SND_SOC_DAIFMT_CBS_CFS: 487 /* codec is clock and frame slave */ 488 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 489 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 490 491 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 492 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 493 494 /* BCLK */ 495 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); 496 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); 497 /* Frame Sync */ 498 set_bit(PIN_BIT_AFSX, &mcasp->pdir); 499 set_bit(PIN_BIT_AFSR, &mcasp->pdir); 500 501 mcasp->bclk_master = 1; 502 break; 503 case SND_SOC_DAIFMT_CBS_CFM: 504 /* codec is clock slave and frame master */ 505 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 506 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 507 508 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 509 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 510 511 /* BCLK */ 512 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); 513 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); 514 /* Frame Sync */ 515 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); 516 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); 517 518 mcasp->bclk_master = 1; 519 break; 520 case SND_SOC_DAIFMT_CBM_CFS: 521 /* codec is clock master and frame slave */ 522 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 523 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 524 525 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 526 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 527 528 /* BCLK */ 529 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); 530 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); 531 /* Frame Sync */ 532 set_bit(PIN_BIT_AFSX, &mcasp->pdir); 533 set_bit(PIN_BIT_AFSR, &mcasp->pdir); 534 535 mcasp->bclk_master = 0; 536 break; 537 case SND_SOC_DAIFMT_CBM_CFM: 538 /* codec is clock and frame master */ 539 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 540 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 541 542 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 543 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 544 545 /* BCLK */ 546 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); 547 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); 548 /* Frame Sync */ 549 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); 550 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); 551 552 mcasp->bclk_master = 0; 553 break; 554 default: 555 ret = -EINVAL; 556 goto out; 557 } 558 559 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 560 case SND_SOC_DAIFMT_IB_NF: 561 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 562 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 563 fs_pol_rising = true; 564 break; 565 case SND_SOC_DAIFMT_NB_IF: 566 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 567 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 568 fs_pol_rising = false; 569 break; 570 case SND_SOC_DAIFMT_IB_IF: 571 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 572 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 573 fs_pol_rising = false; 574 break; 575 case SND_SOC_DAIFMT_NB_NF: 576 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 577 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 578 fs_pol_rising = true; 579 break; 580 default: 581 ret = -EINVAL; 582 goto out; 583 } 584 585 if (inv_fs) 586 fs_pol_rising = !fs_pol_rising; 587 588 if (fs_pol_rising) { 589 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 590 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 591 } else { 592 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 593 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 594 } 595 596 mcasp->dai_fmt = fmt; 597 out: 598 pm_runtime_put(mcasp->dev); 599 return ret; 600 } 601 602 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id, 603 int div, bool explicit) 604 { 605 pm_runtime_get_sync(mcasp->dev); 606 switch (div_id) { 607 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */ 608 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 609 AHCLKXDIV(div - 1), AHCLKXDIV_MASK); 610 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 611 AHCLKRDIV(div - 1), AHCLKRDIV_MASK); 612 break; 613 614 case MCASP_CLKDIV_BCLK: /* BCLK divider */ 615 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, 616 ACLKXDIV(div - 1), ACLKXDIV_MASK); 617 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, 618 ACLKRDIV(div - 1), ACLKRDIV_MASK); 619 if (explicit) 620 mcasp->bclk_div = div; 621 break; 622 623 case MCASP_CLKDIV_BCLK_FS_RATIO: 624 /* 625 * BCLK/LRCLK ratio descries how many bit-clock cycles 626 * fit into one frame. The clock ratio is given for a 627 * full period of data (for I2S format both left and 628 * right channels), so it has to be divided by number 629 * of tdm-slots (for I2S - divided by 2). 630 * Instead of storing this ratio, we calculate a new 631 * tdm_slot width by dividing the the ratio by the 632 * number of configured tdm slots. 633 */ 634 mcasp->slot_width = div / mcasp->tdm_slots; 635 if (div % mcasp->tdm_slots) 636 dev_warn(mcasp->dev, 637 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots", 638 __func__, div, mcasp->tdm_slots); 639 break; 640 641 default: 642 return -EINVAL; 643 } 644 645 pm_runtime_put(mcasp->dev); 646 return 0; 647 } 648 649 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, 650 int div) 651 { 652 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 653 654 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1); 655 } 656 657 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, 658 unsigned int freq, int dir) 659 { 660 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 661 662 pm_runtime_get_sync(mcasp->dev); 663 if (dir == SND_SOC_CLOCK_OUT) { 664 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); 665 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); 666 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 667 } else { 668 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); 669 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); 670 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 671 } 672 673 mcasp->sysclk_freq = freq; 674 675 pm_runtime_put(mcasp->dev); 676 return 0; 677 } 678 679 /* All serializers must have equal number of channels */ 680 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream, 681 int serializers) 682 { 683 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream]; 684 unsigned int *list = (unsigned int *) cl->list; 685 int slots = mcasp->tdm_slots; 686 int i, count = 0; 687 688 if (mcasp->tdm_mask[stream]) 689 slots = hweight32(mcasp->tdm_mask[stream]); 690 691 for (i = 1; i <= slots; i++) 692 list[count++] = i; 693 694 for (i = 2; i <= serializers; i++) 695 list[count++] = i*slots; 696 697 cl->count = count; 698 699 return 0; 700 } 701 702 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp) 703 { 704 int rx_serializers = 0, tx_serializers = 0, ret, i; 705 706 for (i = 0; i < mcasp->num_serializer; i++) 707 if (mcasp->serial_dir[i] == TX_MODE) 708 tx_serializers++; 709 else if (mcasp->serial_dir[i] == RX_MODE) 710 rx_serializers++; 711 712 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK, 713 tx_serializers); 714 if (ret) 715 return ret; 716 717 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE, 718 rx_serializers); 719 720 return ret; 721 } 722 723 724 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai, 725 unsigned int tx_mask, 726 unsigned int rx_mask, 727 int slots, int slot_width) 728 { 729 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 730 731 dev_dbg(mcasp->dev, 732 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n", 733 __func__, tx_mask, rx_mask, slots, slot_width); 734 735 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) { 736 dev_err(mcasp->dev, 737 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n", 738 tx_mask, rx_mask, slots); 739 return -EINVAL; 740 } 741 742 if (slot_width && 743 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) { 744 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n", 745 __func__, slot_width); 746 return -EINVAL; 747 } 748 749 mcasp->tdm_slots = slots; 750 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask; 751 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask; 752 mcasp->slot_width = slot_width; 753 754 return davinci_mcasp_set_ch_constraints(mcasp); 755 } 756 757 static int davinci_config_channel_size(struct davinci_mcasp *mcasp, 758 int sample_width) 759 { 760 u32 fmt; 761 u32 tx_rotate = (sample_width / 4) & 0x7; 762 u32 mask = (1ULL << sample_width) - 1; 763 u32 slot_width = sample_width; 764 765 /* 766 * For captured data we should not rotate, inversion and masking is 767 * enoguh to get the data to the right position: 768 * Format data from bus after reverse (XRBUF) 769 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB| 770 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| 771 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| 772 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB| 773 */ 774 u32 rx_rotate = 0; 775 776 /* 777 * Setting the tdm slot width either with set_clkdiv() or 778 * set_tdm_slot() allows us to for example send 32 bits per 779 * channel to the codec, while only 16 of them carry audio 780 * payload. 781 */ 782 if (mcasp->slot_width) { 783 /* 784 * When we have more bclk then it is needed for the 785 * data, we need to use the rotation to move the 786 * received samples to have correct alignment. 787 */ 788 slot_width = mcasp->slot_width; 789 rx_rotate = (slot_width - sample_width) / 4; 790 } 791 792 /* mapping of the XSSZ bit-field as described in the datasheet */ 793 fmt = (slot_width >> 1) - 1; 794 795 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 796 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), 797 RXSSZ(0x0F)); 798 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), 799 TXSSZ(0x0F)); 800 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), 801 TXROT(7)); 802 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), 803 RXROT(7)); 804 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); 805 } 806 807 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); 808 809 return 0; 810 } 811 812 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, 813 int period_words, int channels) 814 { 815 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; 816 int i; 817 u8 tx_ser = 0; 818 u8 rx_ser = 0; 819 u8 slots = mcasp->tdm_slots; 820 u8 max_active_serializers = (channels + slots - 1) / slots; 821 int active_serializers, numevt; 822 u32 reg; 823 /* Default configuration */ 824 if (mcasp->version < MCASP_VERSION_3) 825 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); 826 827 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 828 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 829 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 830 } else { 831 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 832 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); 833 } 834 835 for (i = 0; i < mcasp->num_serializer; i++) { 836 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 837 mcasp->serial_dir[i]); 838 if (mcasp->serial_dir[i] == TX_MODE && 839 tx_ser < max_active_serializers) { 840 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 841 mcasp->dismod, DISMOD_MASK); 842 set_bit(PIN_BIT_AXR(i), &mcasp->pdir); 843 tx_ser++; 844 } else if (mcasp->serial_dir[i] == RX_MODE && 845 rx_ser < max_active_serializers) { 846 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 847 rx_ser++; 848 } else if (mcasp->serial_dir[i] == INACTIVE_MODE) { 849 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 850 SRMOD_INACTIVE, SRMOD_MASK); 851 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 852 } else if (mcasp->serial_dir[i] == TX_MODE) { 853 /* Unused TX pins, clear PDIR */ 854 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 855 mcasp->dismod, DISMOD_MASK); 856 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 857 } 858 } 859 860 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 861 active_serializers = tx_ser; 862 numevt = mcasp->txnumevt; 863 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 864 } else { 865 active_serializers = rx_ser; 866 numevt = mcasp->rxnumevt; 867 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 868 } 869 870 if (active_serializers < max_active_serializers) { 871 dev_warn(mcasp->dev, "stream has more channels (%d) than are " 872 "enabled in mcasp (%d)\n", channels, 873 active_serializers * slots); 874 return -EINVAL; 875 } 876 877 /* AFIFO is not in use */ 878 if (!numevt) { 879 /* Configure the burst size for platform drivers */ 880 if (active_serializers > 1) { 881 /* 882 * If more than one serializers are in use we have one 883 * DMA request to provide data for all serializers. 884 * For example if three serializers are enabled the DMA 885 * need to transfer three words per DMA request. 886 */ 887 dma_data->maxburst = active_serializers; 888 } else { 889 dma_data->maxburst = 0; 890 } 891 return 0; 892 } 893 894 if (period_words % active_serializers) { 895 dev_err(mcasp->dev, "Invalid combination of period words and " 896 "active serializers: %d, %d\n", period_words, 897 active_serializers); 898 return -EINVAL; 899 } 900 901 /* 902 * Calculate the optimal AFIFO depth for platform side: 903 * The number of words for numevt need to be in steps of active 904 * serializers. 905 */ 906 numevt = (numevt / active_serializers) * active_serializers; 907 908 while (period_words % numevt && numevt > 0) 909 numevt -= active_serializers; 910 if (numevt <= 0) 911 numevt = active_serializers; 912 913 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); 914 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); 915 916 /* Configure the burst size for platform drivers */ 917 if (numevt == 1) 918 numevt = 0; 919 dma_data->maxburst = numevt; 920 921 return 0; 922 } 923 924 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream, 925 int channels) 926 { 927 int i, active_slots; 928 int total_slots; 929 int active_serializers; 930 u32 mask = 0; 931 u32 busel = 0; 932 933 total_slots = mcasp->tdm_slots; 934 935 /* 936 * If more than one serializer is needed, then use them with 937 * all the specified tdm_slots. Otherwise, one serializer can 938 * cope with the transaction using just as many slots as there 939 * are channels in the stream. 940 */ 941 if (mcasp->tdm_mask[stream]) { 942 active_slots = hweight32(mcasp->tdm_mask[stream]); 943 active_serializers = (channels + active_slots - 1) / 944 active_slots; 945 if (active_serializers == 1) { 946 active_slots = channels; 947 for (i = 0; i < total_slots; i++) { 948 if ((1 << i) & mcasp->tdm_mask[stream]) { 949 mask |= (1 << i); 950 if (--active_slots <= 0) 951 break; 952 } 953 } 954 } 955 } else { 956 active_serializers = (channels + total_slots - 1) / total_slots; 957 if (active_serializers == 1) 958 active_slots = channels; 959 else 960 active_slots = total_slots; 961 962 for (i = 0; i < active_slots; i++) 963 mask |= (1 << i); 964 } 965 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); 966 967 if (!mcasp->dat_port) 968 busel = TXSEL; 969 970 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 971 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); 972 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); 973 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 974 FSXMOD(total_slots), FSXMOD(0x1FF)); 975 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) { 976 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); 977 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); 978 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, 979 FSRMOD(total_slots), FSRMOD(0x1FF)); 980 /* 981 * If McASP is set to be TX/RX synchronous and the playback is 982 * not running already we need to configure the TX slots in 983 * order to have correct FSX on the bus 984 */ 985 if (mcasp_is_synchronous(mcasp) && !mcasp->channels) 986 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 987 FSXMOD(total_slots), FSXMOD(0x1FF)); 988 } 989 990 return 0; 991 } 992 993 /* S/PDIF */ 994 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, 995 unsigned int rate) 996 { 997 u32 cs_value = 0; 998 u8 *cs_bytes = (u8*) &cs_value; 999 1000 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 1001 and LSB first */ 1002 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); 1003 1004 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ 1005 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); 1006 1007 /* Set the TX tdm : for all the slots */ 1008 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); 1009 1010 /* Set the TX clock controls : div = 1 and internal */ 1011 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); 1012 1013 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 1014 1015 /* Only 44100 and 48000 are valid, both have the same setting */ 1016 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); 1017 1018 /* Enable the DIT */ 1019 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); 1020 1021 /* Set S/PDIF channel status bits */ 1022 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT; 1023 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER; 1024 1025 switch (rate) { 1026 case 22050: 1027 cs_bytes[3] |= IEC958_AES3_CON_FS_22050; 1028 break; 1029 case 24000: 1030 cs_bytes[3] |= IEC958_AES3_CON_FS_24000; 1031 break; 1032 case 32000: 1033 cs_bytes[3] |= IEC958_AES3_CON_FS_32000; 1034 break; 1035 case 44100: 1036 cs_bytes[3] |= IEC958_AES3_CON_FS_44100; 1037 break; 1038 case 48000: 1039 cs_bytes[3] |= IEC958_AES3_CON_FS_48000; 1040 break; 1041 case 88200: 1042 cs_bytes[3] |= IEC958_AES3_CON_FS_88200; 1043 break; 1044 case 96000: 1045 cs_bytes[3] |= IEC958_AES3_CON_FS_96000; 1046 break; 1047 case 176400: 1048 cs_bytes[3] |= IEC958_AES3_CON_FS_176400; 1049 break; 1050 case 192000: 1051 cs_bytes[3] |= IEC958_AES3_CON_FS_192000; 1052 break; 1053 default: 1054 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate); 1055 return -EINVAL; 1056 } 1057 1058 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value); 1059 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value); 1060 1061 return 0; 1062 } 1063 1064 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp, 1065 unsigned int bclk_freq, bool set) 1066 { 1067 int error_ppm; 1068 unsigned int sysclk_freq = mcasp->sysclk_freq; 1069 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG); 1070 int div = sysclk_freq / bclk_freq; 1071 int rem = sysclk_freq % bclk_freq; 1072 int aux_div = 1; 1073 1074 if (div > (ACLKXDIV_MASK + 1)) { 1075 if (reg & AHCLKXE) { 1076 aux_div = div / (ACLKXDIV_MASK + 1); 1077 if (div % (ACLKXDIV_MASK + 1)) 1078 aux_div++; 1079 1080 sysclk_freq /= aux_div; 1081 div = sysclk_freq / bclk_freq; 1082 rem = sysclk_freq % bclk_freq; 1083 } else if (set) { 1084 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n", 1085 sysclk_freq); 1086 } 1087 } 1088 1089 if (rem != 0) { 1090 if (div == 0 || 1091 ((sysclk_freq / div) - bclk_freq) > 1092 (bclk_freq - (sysclk_freq / (div+1)))) { 1093 div++; 1094 rem = rem - bclk_freq; 1095 } 1096 } 1097 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem, 1098 (int)bclk_freq)) / div - 1000000; 1099 1100 if (set) { 1101 if (error_ppm) 1102 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n", 1103 error_ppm); 1104 1105 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0); 1106 if (reg & AHCLKXE) 1107 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK, 1108 aux_div, 0); 1109 } 1110 1111 return error_ppm; 1112 } 1113 1114 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp) 1115 { 1116 if (!mcasp->txnumevt) 1117 return 0; 1118 1119 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET); 1120 } 1121 1122 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp) 1123 { 1124 if (!mcasp->rxnumevt) 1125 return 0; 1126 1127 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET); 1128 } 1129 1130 static snd_pcm_sframes_t davinci_mcasp_delay( 1131 struct snd_pcm_substream *substream, 1132 struct snd_soc_dai *cpu_dai) 1133 { 1134 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1135 u32 fifo_use; 1136 1137 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1138 fifo_use = davinci_mcasp_tx_delay(mcasp); 1139 else 1140 fifo_use = davinci_mcasp_rx_delay(mcasp); 1141 1142 /* 1143 * Divide the used locations with the channel count to get the 1144 * FIFO usage in samples (don't care about partial samples in the 1145 * buffer). 1146 */ 1147 return fifo_use / substream->runtime->channels; 1148 } 1149 1150 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, 1151 struct snd_pcm_hw_params *params, 1152 struct snd_soc_dai *cpu_dai) 1153 { 1154 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1155 int word_length; 1156 int channels = params_channels(params); 1157 int period_size = params_period_size(params); 1158 int ret; 1159 1160 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt); 1161 if (ret) 1162 return ret; 1163 1164 /* 1165 * If mcasp is BCLK master, and a BCLK divider was not provided by 1166 * the machine driver, we need to calculate the ratio. 1167 */ 1168 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { 1169 int slots = mcasp->tdm_slots; 1170 int rate = params_rate(params); 1171 int sbits = params_width(params); 1172 1173 if (mcasp->slot_width) 1174 sbits = mcasp->slot_width; 1175 1176 davinci_mcasp_calc_clk_div(mcasp, rate * sbits * slots, true); 1177 } 1178 1179 ret = mcasp_common_hw_param(mcasp, substream->stream, 1180 period_size * channels, channels); 1181 if (ret) 1182 return ret; 1183 1184 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1185 ret = mcasp_dit_hw_param(mcasp, params_rate(params)); 1186 else 1187 ret = mcasp_i2s_hw_param(mcasp, substream->stream, 1188 channels); 1189 1190 if (ret) 1191 return ret; 1192 1193 switch (params_format(params)) { 1194 case SNDRV_PCM_FORMAT_U8: 1195 case SNDRV_PCM_FORMAT_S8: 1196 word_length = 8; 1197 break; 1198 1199 case SNDRV_PCM_FORMAT_U16_LE: 1200 case SNDRV_PCM_FORMAT_S16_LE: 1201 word_length = 16; 1202 break; 1203 1204 case SNDRV_PCM_FORMAT_U24_3LE: 1205 case SNDRV_PCM_FORMAT_S24_3LE: 1206 word_length = 24; 1207 break; 1208 1209 case SNDRV_PCM_FORMAT_U24_LE: 1210 case SNDRV_PCM_FORMAT_S24_LE: 1211 word_length = 24; 1212 break; 1213 1214 case SNDRV_PCM_FORMAT_U32_LE: 1215 case SNDRV_PCM_FORMAT_S32_LE: 1216 word_length = 32; 1217 break; 1218 1219 default: 1220 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); 1221 return -EINVAL; 1222 } 1223 1224 davinci_config_channel_size(mcasp, word_length); 1225 1226 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) 1227 mcasp->channels = channels; 1228 1229 return 0; 1230 } 1231 1232 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, 1233 int cmd, struct snd_soc_dai *cpu_dai) 1234 { 1235 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1236 int ret = 0; 1237 1238 switch (cmd) { 1239 case SNDRV_PCM_TRIGGER_RESUME: 1240 case SNDRV_PCM_TRIGGER_START: 1241 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1242 davinci_mcasp_start(mcasp, substream->stream); 1243 break; 1244 case SNDRV_PCM_TRIGGER_SUSPEND: 1245 case SNDRV_PCM_TRIGGER_STOP: 1246 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1247 davinci_mcasp_stop(mcasp, substream->stream); 1248 break; 1249 1250 default: 1251 ret = -EINVAL; 1252 } 1253 1254 return ret; 1255 } 1256 1257 static const unsigned int davinci_mcasp_dai_rates[] = { 1258 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 1259 88200, 96000, 176400, 192000, 1260 }; 1261 1262 #define DAVINCI_MAX_RATE_ERROR_PPM 1000 1263 1264 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params, 1265 struct snd_pcm_hw_rule *rule) 1266 { 1267 struct davinci_mcasp_ruledata *rd = rule->private; 1268 struct snd_interval *ri = 1269 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 1270 int sbits = params_width(params); 1271 int slots = rd->mcasp->tdm_slots; 1272 struct snd_interval range; 1273 int i; 1274 1275 if (rd->mcasp->slot_width) 1276 sbits = rd->mcasp->slot_width; 1277 1278 snd_interval_any(&range); 1279 range.empty = 1; 1280 1281 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) { 1282 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) { 1283 uint bclk_freq = sbits*slots* 1284 davinci_mcasp_dai_rates[i]; 1285 int ppm; 1286 1287 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, 1288 false); 1289 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { 1290 if (range.empty) { 1291 range.min = davinci_mcasp_dai_rates[i]; 1292 range.empty = 0; 1293 } 1294 range.max = davinci_mcasp_dai_rates[i]; 1295 } 1296 } 1297 } 1298 1299 dev_dbg(rd->mcasp->dev, 1300 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n", 1301 ri->min, ri->max, range.min, range.max, sbits, slots); 1302 1303 return snd_interval_refine(hw_param_interval(params, rule->var), 1304 &range); 1305 } 1306 1307 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params, 1308 struct snd_pcm_hw_rule *rule) 1309 { 1310 struct davinci_mcasp_ruledata *rd = rule->private; 1311 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1312 struct snd_mask nfmt; 1313 int rate = params_rate(params); 1314 int slots = rd->mcasp->tdm_slots; 1315 int i, count = 0; 1316 1317 snd_mask_none(&nfmt); 1318 1319 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) { 1320 if (snd_mask_test(fmt, i)) { 1321 uint sbits = snd_pcm_format_width(i); 1322 int ppm; 1323 1324 if (rd->mcasp->slot_width) 1325 sbits = rd->mcasp->slot_width; 1326 1327 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, 1328 sbits * slots * rate, 1329 false); 1330 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { 1331 snd_mask_set(&nfmt, i); 1332 count++; 1333 } 1334 } 1335 } 1336 dev_dbg(rd->mcasp->dev, 1337 "%d possible sample format for %d Hz and %d tdm slots\n", 1338 count, rate, slots); 1339 1340 return snd_mask_refine(fmt, &nfmt); 1341 } 1342 1343 static int davinci_mcasp_hw_rule_min_periodsize( 1344 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) 1345 { 1346 struct snd_interval *period_size = hw_param_interval(params, 1347 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 1348 struct snd_interval frames; 1349 1350 snd_interval_any(&frames); 1351 frames.min = 64; 1352 frames.integer = 1; 1353 1354 return snd_interval_refine(period_size, &frames); 1355 } 1356 1357 static int davinci_mcasp_startup(struct snd_pcm_substream *substream, 1358 struct snd_soc_dai *cpu_dai) 1359 { 1360 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1361 struct davinci_mcasp_ruledata *ruledata = 1362 &mcasp->ruledata[substream->stream]; 1363 u32 max_channels = 0; 1364 int i, dir; 1365 int tdm_slots = mcasp->tdm_slots; 1366 1367 /* Do not allow more then one stream per direction */ 1368 if (mcasp->substreams[substream->stream]) 1369 return -EBUSY; 1370 1371 mcasp->substreams[substream->stream] = substream; 1372 1373 if (mcasp->tdm_mask[substream->stream]) 1374 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]); 1375 1376 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1377 return 0; 1378 1379 /* 1380 * Limit the maximum allowed channels for the first stream: 1381 * number of serializers for the direction * tdm slots per serializer 1382 */ 1383 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1384 dir = TX_MODE; 1385 else 1386 dir = RX_MODE; 1387 1388 for (i = 0; i < mcasp->num_serializer; i++) { 1389 if (mcasp->serial_dir[i] == dir) 1390 max_channels++; 1391 } 1392 ruledata->serializers = max_channels; 1393 max_channels *= tdm_slots; 1394 /* 1395 * If the already active stream has less channels than the calculated 1396 * limnit based on the seirializers * tdm_slots, we need to use that as 1397 * a constraint for the second stream. 1398 * Otherwise (first stream or less allowed channels) we use the 1399 * calculated constraint. 1400 */ 1401 if (mcasp->channels && mcasp->channels < max_channels) 1402 max_channels = mcasp->channels; 1403 /* 1404 * But we can always allow channels upto the amount of 1405 * the available tdm_slots. 1406 */ 1407 if (max_channels < tdm_slots) 1408 max_channels = tdm_slots; 1409 1410 snd_pcm_hw_constraint_minmax(substream->runtime, 1411 SNDRV_PCM_HW_PARAM_CHANNELS, 1412 0, max_channels); 1413 1414 snd_pcm_hw_constraint_list(substream->runtime, 1415 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1416 &mcasp->chconstr[substream->stream]); 1417 1418 if (mcasp->slot_width) 1419 snd_pcm_hw_constraint_minmax(substream->runtime, 1420 SNDRV_PCM_HW_PARAM_SAMPLE_BITS, 1421 8, mcasp->slot_width); 1422 1423 /* 1424 * If we rely on implicit BCLK divider setting we should 1425 * set constraints based on what we can provide. 1426 */ 1427 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { 1428 int ret; 1429 1430 ruledata->mcasp = mcasp; 1431 1432 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1433 SNDRV_PCM_HW_PARAM_RATE, 1434 davinci_mcasp_hw_rule_rate, 1435 ruledata, 1436 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1437 if (ret) 1438 return ret; 1439 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1440 SNDRV_PCM_HW_PARAM_FORMAT, 1441 davinci_mcasp_hw_rule_format, 1442 ruledata, 1443 SNDRV_PCM_HW_PARAM_RATE, -1); 1444 if (ret) 1445 return ret; 1446 } 1447 1448 snd_pcm_hw_rule_add(substream->runtime, 0, 1449 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 1450 davinci_mcasp_hw_rule_min_periodsize, NULL, 1451 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1); 1452 1453 return 0; 1454 } 1455 1456 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream, 1457 struct snd_soc_dai *cpu_dai) 1458 { 1459 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1460 1461 mcasp->substreams[substream->stream] = NULL; 1462 1463 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1464 return; 1465 1466 if (!cpu_dai->active) 1467 mcasp->channels = 0; 1468 } 1469 1470 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { 1471 .startup = davinci_mcasp_startup, 1472 .shutdown = davinci_mcasp_shutdown, 1473 .trigger = davinci_mcasp_trigger, 1474 .delay = davinci_mcasp_delay, 1475 .hw_params = davinci_mcasp_hw_params, 1476 .set_fmt = davinci_mcasp_set_dai_fmt, 1477 .set_clkdiv = davinci_mcasp_set_clkdiv, 1478 .set_sysclk = davinci_mcasp_set_sysclk, 1479 .set_tdm_slot = davinci_mcasp_set_tdm_slot, 1480 }; 1481 1482 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) 1483 { 1484 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 1485 1486 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; 1487 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; 1488 1489 return 0; 1490 } 1491 1492 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 1493 1494 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ 1495 SNDRV_PCM_FMTBIT_U8 | \ 1496 SNDRV_PCM_FMTBIT_S16_LE | \ 1497 SNDRV_PCM_FMTBIT_U16_LE | \ 1498 SNDRV_PCM_FMTBIT_S24_LE | \ 1499 SNDRV_PCM_FMTBIT_U24_LE | \ 1500 SNDRV_PCM_FMTBIT_S24_3LE | \ 1501 SNDRV_PCM_FMTBIT_U24_3LE | \ 1502 SNDRV_PCM_FMTBIT_S32_LE | \ 1503 SNDRV_PCM_FMTBIT_U32_LE) 1504 1505 static struct snd_soc_dai_driver davinci_mcasp_dai[] = { 1506 { 1507 .name = "davinci-mcasp.0", 1508 .probe = davinci_mcasp_dai_probe, 1509 .playback = { 1510 .channels_min = 1, 1511 .channels_max = 32 * 16, 1512 .rates = DAVINCI_MCASP_RATES, 1513 .formats = DAVINCI_MCASP_PCM_FMTS, 1514 }, 1515 .capture = { 1516 .channels_min = 1, 1517 .channels_max = 32 * 16, 1518 .rates = DAVINCI_MCASP_RATES, 1519 .formats = DAVINCI_MCASP_PCM_FMTS, 1520 }, 1521 .ops = &davinci_mcasp_dai_ops, 1522 1523 .symmetric_samplebits = 1, 1524 .symmetric_rates = 1, 1525 }, 1526 { 1527 .name = "davinci-mcasp.1", 1528 .probe = davinci_mcasp_dai_probe, 1529 .playback = { 1530 .channels_min = 1, 1531 .channels_max = 384, 1532 .rates = DAVINCI_MCASP_RATES, 1533 .formats = DAVINCI_MCASP_PCM_FMTS, 1534 }, 1535 .ops = &davinci_mcasp_dai_ops, 1536 }, 1537 1538 }; 1539 1540 static const struct snd_soc_component_driver davinci_mcasp_component = { 1541 .name = "davinci-mcasp", 1542 }; 1543 1544 /* Some HW specific values and defaults. The rest is filled in from DT. */ 1545 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { 1546 .tx_dma_offset = 0x400, 1547 .rx_dma_offset = 0x400, 1548 .version = MCASP_VERSION_1, 1549 }; 1550 1551 static struct davinci_mcasp_pdata da830_mcasp_pdata = { 1552 .tx_dma_offset = 0x2000, 1553 .rx_dma_offset = 0x2000, 1554 .version = MCASP_VERSION_2, 1555 }; 1556 1557 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { 1558 .tx_dma_offset = 0, 1559 .rx_dma_offset = 0, 1560 .version = MCASP_VERSION_3, 1561 }; 1562 1563 static struct davinci_mcasp_pdata dra7_mcasp_pdata = { 1564 /* The CFG port offset will be calculated if it is needed */ 1565 .tx_dma_offset = 0, 1566 .rx_dma_offset = 0, 1567 .version = MCASP_VERSION_4, 1568 }; 1569 1570 static const struct of_device_id mcasp_dt_ids[] = { 1571 { 1572 .compatible = "ti,dm646x-mcasp-audio", 1573 .data = &dm646x_mcasp_pdata, 1574 }, 1575 { 1576 .compatible = "ti,da830-mcasp-audio", 1577 .data = &da830_mcasp_pdata, 1578 }, 1579 { 1580 .compatible = "ti,am33xx-mcasp-audio", 1581 .data = &am33xx_mcasp_pdata, 1582 }, 1583 { 1584 .compatible = "ti,dra7-mcasp-audio", 1585 .data = &dra7_mcasp_pdata, 1586 }, 1587 { /* sentinel */ } 1588 }; 1589 MODULE_DEVICE_TABLE(of, mcasp_dt_ids); 1590 1591 static int mcasp_reparent_fck(struct platform_device *pdev) 1592 { 1593 struct device_node *node = pdev->dev.of_node; 1594 struct clk *gfclk, *parent_clk; 1595 const char *parent_name; 1596 int ret; 1597 1598 if (!node) 1599 return 0; 1600 1601 parent_name = of_get_property(node, "fck_parent", NULL); 1602 if (!parent_name) 1603 return 0; 1604 1605 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n"); 1606 1607 gfclk = clk_get(&pdev->dev, "fck"); 1608 if (IS_ERR(gfclk)) { 1609 dev_err(&pdev->dev, "failed to get fck\n"); 1610 return PTR_ERR(gfclk); 1611 } 1612 1613 parent_clk = clk_get(NULL, parent_name); 1614 if (IS_ERR(parent_clk)) { 1615 dev_err(&pdev->dev, "failed to get parent clock\n"); 1616 ret = PTR_ERR(parent_clk); 1617 goto err1; 1618 } 1619 1620 ret = clk_set_parent(gfclk, parent_clk); 1621 if (ret) { 1622 dev_err(&pdev->dev, "failed to reparent fck\n"); 1623 goto err2; 1624 } 1625 1626 err2: 1627 clk_put(parent_clk); 1628 err1: 1629 clk_put(gfclk); 1630 return ret; 1631 } 1632 1633 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of( 1634 struct platform_device *pdev) 1635 { 1636 struct device_node *np = pdev->dev.of_node; 1637 struct davinci_mcasp_pdata *pdata = NULL; 1638 const struct of_device_id *match = 1639 of_match_device(mcasp_dt_ids, &pdev->dev); 1640 struct of_phandle_args dma_spec; 1641 1642 const u32 *of_serial_dir32; 1643 u32 val; 1644 int i, ret = 0; 1645 1646 if (pdev->dev.platform_data) { 1647 pdata = pdev->dev.platform_data; 1648 pdata->dismod = DISMOD_LOW; 1649 return pdata; 1650 } else if (match) { 1651 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata), 1652 GFP_KERNEL); 1653 if (!pdata) { 1654 ret = -ENOMEM; 1655 return pdata; 1656 } 1657 } else { 1658 /* control shouldn't reach here. something is wrong */ 1659 ret = -EINVAL; 1660 goto nodata; 1661 } 1662 1663 ret = of_property_read_u32(np, "op-mode", &val); 1664 if (ret >= 0) 1665 pdata->op_mode = val; 1666 1667 ret = of_property_read_u32(np, "tdm-slots", &val); 1668 if (ret >= 0) { 1669 if (val < 2 || val > 32) { 1670 dev_err(&pdev->dev, 1671 "tdm-slots must be in rage [2-32]\n"); 1672 ret = -EINVAL; 1673 goto nodata; 1674 } 1675 1676 pdata->tdm_slots = val; 1677 } 1678 1679 of_serial_dir32 = of_get_property(np, "serial-dir", &val); 1680 val /= sizeof(u32); 1681 if (of_serial_dir32) { 1682 u8 *of_serial_dir = devm_kzalloc(&pdev->dev, 1683 (sizeof(*of_serial_dir) * val), 1684 GFP_KERNEL); 1685 if (!of_serial_dir) { 1686 ret = -ENOMEM; 1687 goto nodata; 1688 } 1689 1690 for (i = 0; i < val; i++) 1691 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); 1692 1693 pdata->num_serializer = val; 1694 pdata->serial_dir = of_serial_dir; 1695 } 1696 1697 ret = of_property_match_string(np, "dma-names", "tx"); 1698 if (ret < 0) 1699 goto nodata; 1700 1701 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, 1702 &dma_spec); 1703 if (ret < 0) 1704 goto nodata; 1705 1706 pdata->tx_dma_channel = dma_spec.args[0]; 1707 1708 /* RX is not valid in DIT mode */ 1709 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) { 1710 ret = of_property_match_string(np, "dma-names", "rx"); 1711 if (ret < 0) 1712 goto nodata; 1713 1714 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, 1715 &dma_spec); 1716 if (ret < 0) 1717 goto nodata; 1718 1719 pdata->rx_dma_channel = dma_spec.args[0]; 1720 } 1721 1722 ret = of_property_read_u32(np, "tx-num-evt", &val); 1723 if (ret >= 0) 1724 pdata->txnumevt = val; 1725 1726 ret = of_property_read_u32(np, "rx-num-evt", &val); 1727 if (ret >= 0) 1728 pdata->rxnumevt = val; 1729 1730 ret = of_property_read_u32(np, "sram-size-playback", &val); 1731 if (ret >= 0) 1732 pdata->sram_size_playback = val; 1733 1734 ret = of_property_read_u32(np, "sram-size-capture", &val); 1735 if (ret >= 0) 1736 pdata->sram_size_capture = val; 1737 1738 ret = of_property_read_u32(np, "dismod", &val); 1739 if (ret >= 0) { 1740 if (val == 0 || val == 2 || val == 3) { 1741 pdata->dismod = DISMOD_VAL(val); 1742 } else { 1743 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val); 1744 pdata->dismod = DISMOD_LOW; 1745 } 1746 } else { 1747 pdata->dismod = DISMOD_LOW; 1748 } 1749 1750 return pdata; 1751 1752 nodata: 1753 if (ret < 0) { 1754 dev_err(&pdev->dev, "Error populating platform data, err %d\n", 1755 ret); 1756 pdata = NULL; 1757 } 1758 return pdata; 1759 } 1760 1761 enum { 1762 PCM_EDMA, 1763 PCM_SDMA, 1764 }; 1765 static const char *sdma_prefix = "ti,omap"; 1766 1767 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp) 1768 { 1769 struct dma_chan *chan; 1770 const char *tmp; 1771 int ret = PCM_EDMA; 1772 1773 if (!mcasp->dev->of_node) 1774 return PCM_EDMA; 1775 1776 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data; 1777 chan = dma_request_slave_channel_reason(mcasp->dev, tmp); 1778 if (IS_ERR(chan)) { 1779 if (PTR_ERR(chan) != -EPROBE_DEFER) 1780 dev_err(mcasp->dev, 1781 "Can't verify DMA configuration (%ld)\n", 1782 PTR_ERR(chan)); 1783 return PTR_ERR(chan); 1784 } 1785 if (WARN_ON(!chan->device || !chan->device->dev)) 1786 return -EINVAL; 1787 1788 if (chan->device->dev->of_node) 1789 ret = of_property_read_string(chan->device->dev->of_node, 1790 "compatible", &tmp); 1791 else 1792 dev_dbg(mcasp->dev, "DMA controller has no of-node\n"); 1793 1794 dma_release_channel(chan); 1795 if (ret) 1796 return ret; 1797 1798 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp); 1799 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix))) 1800 return PCM_SDMA; 1801 1802 return PCM_EDMA; 1803 } 1804 1805 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata) 1806 { 1807 int i; 1808 u32 offset = 0; 1809 1810 if (pdata->version != MCASP_VERSION_4) 1811 return pdata->tx_dma_offset; 1812 1813 for (i = 0; i < pdata->num_serializer; i++) { 1814 if (pdata->serial_dir[i] == TX_MODE) { 1815 if (!offset) { 1816 offset = DAVINCI_MCASP_TXBUF_REG(i); 1817 } else { 1818 pr_err("%s: Only one serializer allowed!\n", 1819 __func__); 1820 break; 1821 } 1822 } 1823 } 1824 1825 return offset; 1826 } 1827 1828 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata) 1829 { 1830 int i; 1831 u32 offset = 0; 1832 1833 if (pdata->version != MCASP_VERSION_4) 1834 return pdata->rx_dma_offset; 1835 1836 for (i = 0; i < pdata->num_serializer; i++) { 1837 if (pdata->serial_dir[i] == RX_MODE) { 1838 if (!offset) { 1839 offset = DAVINCI_MCASP_RXBUF_REG(i); 1840 } else { 1841 pr_err("%s: Only one serializer allowed!\n", 1842 __func__); 1843 break; 1844 } 1845 } 1846 } 1847 1848 return offset; 1849 } 1850 1851 #ifdef CONFIG_GPIOLIB 1852 static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset) 1853 { 1854 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1855 1856 if (mcasp->num_serializer && offset < mcasp->num_serializer && 1857 mcasp->serial_dir[offset] != INACTIVE_MODE) { 1858 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset); 1859 return -EBUSY; 1860 } 1861 1862 /* Do not change the PIN yet */ 1863 1864 return pm_runtime_get_sync(mcasp->dev); 1865 } 1866 1867 static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset) 1868 { 1869 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1870 1871 /* Set the direction to input */ 1872 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 1873 1874 /* Set the pin as McASP pin */ 1875 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 1876 1877 pm_runtime_put_sync(mcasp->dev); 1878 } 1879 1880 static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip, 1881 unsigned offset, int value) 1882 { 1883 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1884 u32 val; 1885 1886 if (value) 1887 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 1888 else 1889 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 1890 1891 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); 1892 if (!(val & BIT(offset))) { 1893 /* Set the pin as GPIO pin */ 1894 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 1895 1896 /* Set the direction to output */ 1897 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 1898 } 1899 1900 return 0; 1901 } 1902 1903 static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset, 1904 int value) 1905 { 1906 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1907 1908 if (value) 1909 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 1910 else 1911 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 1912 } 1913 1914 static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip, 1915 unsigned offset) 1916 { 1917 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1918 u32 val; 1919 1920 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); 1921 if (!(val & BIT(offset))) { 1922 /* Set the direction to input */ 1923 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 1924 1925 /* Set the pin as GPIO pin */ 1926 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 1927 } 1928 1929 return 0; 1930 } 1931 1932 static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset) 1933 { 1934 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1935 u32 val; 1936 1937 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG); 1938 if (val & BIT(offset)) 1939 return 1; 1940 1941 return 0; 1942 } 1943 1944 static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip, 1945 unsigned offset) 1946 { 1947 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 1948 u32 val; 1949 1950 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG); 1951 if (val & BIT(offset)) 1952 return 0; 1953 1954 return 1; 1955 } 1956 1957 static const struct gpio_chip davinci_mcasp_template_chip = { 1958 .owner = THIS_MODULE, 1959 .request = davinci_mcasp_gpio_request, 1960 .free = davinci_mcasp_gpio_free, 1961 .direction_output = davinci_mcasp_gpio_direction_out, 1962 .set = davinci_mcasp_gpio_set, 1963 .direction_input = davinci_mcasp_gpio_direction_in, 1964 .get = davinci_mcasp_gpio_get, 1965 .get_direction = davinci_mcasp_gpio_get_direction, 1966 .base = -1, 1967 .ngpio = 32, 1968 }; 1969 1970 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) 1971 { 1972 if (!of_property_read_bool(mcasp->dev->of_node, "gpio-controller")) 1973 return 0; 1974 1975 mcasp->gpio_chip = davinci_mcasp_template_chip; 1976 mcasp->gpio_chip.label = dev_name(mcasp->dev); 1977 mcasp->gpio_chip.parent = mcasp->dev; 1978 #ifdef CONFIG_OF_GPIO 1979 mcasp->gpio_chip.of_node = mcasp->dev->of_node; 1980 #endif 1981 1982 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp); 1983 } 1984 1985 #else /* CONFIG_GPIOLIB */ 1986 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) 1987 { 1988 return 0; 1989 } 1990 #endif /* CONFIG_GPIOLIB */ 1991 1992 static int davinci_mcasp_probe(struct platform_device *pdev) 1993 { 1994 struct snd_dmaengine_dai_dma_data *dma_data; 1995 struct resource *mem, *res, *dat; 1996 struct davinci_mcasp_pdata *pdata; 1997 struct davinci_mcasp *mcasp; 1998 char *irq_name; 1999 int *dma; 2000 int irq; 2001 int ret; 2002 2003 if (!pdev->dev.platform_data && !pdev->dev.of_node) { 2004 dev_err(&pdev->dev, "No platform data supplied\n"); 2005 return -EINVAL; 2006 } 2007 2008 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), 2009 GFP_KERNEL); 2010 if (!mcasp) 2011 return -ENOMEM; 2012 2013 pdata = davinci_mcasp_set_pdata_from_of(pdev); 2014 if (!pdata) { 2015 dev_err(&pdev->dev, "no platform data\n"); 2016 return -EINVAL; 2017 } 2018 2019 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); 2020 if (!mem) { 2021 dev_warn(mcasp->dev, 2022 "\"mpu\" mem resource not found, using index 0\n"); 2023 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2024 if (!mem) { 2025 dev_err(&pdev->dev, "no mem resource?\n"); 2026 return -ENODEV; 2027 } 2028 } 2029 2030 mcasp->base = devm_ioremap_resource(&pdev->dev, mem); 2031 if (IS_ERR(mcasp->base)) 2032 return PTR_ERR(mcasp->base); 2033 2034 pm_runtime_enable(&pdev->dev); 2035 2036 mcasp->op_mode = pdata->op_mode; 2037 /* sanity check for tdm slots parameter */ 2038 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { 2039 if (pdata->tdm_slots < 2) { 2040 dev_err(&pdev->dev, "invalid tdm slots: %d\n", 2041 pdata->tdm_slots); 2042 mcasp->tdm_slots = 2; 2043 } else if (pdata->tdm_slots > 32) { 2044 dev_err(&pdev->dev, "invalid tdm slots: %d\n", 2045 pdata->tdm_slots); 2046 mcasp->tdm_slots = 32; 2047 } else { 2048 mcasp->tdm_slots = pdata->tdm_slots; 2049 } 2050 } 2051 2052 mcasp->num_serializer = pdata->num_serializer; 2053 #ifdef CONFIG_PM 2054 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev, 2055 mcasp->num_serializer, sizeof(u32), 2056 GFP_KERNEL); 2057 if (!mcasp->context.xrsr_regs) { 2058 ret = -ENOMEM; 2059 goto err; 2060 } 2061 #endif 2062 mcasp->serial_dir = pdata->serial_dir; 2063 mcasp->version = pdata->version; 2064 mcasp->txnumevt = pdata->txnumevt; 2065 mcasp->rxnumevt = pdata->rxnumevt; 2066 mcasp->dismod = pdata->dismod; 2067 2068 mcasp->dev = &pdev->dev; 2069 2070 irq = platform_get_irq_byname(pdev, "common"); 2071 if (irq >= 0) { 2072 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common", 2073 dev_name(&pdev->dev)); 2074 if (!irq_name) { 2075 ret = -ENOMEM; 2076 goto err; 2077 } 2078 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2079 davinci_mcasp_common_irq_handler, 2080 IRQF_ONESHOT | IRQF_SHARED, 2081 irq_name, mcasp); 2082 if (ret) { 2083 dev_err(&pdev->dev, "common IRQ request failed\n"); 2084 goto err; 2085 } 2086 2087 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; 2088 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; 2089 } 2090 2091 irq = platform_get_irq_byname(pdev, "rx"); 2092 if (irq >= 0) { 2093 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx", 2094 dev_name(&pdev->dev)); 2095 if (!irq_name) { 2096 ret = -ENOMEM; 2097 goto err; 2098 } 2099 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2100 davinci_mcasp_rx_irq_handler, 2101 IRQF_ONESHOT, irq_name, mcasp); 2102 if (ret) { 2103 dev_err(&pdev->dev, "RX IRQ request failed\n"); 2104 goto err; 2105 } 2106 2107 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; 2108 } 2109 2110 irq = platform_get_irq_byname(pdev, "tx"); 2111 if (irq >= 0) { 2112 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx", 2113 dev_name(&pdev->dev)); 2114 if (!irq_name) { 2115 ret = -ENOMEM; 2116 goto err; 2117 } 2118 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2119 davinci_mcasp_tx_irq_handler, 2120 IRQF_ONESHOT, irq_name, mcasp); 2121 if (ret) { 2122 dev_err(&pdev->dev, "TX IRQ request failed\n"); 2123 goto err; 2124 } 2125 2126 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; 2127 } 2128 2129 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 2130 if (dat) 2131 mcasp->dat_port = true; 2132 2133 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; 2134 if (dat) 2135 dma_data->addr = dat->start; 2136 else 2137 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata); 2138 2139 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK]; 2140 res = platform_get_resource(pdev, IORESOURCE_DMA, 0); 2141 if (res) 2142 *dma = res->start; 2143 else 2144 *dma = pdata->tx_dma_channel; 2145 2146 /* dmaengine filter data for DT and non-DT boot */ 2147 if (pdev->dev.of_node) 2148 dma_data->filter_data = "tx"; 2149 else 2150 dma_data->filter_data = dma; 2151 2152 /* RX is not valid in DIT mode */ 2153 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 2154 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; 2155 if (dat) 2156 dma_data->addr = dat->start; 2157 else 2158 dma_data->addr = 2159 mem->start + davinci_mcasp_rxdma_offset(pdata); 2160 2161 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE]; 2162 res = platform_get_resource(pdev, IORESOURCE_DMA, 1); 2163 if (res) 2164 *dma = res->start; 2165 else 2166 *dma = pdata->rx_dma_channel; 2167 2168 /* dmaengine filter data for DT and non-DT boot */ 2169 if (pdev->dev.of_node) 2170 dma_data->filter_data = "rx"; 2171 else 2172 dma_data->filter_data = dma; 2173 } 2174 2175 if (mcasp->version < MCASP_VERSION_3) { 2176 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; 2177 /* dma_params->dma_addr is pointing to the data port address */ 2178 mcasp->dat_port = true; 2179 } else { 2180 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; 2181 } 2182 2183 /* Allocate memory for long enough list for all possible 2184 * scenarios. Maximum number tdm slots is 32 and there cannot 2185 * be more serializers than given in the configuration. The 2186 * serializer directions could be taken into account, but it 2187 * would make code much more complex and save only couple of 2188 * bytes. 2189 */ 2190 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list = 2191 devm_kcalloc(mcasp->dev, 2192 32 + mcasp->num_serializer - 1, 2193 sizeof(unsigned int), 2194 GFP_KERNEL); 2195 2196 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list = 2197 devm_kcalloc(mcasp->dev, 2198 32 + mcasp->num_serializer - 1, 2199 sizeof(unsigned int), 2200 GFP_KERNEL); 2201 2202 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list || 2203 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) { 2204 ret = -ENOMEM; 2205 goto err; 2206 } 2207 2208 ret = davinci_mcasp_set_ch_constraints(mcasp); 2209 if (ret) 2210 goto err; 2211 2212 dev_set_drvdata(&pdev->dev, mcasp); 2213 2214 mcasp_reparent_fck(pdev); 2215 2216 /* All PINS as McASP */ 2217 pm_runtime_get_sync(mcasp->dev); 2218 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); 2219 pm_runtime_put(mcasp->dev); 2220 2221 ret = davinci_mcasp_init_gpiochip(mcasp); 2222 if (ret) 2223 goto err; 2224 2225 ret = devm_snd_soc_register_component(&pdev->dev, 2226 &davinci_mcasp_component, 2227 &davinci_mcasp_dai[pdata->op_mode], 1); 2228 2229 if (ret != 0) 2230 goto err; 2231 2232 ret = davinci_mcasp_get_dma_type(mcasp); 2233 switch (ret) { 2234 case PCM_EDMA: 2235 ret = edma_pcm_platform_register(&pdev->dev); 2236 break; 2237 case PCM_SDMA: 2238 ret = sdma_pcm_platform_register(&pdev->dev, NULL, NULL); 2239 break; 2240 default: 2241 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret); 2242 case -EPROBE_DEFER: 2243 goto err; 2244 break; 2245 } 2246 2247 if (ret) { 2248 dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 2249 goto err; 2250 } 2251 2252 return 0; 2253 2254 err: 2255 pm_runtime_disable(&pdev->dev); 2256 return ret; 2257 } 2258 2259 static int davinci_mcasp_remove(struct platform_device *pdev) 2260 { 2261 pm_runtime_disable(&pdev->dev); 2262 2263 return 0; 2264 } 2265 2266 #ifdef CONFIG_PM 2267 static int davinci_mcasp_runtime_suspend(struct device *dev) 2268 { 2269 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 2270 struct davinci_mcasp_context *context = &mcasp->context; 2271 u32 reg; 2272 int i; 2273 2274 for (i = 0; i < ARRAY_SIZE(context_regs); i++) 2275 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); 2276 2277 if (mcasp->txnumevt) { 2278 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 2279 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); 2280 } 2281 if (mcasp->rxnumevt) { 2282 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 2283 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); 2284 } 2285 2286 for (i = 0; i < mcasp->num_serializer; i++) 2287 context->xrsr_regs[i] = mcasp_get_reg(mcasp, 2288 DAVINCI_MCASP_XRSRCTL_REG(i)); 2289 2290 return 0; 2291 } 2292 2293 static int davinci_mcasp_runtime_resume(struct device *dev) 2294 { 2295 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 2296 struct davinci_mcasp_context *context = &mcasp->context; 2297 u32 reg; 2298 int i; 2299 2300 for (i = 0; i < ARRAY_SIZE(context_regs); i++) 2301 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); 2302 2303 if (mcasp->txnumevt) { 2304 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 2305 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); 2306 } 2307 if (mcasp->rxnumevt) { 2308 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 2309 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); 2310 } 2311 2312 for (i = 0; i < mcasp->num_serializer; i++) 2313 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 2314 context->xrsr_regs[i]); 2315 2316 return 0; 2317 } 2318 2319 #endif 2320 2321 static const struct dev_pm_ops davinci_mcasp_pm_ops = { 2322 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend, 2323 davinci_mcasp_runtime_resume, 2324 NULL) 2325 }; 2326 2327 static struct platform_driver davinci_mcasp_driver = { 2328 .probe = davinci_mcasp_probe, 2329 .remove = davinci_mcasp_remove, 2330 .driver = { 2331 .name = "davinci-mcasp", 2332 .pm = &davinci_mcasp_pm_ops, 2333 .of_match_table = mcasp_dt_ids, 2334 }, 2335 }; 2336 2337 module_platform_driver(davinci_mcasp_driver); 2338 2339 MODULE_AUTHOR("Steve Chen"); 2340 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); 2341 MODULE_LICENSE("GPL"); 2342