1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ALSA SoC McASP Audio Layer for TI DAVINCI processor 4 * 5 * Multi-channel Audio Serial Port Driver 6 * 7 * Author: Nirmal Pandey <n-pandey@ti.com>, 8 * Suresh Rajashekara <suresh.r@ti.com> 9 * Steve Chen <schen@.mvista.com> 10 * 11 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> 12 * Copyright: (C) 2009 Texas Instruments, India 13 */ 14 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/device.h> 18 #include <linux/slab.h> 19 #include <linux/delay.h> 20 #include <linux/io.h> 21 #include <linux/clk.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/of.h> 24 #include <linux/platform_data/davinci_asp.h> 25 #include <linux/math64.h> 26 #include <linux/bitmap.h> 27 #include <linux/gpio/driver.h> 28 29 #include <sound/asoundef.h> 30 #include <sound/core.h> 31 #include <sound/pcm.h> 32 #include <sound/pcm_params.h> 33 #include <sound/initval.h> 34 #include <sound/soc.h> 35 #include <sound/dmaengine_pcm.h> 36 37 #include "edma-pcm.h" 38 #include "sdma-pcm.h" 39 #include "udma-pcm.h" 40 #include "davinci-mcasp.h" 41 42 #define MCASP_MAX_AFIFO_DEPTH 64 43 44 #ifdef CONFIG_PM 45 static u32 context_regs[] = { 46 DAVINCI_MCASP_TXFMCTL_REG, 47 DAVINCI_MCASP_RXFMCTL_REG, 48 DAVINCI_MCASP_TXFMT_REG, 49 DAVINCI_MCASP_RXFMT_REG, 50 DAVINCI_MCASP_ACLKXCTL_REG, 51 DAVINCI_MCASP_ACLKRCTL_REG, 52 DAVINCI_MCASP_AHCLKXCTL_REG, 53 DAVINCI_MCASP_AHCLKRCTL_REG, 54 DAVINCI_MCASP_PDIR_REG, 55 DAVINCI_MCASP_PFUNC_REG, 56 DAVINCI_MCASP_RXMASK_REG, 57 DAVINCI_MCASP_TXMASK_REG, 58 DAVINCI_MCASP_RXTDM_REG, 59 DAVINCI_MCASP_TXTDM_REG, 60 }; 61 62 struct davinci_mcasp_context { 63 u32 config_regs[ARRAY_SIZE(context_regs)]; 64 u32 afifo_regs[2]; /* for read/write fifo control registers */ 65 u32 *xrsr_regs; /* for serializer configuration */ 66 bool pm_state; 67 }; 68 #endif 69 70 struct davinci_mcasp_ruledata { 71 struct davinci_mcasp *mcasp; 72 int serializers; 73 }; 74 75 struct davinci_mcasp { 76 struct snd_dmaengine_dai_dma_data dma_data[2]; 77 struct davinci_mcasp_pdata *pdata; 78 void __iomem *base; 79 u32 fifo_base; 80 struct device *dev; 81 struct snd_pcm_substream *substreams[2]; 82 unsigned int dai_fmt; 83 84 u32 iec958_status; 85 86 /* Audio can not be enabled due to missing parameter(s) */ 87 bool missing_audio_param; 88 89 /* McASP specific data */ 90 int tdm_slots; 91 u32 tdm_mask[2]; 92 int slot_width; 93 u8 op_mode; 94 u8 dismod; 95 u8 num_serializer; 96 u8 *serial_dir; 97 u8 version; 98 u8 bclk_div; 99 int streams; 100 u32 irq_request[2]; 101 102 int sysclk_freq; 103 bool bclk_master; 104 u32 auxclk_fs_ratio; 105 106 unsigned long pdir; /* Pin direction bitfield */ 107 108 /* McASP FIFO related */ 109 u8 txnumevt; 110 u8 rxnumevt; 111 112 bool dat_port; 113 114 /* Used for comstraint setting on the second stream */ 115 u32 channels; 116 int max_format_width; 117 u8 active_serializers[2]; 118 119 #ifdef CONFIG_GPIOLIB 120 struct gpio_chip gpio_chip; 121 #endif 122 123 #ifdef CONFIG_PM 124 struct davinci_mcasp_context context; 125 #endif 126 127 struct davinci_mcasp_ruledata ruledata[2]; 128 struct snd_pcm_hw_constraint_list chconstr[2]; 129 }; 130 131 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, 132 u32 val) 133 { 134 void __iomem *reg = mcasp->base + offset; 135 __raw_writel(__raw_readl(reg) | val, reg); 136 } 137 138 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, 139 u32 val) 140 { 141 void __iomem *reg = mcasp->base + offset; 142 __raw_writel((__raw_readl(reg) & ~(val)), reg); 143 } 144 145 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, 146 u32 val, u32 mask) 147 { 148 void __iomem *reg = mcasp->base + offset; 149 __raw_writel((__raw_readl(reg) & ~mask) | val, reg); 150 } 151 152 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, 153 u32 val) 154 { 155 __raw_writel(val, mcasp->base + offset); 156 } 157 158 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) 159 { 160 return (u32)__raw_readl(mcasp->base + offset); 161 } 162 163 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) 164 { 165 int i = 0; 166 167 mcasp_set_bits(mcasp, ctl_reg, val); 168 169 /* programming GBLCTL needs to read back from GBLCTL and verfiy */ 170 /* loop count is to avoid the lock-up */ 171 for (i = 0; i < 1000; i++) { 172 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) 173 break; 174 } 175 176 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) 177 printk(KERN_ERR "GBLCTL write error\n"); 178 } 179 180 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) 181 { 182 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); 183 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); 184 185 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; 186 } 187 188 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable) 189 { 190 u32 bit = PIN_BIT_AMUTE; 191 192 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) { 193 if (enable) 194 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 195 else 196 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 197 } 198 } 199 200 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable) 201 { 202 u32 bit; 203 204 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) { 205 if (enable) 206 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 207 else 208 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 209 } 210 } 211 212 static void mcasp_start_rx(struct davinci_mcasp *mcasp) 213 { 214 if (mcasp->rxnumevt) { /* enable FIFO */ 215 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 216 217 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 218 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); 219 } 220 221 /* Start clocks */ 222 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); 223 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); 224 /* 225 * When ASYNC == 0 the transmit and receive sections operate 226 * synchronously from the transmit clock and frame sync. We need to make 227 * sure that the TX signlas are enabled when starting reception. 228 */ 229 if (mcasp_is_synchronous(mcasp)) { 230 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 231 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 232 mcasp_set_clk_pdir(mcasp, true); 233 } 234 235 /* Activate serializer(s) */ 236 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 237 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); 238 /* Release RX state machine */ 239 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); 240 /* Release Frame Sync generator */ 241 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); 242 if (mcasp_is_synchronous(mcasp)) 243 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 244 245 /* enable receive IRQs */ 246 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, 247 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); 248 } 249 250 static void mcasp_start_tx(struct davinci_mcasp *mcasp) 251 { 252 u32 cnt; 253 254 if (mcasp->txnumevt) { /* enable FIFO */ 255 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 256 257 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 258 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); 259 } 260 261 /* Start clocks */ 262 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 263 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 264 mcasp_set_clk_pdir(mcasp, true); 265 266 /* Activate serializer(s) */ 267 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 268 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); 269 270 /* wait for XDATA to be cleared */ 271 cnt = 0; 272 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) && 273 (cnt < 100000)) 274 cnt++; 275 276 mcasp_set_axr_pdir(mcasp, true); 277 278 /* Release TX state machine */ 279 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); 280 /* Release Frame Sync generator */ 281 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 282 283 /* enable transmit IRQs */ 284 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, 285 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); 286 } 287 288 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) 289 { 290 mcasp->streams++; 291 292 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 293 mcasp_start_tx(mcasp); 294 else 295 mcasp_start_rx(mcasp); 296 } 297 298 static void mcasp_stop_rx(struct davinci_mcasp *mcasp) 299 { 300 /* disable IRQ sources */ 301 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, 302 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); 303 304 /* 305 * In synchronous mode stop the TX clocks if no other stream is 306 * running 307 */ 308 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) { 309 mcasp_set_clk_pdir(mcasp, false); 310 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); 311 } 312 313 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); 314 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 315 316 if (mcasp->rxnumevt) { /* disable FIFO */ 317 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 318 319 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 320 } 321 } 322 323 static void mcasp_stop_tx(struct davinci_mcasp *mcasp) 324 { 325 u32 val = 0; 326 327 /* disable IRQ sources */ 328 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, 329 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); 330 331 /* 332 * In synchronous mode keep TX clocks running if the capture stream is 333 * still running. 334 */ 335 if (mcasp_is_synchronous(mcasp) && mcasp->streams) 336 val = TXHCLKRST | TXCLKRST | TXFSRST; 337 else 338 mcasp_set_clk_pdir(mcasp, false); 339 340 341 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); 342 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 343 344 if (mcasp->txnumevt) { /* disable FIFO */ 345 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 346 347 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 348 } 349 350 mcasp_set_axr_pdir(mcasp, false); 351 } 352 353 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) 354 { 355 mcasp->streams--; 356 357 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 358 mcasp_stop_tx(mcasp); 359 else 360 mcasp_stop_rx(mcasp); 361 } 362 363 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data) 364 { 365 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 366 struct snd_pcm_substream *substream; 367 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]; 368 u32 handled_mask = 0; 369 u32 stat; 370 371 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG); 372 if (stat & XUNDRN & irq_mask) { 373 dev_warn(mcasp->dev, "Transmit buffer underflow\n"); 374 handled_mask |= XUNDRN; 375 376 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]; 377 if (substream) 378 snd_pcm_stop_xrun(substream); 379 } 380 381 if (!handled_mask) 382 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n", 383 stat); 384 385 if (stat & XRERR) 386 handled_mask |= XRERR; 387 388 /* Ack the handled event only */ 389 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask); 390 391 return IRQ_RETVAL(handled_mask); 392 } 393 394 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data) 395 { 396 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 397 struct snd_pcm_substream *substream; 398 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]; 399 u32 handled_mask = 0; 400 u32 stat; 401 402 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG); 403 if (stat & ROVRN & irq_mask) { 404 dev_warn(mcasp->dev, "Receive buffer overflow\n"); 405 handled_mask |= ROVRN; 406 407 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]; 408 if (substream) 409 snd_pcm_stop_xrun(substream); 410 } 411 412 if (!handled_mask) 413 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n", 414 stat); 415 416 if (stat & XRERR) 417 handled_mask |= XRERR; 418 419 /* Ack the handled event only */ 420 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask); 421 422 return IRQ_RETVAL(handled_mask); 423 } 424 425 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data) 426 { 427 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 428 irqreturn_t ret = IRQ_NONE; 429 430 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]) 431 ret = davinci_mcasp_tx_irq_handler(irq, data); 432 433 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]) 434 ret |= davinci_mcasp_rx_irq_handler(irq, data); 435 436 return ret; 437 } 438 439 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, 440 unsigned int fmt) 441 { 442 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 443 int ret = 0; 444 u32 data_delay; 445 bool fs_pol_rising; 446 bool inv_fs = false; 447 448 if (!fmt) 449 return 0; 450 451 pm_runtime_get_sync(mcasp->dev); 452 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 453 case SND_SOC_DAIFMT_DSP_A: 454 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 455 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 456 /* 1st data bit occur one ACLK cycle after the frame sync */ 457 data_delay = 1; 458 break; 459 case SND_SOC_DAIFMT_DSP_B: 460 case SND_SOC_DAIFMT_AC97: 461 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 462 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 463 /* No delay after FS */ 464 data_delay = 0; 465 break; 466 case SND_SOC_DAIFMT_I2S: 467 /* configure a full-word SYNC pulse (LRCLK) */ 468 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 469 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 470 /* 1st data bit occur one ACLK cycle after the frame sync */ 471 data_delay = 1; 472 /* FS need to be inverted */ 473 inv_fs = true; 474 break; 475 case SND_SOC_DAIFMT_RIGHT_J: 476 case SND_SOC_DAIFMT_LEFT_J: 477 /* configure a full-word SYNC pulse (LRCLK) */ 478 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 479 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 480 /* No delay after FS */ 481 data_delay = 0; 482 break; 483 default: 484 ret = -EINVAL; 485 goto out; 486 } 487 488 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), 489 FSXDLY(3)); 490 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), 491 FSRDLY(3)); 492 493 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 494 case SND_SOC_DAIFMT_BP_FP: 495 /* codec is clock and frame slave */ 496 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 497 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 498 499 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 500 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 501 502 /* BCLK */ 503 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); 504 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); 505 /* Frame Sync */ 506 set_bit(PIN_BIT_AFSX, &mcasp->pdir); 507 set_bit(PIN_BIT_AFSR, &mcasp->pdir); 508 509 mcasp->bclk_master = 1; 510 break; 511 case SND_SOC_DAIFMT_BP_FC: 512 /* codec is clock slave and frame master */ 513 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 514 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 515 516 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 517 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 518 519 /* BCLK */ 520 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); 521 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); 522 /* Frame Sync */ 523 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); 524 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); 525 526 mcasp->bclk_master = 1; 527 break; 528 case SND_SOC_DAIFMT_BC_FP: 529 /* codec is clock master and frame slave */ 530 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 531 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 532 533 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 534 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 535 536 /* BCLK */ 537 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); 538 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); 539 /* Frame Sync */ 540 set_bit(PIN_BIT_AFSX, &mcasp->pdir); 541 set_bit(PIN_BIT_AFSR, &mcasp->pdir); 542 543 mcasp->bclk_master = 0; 544 break; 545 case SND_SOC_DAIFMT_BC_FC: 546 /* codec is clock and frame master */ 547 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 548 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 549 550 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 551 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 552 553 /* BCLK */ 554 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); 555 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); 556 /* Frame Sync */ 557 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); 558 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); 559 560 mcasp->bclk_master = 0; 561 break; 562 default: 563 ret = -EINVAL; 564 goto out; 565 } 566 567 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 568 case SND_SOC_DAIFMT_IB_NF: 569 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 570 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 571 fs_pol_rising = true; 572 break; 573 case SND_SOC_DAIFMT_NB_IF: 574 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 575 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 576 fs_pol_rising = false; 577 break; 578 case SND_SOC_DAIFMT_IB_IF: 579 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 580 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 581 fs_pol_rising = false; 582 break; 583 case SND_SOC_DAIFMT_NB_NF: 584 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 585 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 586 fs_pol_rising = true; 587 break; 588 default: 589 ret = -EINVAL; 590 goto out; 591 } 592 593 if (inv_fs) 594 fs_pol_rising = !fs_pol_rising; 595 596 if (fs_pol_rising) { 597 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 598 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 599 } else { 600 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 601 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 602 } 603 604 mcasp->dai_fmt = fmt; 605 out: 606 pm_runtime_put(mcasp->dev); 607 return ret; 608 } 609 610 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id, 611 int div, bool explicit) 612 { 613 pm_runtime_get_sync(mcasp->dev); 614 switch (div_id) { 615 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */ 616 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 617 AHCLKXDIV(div - 1), AHCLKXDIV_MASK); 618 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 619 AHCLKRDIV(div - 1), AHCLKRDIV_MASK); 620 break; 621 622 case MCASP_CLKDIV_BCLK: /* BCLK divider */ 623 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, 624 ACLKXDIV(div - 1), ACLKXDIV_MASK); 625 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, 626 ACLKRDIV(div - 1), ACLKRDIV_MASK); 627 if (explicit) 628 mcasp->bclk_div = div; 629 break; 630 631 case MCASP_CLKDIV_BCLK_FS_RATIO: 632 /* 633 * BCLK/LRCLK ratio descries how many bit-clock cycles 634 * fit into one frame. The clock ratio is given for a 635 * full period of data (for I2S format both left and 636 * right channels), so it has to be divided by number 637 * of tdm-slots (for I2S - divided by 2). 638 * Instead of storing this ratio, we calculate a new 639 * tdm_slot width by dividing the ratio by the 640 * number of configured tdm slots. 641 */ 642 mcasp->slot_width = div / mcasp->tdm_slots; 643 if (div % mcasp->tdm_slots) 644 dev_warn(mcasp->dev, 645 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots", 646 __func__, div, mcasp->tdm_slots); 647 break; 648 649 default: 650 return -EINVAL; 651 } 652 653 pm_runtime_put(mcasp->dev); 654 return 0; 655 } 656 657 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, 658 int div) 659 { 660 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 661 662 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1); 663 } 664 665 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, 666 unsigned int freq, int dir) 667 { 668 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 669 670 pm_runtime_get_sync(mcasp->dev); 671 672 if (dir == SND_SOC_CLOCK_IN) { 673 switch (clk_id) { 674 case MCASP_CLK_HCLK_AHCLK: 675 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 676 AHCLKXE); 677 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 678 AHCLKRE); 679 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 680 break; 681 case MCASP_CLK_HCLK_AUXCLK: 682 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 683 AHCLKXE); 684 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 685 AHCLKRE); 686 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 687 break; 688 default: 689 dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id); 690 goto out; 691 } 692 } else { 693 /* Select AUXCLK as HCLK */ 694 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); 695 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); 696 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 697 } 698 /* 699 * When AHCLK X/R is selected to be output it means that the HCLK is 700 * the same clock - coming via AUXCLK. 701 */ 702 mcasp->sysclk_freq = freq; 703 out: 704 pm_runtime_put(mcasp->dev); 705 return 0; 706 } 707 708 /* All serializers must have equal number of channels */ 709 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream, 710 int serializers) 711 { 712 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream]; 713 unsigned int *list = (unsigned int *) cl->list; 714 int slots = mcasp->tdm_slots; 715 int i, count = 0; 716 717 if (mcasp->tdm_mask[stream]) 718 slots = hweight32(mcasp->tdm_mask[stream]); 719 720 for (i = 1; i <= slots; i++) 721 list[count++] = i; 722 723 for (i = 2; i <= serializers; i++) 724 list[count++] = i*slots; 725 726 cl->count = count; 727 728 return 0; 729 } 730 731 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp) 732 { 733 int rx_serializers = 0, tx_serializers = 0, ret, i; 734 735 for (i = 0; i < mcasp->num_serializer; i++) 736 if (mcasp->serial_dir[i] == TX_MODE) 737 tx_serializers++; 738 else if (mcasp->serial_dir[i] == RX_MODE) 739 rx_serializers++; 740 741 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK, 742 tx_serializers); 743 if (ret) 744 return ret; 745 746 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE, 747 rx_serializers); 748 749 return ret; 750 } 751 752 753 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai, 754 unsigned int tx_mask, 755 unsigned int rx_mask, 756 int slots, int slot_width) 757 { 758 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 759 760 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 761 return 0; 762 763 dev_dbg(mcasp->dev, 764 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n", 765 __func__, tx_mask, rx_mask, slots, slot_width); 766 767 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) { 768 dev_err(mcasp->dev, 769 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n", 770 tx_mask, rx_mask, slots); 771 return -EINVAL; 772 } 773 774 if (slot_width && 775 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) { 776 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n", 777 __func__, slot_width); 778 return -EINVAL; 779 } 780 781 mcasp->tdm_slots = slots; 782 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask; 783 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask; 784 mcasp->slot_width = slot_width; 785 786 return davinci_mcasp_set_ch_constraints(mcasp); 787 } 788 789 static int davinci_config_channel_size(struct davinci_mcasp *mcasp, 790 int sample_width) 791 { 792 u32 fmt; 793 u32 tx_rotate, rx_rotate, slot_width; 794 u32 mask = (1ULL << sample_width) - 1; 795 796 if (mcasp->slot_width) 797 slot_width = mcasp->slot_width; 798 else if (mcasp->max_format_width) 799 slot_width = mcasp->max_format_width; 800 else 801 slot_width = sample_width; 802 /* 803 * TX rotation: 804 * right aligned formats: rotate w/ slot_width 805 * left aligned formats: rotate w/ sample_width 806 * 807 * RX rotation: 808 * right aligned formats: no rotation needed 809 * left aligned formats: rotate w/ (slot_width - sample_width) 810 */ 811 if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == 812 SND_SOC_DAIFMT_RIGHT_J) { 813 tx_rotate = (slot_width / 4) & 0x7; 814 rx_rotate = 0; 815 } else { 816 tx_rotate = (sample_width / 4) & 0x7; 817 rx_rotate = (slot_width - sample_width) / 4; 818 } 819 820 /* mapping of the XSSZ bit-field as described in the datasheet */ 821 fmt = (slot_width >> 1) - 1; 822 823 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 824 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), 825 RXSSZ(0x0F)); 826 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), 827 TXSSZ(0x0F)); 828 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), 829 TXROT(7)); 830 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), 831 RXROT(7)); 832 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); 833 } else { 834 /* 835 * according to the TRM it should be TXROT=0, this one works: 836 * 16 bit to 23-8 (TXROT=6, rotate 24 bits) 837 * 24 bit to 23-0 (TXROT=0, rotate 0 bits) 838 * 839 * TXROT = 0 only works with 24bit samples 840 */ 841 tx_rotate = (sample_width / 4 + 2) & 0x7; 842 843 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), 844 TXROT(7)); 845 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(15), 846 TXSSZ(0x0F)); 847 } 848 849 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); 850 851 return 0; 852 } 853 854 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, 855 int period_words, int channels) 856 { 857 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; 858 int i; 859 u8 tx_ser = 0; 860 u8 rx_ser = 0; 861 u8 slots = mcasp->tdm_slots; 862 u8 max_active_serializers, max_rx_serializers, max_tx_serializers; 863 int active_serializers, numevt; 864 u32 reg; 865 866 /* In DIT mode we only allow maximum of one serializers for now */ 867 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 868 max_active_serializers = 1; 869 else 870 max_active_serializers = DIV_ROUND_UP(channels, slots); 871 872 /* Default configuration */ 873 if (mcasp->version < MCASP_VERSION_3) 874 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); 875 876 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 877 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 878 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 879 max_tx_serializers = max_active_serializers; 880 max_rx_serializers = 881 mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE]; 882 } else { 883 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 884 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); 885 max_tx_serializers = 886 mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK]; 887 max_rx_serializers = max_active_serializers; 888 } 889 890 for (i = 0; i < mcasp->num_serializer; i++) { 891 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 892 mcasp->serial_dir[i]); 893 if (mcasp->serial_dir[i] == TX_MODE && 894 tx_ser < max_tx_serializers) { 895 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 896 mcasp->dismod, DISMOD_MASK); 897 set_bit(PIN_BIT_AXR(i), &mcasp->pdir); 898 tx_ser++; 899 } else if (mcasp->serial_dir[i] == RX_MODE && 900 rx_ser < max_rx_serializers) { 901 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 902 rx_ser++; 903 } else { 904 /* Inactive or unused pin, set it to inactive */ 905 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 906 SRMOD_INACTIVE, SRMOD_MASK); 907 /* If unused, set DISMOD for the pin */ 908 if (mcasp->serial_dir[i] != INACTIVE_MODE) 909 mcasp_mod_bits(mcasp, 910 DAVINCI_MCASP_XRSRCTL_REG(i), 911 mcasp->dismod, DISMOD_MASK); 912 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 913 } 914 } 915 916 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 917 active_serializers = tx_ser; 918 numevt = mcasp->txnumevt; 919 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 920 } else { 921 active_serializers = rx_ser; 922 numevt = mcasp->rxnumevt; 923 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 924 } 925 926 if (active_serializers < max_active_serializers) { 927 dev_warn(mcasp->dev, "stream has more channels (%d) than are " 928 "enabled in mcasp (%d)\n", channels, 929 active_serializers * slots); 930 return -EINVAL; 931 } 932 933 /* AFIFO is not in use */ 934 if (!numevt) { 935 /* Configure the burst size for platform drivers */ 936 if (active_serializers > 1) { 937 /* 938 * If more than one serializers are in use we have one 939 * DMA request to provide data for all serializers. 940 * For example if three serializers are enabled the DMA 941 * need to transfer three words per DMA request. 942 */ 943 dma_data->maxburst = active_serializers; 944 } else { 945 dma_data->maxburst = 0; 946 } 947 948 goto out; 949 } 950 951 if (period_words % active_serializers) { 952 dev_err(mcasp->dev, "Invalid combination of period words and " 953 "active serializers: %d, %d\n", period_words, 954 active_serializers); 955 return -EINVAL; 956 } 957 958 /* 959 * Calculate the optimal AFIFO depth for platform side: 960 * The number of words for numevt need to be in steps of active 961 * serializers. 962 */ 963 numevt = (numevt / active_serializers) * active_serializers; 964 965 while (period_words % numevt && numevt > 0) 966 numevt -= active_serializers; 967 if (numevt <= 0) 968 numevt = active_serializers; 969 970 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); 971 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); 972 973 /* Configure the burst size for platform drivers */ 974 if (numevt == 1) 975 numevt = 0; 976 dma_data->maxburst = numevt; 977 978 out: 979 mcasp->active_serializers[stream] = active_serializers; 980 981 return 0; 982 } 983 984 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream, 985 int channels) 986 { 987 int i, active_slots; 988 int total_slots; 989 int active_serializers; 990 u32 mask = 0; 991 u32 busel = 0; 992 993 total_slots = mcasp->tdm_slots; 994 995 /* 996 * If more than one serializer is needed, then use them with 997 * all the specified tdm_slots. Otherwise, one serializer can 998 * cope with the transaction using just as many slots as there 999 * are channels in the stream. 1000 */ 1001 if (mcasp->tdm_mask[stream]) { 1002 active_slots = hweight32(mcasp->tdm_mask[stream]); 1003 active_serializers = DIV_ROUND_UP(channels, active_slots); 1004 if (active_serializers == 1) 1005 active_slots = channels; 1006 for (i = 0; i < total_slots; i++) { 1007 if ((1 << i) & mcasp->tdm_mask[stream]) { 1008 mask |= (1 << i); 1009 if (--active_slots <= 0) 1010 break; 1011 } 1012 } 1013 } else { 1014 active_serializers = DIV_ROUND_UP(channels, total_slots); 1015 if (active_serializers == 1) 1016 active_slots = channels; 1017 else 1018 active_slots = total_slots; 1019 1020 for (i = 0; i < active_slots; i++) 1021 mask |= (1 << i); 1022 } 1023 1024 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); 1025 1026 if (!mcasp->dat_port) 1027 busel = TXSEL; 1028 1029 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1030 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); 1031 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); 1032 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 1033 FSXMOD(total_slots), FSXMOD(0x1FF)); 1034 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) { 1035 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); 1036 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); 1037 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, 1038 FSRMOD(total_slots), FSRMOD(0x1FF)); 1039 /* 1040 * If McASP is set to be TX/RX synchronous and the playback is 1041 * not running already we need to configure the TX slots in 1042 * order to have correct FSX on the bus 1043 */ 1044 if (mcasp_is_synchronous(mcasp) && !mcasp->channels) 1045 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 1046 FSXMOD(total_slots), FSXMOD(0x1FF)); 1047 } 1048 1049 return 0; 1050 } 1051 1052 /* S/PDIF */ 1053 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, 1054 unsigned int rate) 1055 { 1056 u8 *cs_bytes = (u8 *)&mcasp->iec958_status; 1057 1058 if (!mcasp->dat_port) 1059 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL); 1060 else 1061 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL); 1062 1063 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ 1064 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); 1065 1066 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, 0xFFFF); 1067 1068 /* Set the TX tdm : for all the slots */ 1069 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); 1070 1071 /* Set the TX clock controls : div = 1 and internal */ 1072 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); 1073 1074 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 1075 1076 /* Set S/PDIF channel status bits */ 1077 cs_bytes[3] &= ~IEC958_AES3_CON_FS; 1078 switch (rate) { 1079 case 22050: 1080 cs_bytes[3] |= IEC958_AES3_CON_FS_22050; 1081 break; 1082 case 24000: 1083 cs_bytes[3] |= IEC958_AES3_CON_FS_24000; 1084 break; 1085 case 32000: 1086 cs_bytes[3] |= IEC958_AES3_CON_FS_32000; 1087 break; 1088 case 44100: 1089 cs_bytes[3] |= IEC958_AES3_CON_FS_44100; 1090 break; 1091 case 48000: 1092 cs_bytes[3] |= IEC958_AES3_CON_FS_48000; 1093 break; 1094 case 88200: 1095 cs_bytes[3] |= IEC958_AES3_CON_FS_88200; 1096 break; 1097 case 96000: 1098 cs_bytes[3] |= IEC958_AES3_CON_FS_96000; 1099 break; 1100 case 176400: 1101 cs_bytes[3] |= IEC958_AES3_CON_FS_176400; 1102 break; 1103 case 192000: 1104 cs_bytes[3] |= IEC958_AES3_CON_FS_192000; 1105 break; 1106 default: 1107 dev_err(mcasp->dev, "unsupported sampling rate: %d\n", rate); 1108 return -EINVAL; 1109 } 1110 1111 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, mcasp->iec958_status); 1112 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, mcasp->iec958_status); 1113 1114 /* Enable the DIT */ 1115 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); 1116 1117 return 0; 1118 } 1119 1120 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp, 1121 unsigned int sysclk_freq, 1122 unsigned int bclk_freq, bool set) 1123 { 1124 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG); 1125 int div = sysclk_freq / bclk_freq; 1126 int rem = sysclk_freq % bclk_freq; 1127 int error_ppm; 1128 int aux_div = 1; 1129 1130 if (div > (ACLKXDIV_MASK + 1)) { 1131 if (reg & AHCLKXE) { 1132 aux_div = div / (ACLKXDIV_MASK + 1); 1133 if (div % (ACLKXDIV_MASK + 1)) 1134 aux_div++; 1135 1136 sysclk_freq /= aux_div; 1137 div = sysclk_freq / bclk_freq; 1138 rem = sysclk_freq % bclk_freq; 1139 } else if (set) { 1140 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n", 1141 sysclk_freq); 1142 } 1143 } 1144 1145 if (rem != 0) { 1146 if (div == 0 || 1147 ((sysclk_freq / div) - bclk_freq) > 1148 (bclk_freq - (sysclk_freq / (div+1)))) { 1149 div++; 1150 rem = rem - bclk_freq; 1151 } 1152 } 1153 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem, 1154 (int)bclk_freq)) / div - 1000000; 1155 1156 if (set) { 1157 if (error_ppm) 1158 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n", 1159 error_ppm); 1160 1161 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0); 1162 if (reg & AHCLKXE) 1163 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK, 1164 aux_div, 0); 1165 } 1166 1167 return error_ppm; 1168 } 1169 1170 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp) 1171 { 1172 if (!mcasp->txnumevt) 1173 return 0; 1174 1175 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET); 1176 } 1177 1178 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp) 1179 { 1180 if (!mcasp->rxnumevt) 1181 return 0; 1182 1183 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET); 1184 } 1185 1186 static snd_pcm_sframes_t davinci_mcasp_delay( 1187 struct snd_pcm_substream *substream, 1188 struct snd_soc_dai *cpu_dai) 1189 { 1190 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1191 u32 fifo_use; 1192 1193 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1194 fifo_use = davinci_mcasp_tx_delay(mcasp); 1195 else 1196 fifo_use = davinci_mcasp_rx_delay(mcasp); 1197 1198 /* 1199 * Divide the used locations with the channel count to get the 1200 * FIFO usage in samples (don't care about partial samples in the 1201 * buffer). 1202 */ 1203 return fifo_use / substream->runtime->channels; 1204 } 1205 1206 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, 1207 struct snd_pcm_hw_params *params, 1208 struct snd_soc_dai *cpu_dai) 1209 { 1210 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1211 int word_length; 1212 int channels = params_channels(params); 1213 int period_size = params_period_size(params); 1214 int ret; 1215 1216 switch (params_format(params)) { 1217 case SNDRV_PCM_FORMAT_U8: 1218 case SNDRV_PCM_FORMAT_S8: 1219 word_length = 8; 1220 break; 1221 1222 case SNDRV_PCM_FORMAT_U16_LE: 1223 case SNDRV_PCM_FORMAT_S16_LE: 1224 word_length = 16; 1225 break; 1226 1227 case SNDRV_PCM_FORMAT_U24_3LE: 1228 case SNDRV_PCM_FORMAT_S24_3LE: 1229 word_length = 24; 1230 break; 1231 1232 case SNDRV_PCM_FORMAT_U24_LE: 1233 case SNDRV_PCM_FORMAT_S24_LE: 1234 word_length = 24; 1235 break; 1236 1237 case SNDRV_PCM_FORMAT_U32_LE: 1238 case SNDRV_PCM_FORMAT_S32_LE: 1239 word_length = 32; 1240 break; 1241 1242 default: 1243 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); 1244 return -EINVAL; 1245 } 1246 1247 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt); 1248 if (ret) 1249 return ret; 1250 1251 /* 1252 * If mcasp is BCLK master, and a BCLK divider was not provided by 1253 * the machine driver, we need to calculate the ratio. 1254 */ 1255 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { 1256 int slots = mcasp->tdm_slots; 1257 int rate = params_rate(params); 1258 int sbits = params_width(params); 1259 unsigned int bclk_target; 1260 1261 if (mcasp->slot_width) 1262 sbits = mcasp->slot_width; 1263 1264 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) 1265 bclk_target = rate * sbits * slots; 1266 else 1267 bclk_target = rate * 128; 1268 1269 davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq, 1270 bclk_target, true); 1271 } 1272 1273 ret = mcasp_common_hw_param(mcasp, substream->stream, 1274 period_size * channels, channels); 1275 if (ret) 1276 return ret; 1277 1278 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1279 ret = mcasp_dit_hw_param(mcasp, params_rate(params)); 1280 else 1281 ret = mcasp_i2s_hw_param(mcasp, substream->stream, 1282 channels); 1283 1284 if (ret) 1285 return ret; 1286 1287 davinci_config_channel_size(mcasp, word_length); 1288 1289 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { 1290 mcasp->channels = channels; 1291 if (!mcasp->max_format_width) 1292 mcasp->max_format_width = word_length; 1293 } 1294 1295 return 0; 1296 } 1297 1298 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, 1299 int cmd, struct snd_soc_dai *cpu_dai) 1300 { 1301 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1302 int ret = 0; 1303 1304 switch (cmd) { 1305 case SNDRV_PCM_TRIGGER_RESUME: 1306 case SNDRV_PCM_TRIGGER_START: 1307 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1308 davinci_mcasp_start(mcasp, substream->stream); 1309 break; 1310 case SNDRV_PCM_TRIGGER_SUSPEND: 1311 case SNDRV_PCM_TRIGGER_STOP: 1312 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1313 davinci_mcasp_stop(mcasp, substream->stream); 1314 break; 1315 1316 default: 1317 ret = -EINVAL; 1318 } 1319 1320 return ret; 1321 } 1322 1323 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params, 1324 struct snd_pcm_hw_rule *rule) 1325 { 1326 struct davinci_mcasp_ruledata *rd = rule->private; 1327 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1328 struct snd_mask nfmt; 1329 int slot_width; 1330 snd_pcm_format_t i; 1331 1332 snd_mask_none(&nfmt); 1333 slot_width = rd->mcasp->slot_width; 1334 1335 pcm_for_each_format(i) { 1336 if (snd_mask_test_format(fmt, i)) { 1337 if (snd_pcm_format_width(i) <= slot_width) { 1338 snd_mask_set_format(&nfmt, i); 1339 } 1340 } 1341 } 1342 1343 return snd_mask_refine(fmt, &nfmt); 1344 } 1345 1346 static int davinci_mcasp_hw_rule_format_width(struct snd_pcm_hw_params *params, 1347 struct snd_pcm_hw_rule *rule) 1348 { 1349 struct davinci_mcasp_ruledata *rd = rule->private; 1350 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1351 struct snd_mask nfmt; 1352 int format_width; 1353 snd_pcm_format_t i; 1354 1355 snd_mask_none(&nfmt); 1356 format_width = rd->mcasp->max_format_width; 1357 1358 pcm_for_each_format(i) { 1359 if (snd_mask_test_format(fmt, i)) { 1360 if (snd_pcm_format_width(i) == format_width) { 1361 snd_mask_set_format(&nfmt, i); 1362 } 1363 } 1364 } 1365 1366 return snd_mask_refine(fmt, &nfmt); 1367 } 1368 1369 static const unsigned int davinci_mcasp_dai_rates[] = { 1370 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 1371 88200, 96000, 176400, 192000, 1372 }; 1373 1374 #define DAVINCI_MAX_RATE_ERROR_PPM 1000 1375 1376 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params, 1377 struct snd_pcm_hw_rule *rule) 1378 { 1379 struct davinci_mcasp_ruledata *rd = rule->private; 1380 struct snd_interval *ri = 1381 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 1382 int sbits = params_width(params); 1383 int slots = rd->mcasp->tdm_slots; 1384 struct snd_interval range; 1385 int i; 1386 1387 if (rd->mcasp->slot_width) 1388 sbits = rd->mcasp->slot_width; 1389 1390 snd_interval_any(&range); 1391 range.empty = 1; 1392 1393 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) { 1394 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) { 1395 uint bclk_freq = sbits * slots * 1396 davinci_mcasp_dai_rates[i]; 1397 unsigned int sysclk_freq; 1398 int ppm; 1399 1400 if (rd->mcasp->auxclk_fs_ratio) 1401 sysclk_freq = davinci_mcasp_dai_rates[i] * 1402 rd->mcasp->auxclk_fs_ratio; 1403 else 1404 sysclk_freq = rd->mcasp->sysclk_freq; 1405 1406 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq, 1407 bclk_freq, false); 1408 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { 1409 if (range.empty) { 1410 range.min = davinci_mcasp_dai_rates[i]; 1411 range.empty = 0; 1412 } 1413 range.max = davinci_mcasp_dai_rates[i]; 1414 } 1415 } 1416 } 1417 1418 dev_dbg(rd->mcasp->dev, 1419 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n", 1420 ri->min, ri->max, range.min, range.max, sbits, slots); 1421 1422 return snd_interval_refine(hw_param_interval(params, rule->var), 1423 &range); 1424 } 1425 1426 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params, 1427 struct snd_pcm_hw_rule *rule) 1428 { 1429 struct davinci_mcasp_ruledata *rd = rule->private; 1430 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1431 struct snd_mask nfmt; 1432 int rate = params_rate(params); 1433 int slots = rd->mcasp->tdm_slots; 1434 int count = 0; 1435 snd_pcm_format_t i; 1436 1437 snd_mask_none(&nfmt); 1438 1439 pcm_for_each_format(i) { 1440 if (snd_mask_test_format(fmt, i)) { 1441 uint sbits = snd_pcm_format_width(i); 1442 unsigned int sysclk_freq; 1443 int ppm; 1444 1445 if (rd->mcasp->auxclk_fs_ratio) 1446 sysclk_freq = rate * 1447 rd->mcasp->auxclk_fs_ratio; 1448 else 1449 sysclk_freq = rd->mcasp->sysclk_freq; 1450 1451 if (rd->mcasp->slot_width) 1452 sbits = rd->mcasp->slot_width; 1453 1454 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq, 1455 sbits * slots * rate, 1456 false); 1457 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { 1458 snd_mask_set_format(&nfmt, i); 1459 count++; 1460 } 1461 } 1462 } 1463 dev_dbg(rd->mcasp->dev, 1464 "%d possible sample format for %d Hz and %d tdm slots\n", 1465 count, rate, slots); 1466 1467 return snd_mask_refine(fmt, &nfmt); 1468 } 1469 1470 static int davinci_mcasp_hw_rule_min_periodsize( 1471 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) 1472 { 1473 struct snd_interval *period_size = hw_param_interval(params, 1474 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 1475 struct snd_interval frames; 1476 1477 snd_interval_any(&frames); 1478 frames.min = 64; 1479 frames.integer = 1; 1480 1481 return snd_interval_refine(period_size, &frames); 1482 } 1483 1484 static int davinci_mcasp_startup(struct snd_pcm_substream *substream, 1485 struct snd_soc_dai *cpu_dai) 1486 { 1487 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1488 struct davinci_mcasp_ruledata *ruledata = 1489 &mcasp->ruledata[substream->stream]; 1490 u32 max_channels = 0; 1491 int i, dir, ret; 1492 int tdm_slots = mcasp->tdm_slots; 1493 1494 /* Do not allow more then one stream per direction */ 1495 if (mcasp->substreams[substream->stream]) 1496 return -EBUSY; 1497 1498 mcasp->substreams[substream->stream] = substream; 1499 1500 if (mcasp->tdm_mask[substream->stream]) 1501 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]); 1502 1503 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1504 return 0; 1505 1506 /* 1507 * Limit the maximum allowed channels for the first stream: 1508 * number of serializers for the direction * tdm slots per serializer 1509 */ 1510 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1511 dir = TX_MODE; 1512 else 1513 dir = RX_MODE; 1514 1515 for (i = 0; i < mcasp->num_serializer; i++) { 1516 if (mcasp->serial_dir[i] == dir) 1517 max_channels++; 1518 } 1519 ruledata->serializers = max_channels; 1520 ruledata->mcasp = mcasp; 1521 max_channels *= tdm_slots; 1522 /* 1523 * If the already active stream has less channels than the calculated 1524 * limit based on the seirializers * tdm_slots, and only one serializer 1525 * is in use we need to use that as a constraint for the second stream. 1526 * Otherwise (first stream or less allowed channels or more than one 1527 * serializer in use) we use the calculated constraint. 1528 */ 1529 if (mcasp->channels && mcasp->channels < max_channels && 1530 ruledata->serializers == 1) 1531 max_channels = mcasp->channels; 1532 /* 1533 * But we can always allow channels upto the amount of 1534 * the available tdm_slots. 1535 */ 1536 if (max_channels < tdm_slots) 1537 max_channels = tdm_slots; 1538 1539 snd_pcm_hw_constraint_minmax(substream->runtime, 1540 SNDRV_PCM_HW_PARAM_CHANNELS, 1541 0, max_channels); 1542 1543 snd_pcm_hw_constraint_list(substream->runtime, 1544 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1545 &mcasp->chconstr[substream->stream]); 1546 1547 if (mcasp->max_format_width) { 1548 /* 1549 * Only allow formats which require same amount of bits on the 1550 * bus as the currently running stream 1551 */ 1552 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1553 SNDRV_PCM_HW_PARAM_FORMAT, 1554 davinci_mcasp_hw_rule_format_width, 1555 ruledata, 1556 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1557 if (ret) 1558 return ret; 1559 } 1560 else if (mcasp->slot_width) { 1561 /* Only allow formats require <= slot_width bits on the bus */ 1562 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1563 SNDRV_PCM_HW_PARAM_FORMAT, 1564 davinci_mcasp_hw_rule_slot_width, 1565 ruledata, 1566 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1567 if (ret) 1568 return ret; 1569 } 1570 1571 /* 1572 * If we rely on implicit BCLK divider setting we should 1573 * set constraints based on what we can provide. 1574 */ 1575 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { 1576 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1577 SNDRV_PCM_HW_PARAM_RATE, 1578 davinci_mcasp_hw_rule_rate, 1579 ruledata, 1580 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1581 if (ret) 1582 return ret; 1583 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1584 SNDRV_PCM_HW_PARAM_FORMAT, 1585 davinci_mcasp_hw_rule_format, 1586 ruledata, 1587 SNDRV_PCM_HW_PARAM_RATE, -1); 1588 if (ret) 1589 return ret; 1590 } 1591 1592 snd_pcm_hw_rule_add(substream->runtime, 0, 1593 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 1594 davinci_mcasp_hw_rule_min_periodsize, NULL, 1595 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1); 1596 1597 return 0; 1598 } 1599 1600 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream, 1601 struct snd_soc_dai *cpu_dai) 1602 { 1603 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1604 1605 mcasp->substreams[substream->stream] = NULL; 1606 mcasp->active_serializers[substream->stream] = 0; 1607 1608 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1609 return; 1610 1611 if (!snd_soc_dai_active(cpu_dai)) { 1612 mcasp->channels = 0; 1613 mcasp->max_format_width = 0; 1614 } 1615 } 1616 1617 static int davinci_mcasp_iec958_info(struct snd_kcontrol *kcontrol, 1618 struct snd_ctl_elem_info *uinfo) 1619 { 1620 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1621 uinfo->count = 1; 1622 1623 return 0; 1624 } 1625 1626 static int davinci_mcasp_iec958_get(struct snd_kcontrol *kcontrol, 1627 struct snd_ctl_elem_value *uctl) 1628 { 1629 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1630 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1631 1632 memcpy(uctl->value.iec958.status, &mcasp->iec958_status, 1633 sizeof(mcasp->iec958_status)); 1634 1635 return 0; 1636 } 1637 1638 static int davinci_mcasp_iec958_put(struct snd_kcontrol *kcontrol, 1639 struct snd_ctl_elem_value *uctl) 1640 { 1641 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1642 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1643 1644 memcpy(&mcasp->iec958_status, uctl->value.iec958.status, 1645 sizeof(mcasp->iec958_status)); 1646 1647 return 0; 1648 } 1649 1650 static int davinci_mcasp_iec958_con_mask_get(struct snd_kcontrol *kcontrol, 1651 struct snd_ctl_elem_value *ucontrol) 1652 { 1653 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1654 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1655 1656 memset(ucontrol->value.iec958.status, 0xff, sizeof(mcasp->iec958_status)); 1657 return 0; 1658 } 1659 1660 static const struct snd_kcontrol_new davinci_mcasp_iec958_ctls[] = { 1661 { 1662 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 1663 SNDRV_CTL_ELEM_ACCESS_VOLATILE), 1664 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1665 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1666 .info = davinci_mcasp_iec958_info, 1667 .get = davinci_mcasp_iec958_get, 1668 .put = davinci_mcasp_iec958_put, 1669 }, { 1670 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1671 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1672 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK), 1673 .info = davinci_mcasp_iec958_info, 1674 .get = davinci_mcasp_iec958_con_mask_get, 1675 }, 1676 }; 1677 1678 static void davinci_mcasp_init_iec958_status(struct davinci_mcasp *mcasp) 1679 { 1680 unsigned char *cs = (u8 *)&mcasp->iec958_status; 1681 1682 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; 1683 cs[1] = IEC958_AES1_CON_PCM_CODER; 1684 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; 1685 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM; 1686 } 1687 1688 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) 1689 { 1690 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 1691 int stream; 1692 1693 for_each_pcm_streams(stream) 1694 snd_soc_dai_dma_data_set(dai, stream, &mcasp->dma_data[stream]); 1695 1696 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) { 1697 davinci_mcasp_init_iec958_status(mcasp); 1698 snd_soc_add_dai_controls(dai, davinci_mcasp_iec958_ctls, 1699 ARRAY_SIZE(davinci_mcasp_iec958_ctls)); 1700 } 1701 1702 return 0; 1703 } 1704 1705 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { 1706 .probe = davinci_mcasp_dai_probe, 1707 .startup = davinci_mcasp_startup, 1708 .shutdown = davinci_mcasp_shutdown, 1709 .trigger = davinci_mcasp_trigger, 1710 .delay = davinci_mcasp_delay, 1711 .hw_params = davinci_mcasp_hw_params, 1712 .set_fmt = davinci_mcasp_set_dai_fmt, 1713 .set_clkdiv = davinci_mcasp_set_clkdiv, 1714 .set_sysclk = davinci_mcasp_set_sysclk, 1715 .set_tdm_slot = davinci_mcasp_set_tdm_slot, 1716 }; 1717 1718 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 1719 1720 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ 1721 SNDRV_PCM_FMTBIT_U8 | \ 1722 SNDRV_PCM_FMTBIT_S16_LE | \ 1723 SNDRV_PCM_FMTBIT_U16_LE | \ 1724 SNDRV_PCM_FMTBIT_S24_LE | \ 1725 SNDRV_PCM_FMTBIT_U24_LE | \ 1726 SNDRV_PCM_FMTBIT_S24_3LE | \ 1727 SNDRV_PCM_FMTBIT_U24_3LE | \ 1728 SNDRV_PCM_FMTBIT_S32_LE | \ 1729 SNDRV_PCM_FMTBIT_U32_LE) 1730 1731 static struct snd_soc_dai_driver davinci_mcasp_dai[] = { 1732 { 1733 .name = "davinci-mcasp.0", 1734 .playback = { 1735 .stream_name = "IIS Playback", 1736 .channels_min = 1, 1737 .channels_max = 32 * 16, 1738 .rates = DAVINCI_MCASP_RATES, 1739 .formats = DAVINCI_MCASP_PCM_FMTS, 1740 }, 1741 .capture = { 1742 .stream_name = "IIS Capture", 1743 .channels_min = 1, 1744 .channels_max = 32 * 16, 1745 .rates = DAVINCI_MCASP_RATES, 1746 .formats = DAVINCI_MCASP_PCM_FMTS, 1747 }, 1748 .ops = &davinci_mcasp_dai_ops, 1749 1750 .symmetric_rate = 1, 1751 }, 1752 { 1753 .name = "davinci-mcasp.1", 1754 .playback = { 1755 .stream_name = "DIT Playback", 1756 .channels_min = 1, 1757 .channels_max = 384, 1758 .rates = DAVINCI_MCASP_RATES, 1759 .formats = SNDRV_PCM_FMTBIT_S16_LE | 1760 SNDRV_PCM_FMTBIT_S24_LE, 1761 }, 1762 .ops = &davinci_mcasp_dai_ops, 1763 }, 1764 1765 }; 1766 1767 static const struct snd_soc_component_driver davinci_mcasp_component = { 1768 .name = "davinci-mcasp", 1769 .legacy_dai_naming = 1, 1770 }; 1771 1772 /* Some HW specific values and defaults. The rest is filled in from DT. */ 1773 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { 1774 .tx_dma_offset = 0x400, 1775 .rx_dma_offset = 0x400, 1776 .version = MCASP_VERSION_1, 1777 }; 1778 1779 static struct davinci_mcasp_pdata da830_mcasp_pdata = { 1780 .tx_dma_offset = 0x2000, 1781 .rx_dma_offset = 0x2000, 1782 .version = MCASP_VERSION_2, 1783 }; 1784 1785 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { 1786 .tx_dma_offset = 0, 1787 .rx_dma_offset = 0, 1788 .version = MCASP_VERSION_3, 1789 }; 1790 1791 static struct davinci_mcasp_pdata dra7_mcasp_pdata = { 1792 /* The CFG port offset will be calculated if it is needed */ 1793 .tx_dma_offset = 0, 1794 .rx_dma_offset = 0, 1795 .version = MCASP_VERSION_4, 1796 }; 1797 1798 static struct davinci_mcasp_pdata omap_mcasp_pdata = { 1799 .tx_dma_offset = 0x200, 1800 .rx_dma_offset = 0, 1801 .version = MCASP_VERSION_OMAP, 1802 }; 1803 1804 static const struct of_device_id mcasp_dt_ids[] = { 1805 { 1806 .compatible = "ti,dm646x-mcasp-audio", 1807 .data = &dm646x_mcasp_pdata, 1808 }, 1809 { 1810 .compatible = "ti,da830-mcasp-audio", 1811 .data = &da830_mcasp_pdata, 1812 }, 1813 { 1814 .compatible = "ti,am33xx-mcasp-audio", 1815 .data = &am33xx_mcasp_pdata, 1816 }, 1817 { 1818 .compatible = "ti,dra7-mcasp-audio", 1819 .data = &dra7_mcasp_pdata, 1820 }, 1821 { 1822 .compatible = "ti,omap4-mcasp-audio", 1823 .data = &omap_mcasp_pdata, 1824 }, 1825 { /* sentinel */ } 1826 }; 1827 MODULE_DEVICE_TABLE(of, mcasp_dt_ids); 1828 1829 static int mcasp_reparent_fck(struct platform_device *pdev) 1830 { 1831 struct device_node *node = pdev->dev.of_node; 1832 struct clk *gfclk, *parent_clk; 1833 const char *parent_name; 1834 int ret; 1835 1836 if (!node) 1837 return 0; 1838 1839 parent_name = of_get_property(node, "fck_parent", NULL); 1840 if (!parent_name) 1841 return 0; 1842 1843 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n"); 1844 1845 gfclk = clk_get(&pdev->dev, "fck"); 1846 if (IS_ERR(gfclk)) { 1847 dev_err(&pdev->dev, "failed to get fck\n"); 1848 return PTR_ERR(gfclk); 1849 } 1850 1851 parent_clk = clk_get(NULL, parent_name); 1852 if (IS_ERR(parent_clk)) { 1853 dev_err(&pdev->dev, "failed to get parent clock\n"); 1854 ret = PTR_ERR(parent_clk); 1855 goto err1; 1856 } 1857 1858 ret = clk_set_parent(gfclk, parent_clk); 1859 if (ret) { 1860 dev_err(&pdev->dev, "failed to reparent fck\n"); 1861 goto err2; 1862 } 1863 1864 err2: 1865 clk_put(parent_clk); 1866 err1: 1867 clk_put(gfclk); 1868 return ret; 1869 } 1870 1871 static bool davinci_mcasp_have_gpiochip(struct davinci_mcasp *mcasp) 1872 { 1873 #ifdef CONFIG_OF_GPIO 1874 return of_property_read_bool(mcasp->dev->of_node, "gpio-controller"); 1875 #else 1876 return false; 1877 #endif 1878 } 1879 1880 static int davinci_mcasp_get_config(struct davinci_mcasp *mcasp, 1881 struct platform_device *pdev) 1882 { 1883 struct device_node *np = pdev->dev.of_node; 1884 struct davinci_mcasp_pdata *pdata = NULL; 1885 const struct davinci_mcasp_pdata *match_pdata = 1886 device_get_match_data(&pdev->dev); 1887 const u32 *of_serial_dir32; 1888 u32 val; 1889 int i; 1890 1891 if (pdev->dev.platform_data) { 1892 pdata = pdev->dev.platform_data; 1893 pdata->dismod = DISMOD_LOW; 1894 goto out; 1895 } else if (match_pdata) { 1896 pdata = devm_kmemdup(&pdev->dev, match_pdata, sizeof(*pdata), 1897 GFP_KERNEL); 1898 if (!pdata) 1899 return -ENOMEM; 1900 } else { 1901 dev_err(&pdev->dev, "No compatible match found\n"); 1902 return -EINVAL; 1903 } 1904 1905 if (of_property_read_u32(np, "op-mode", &val) == 0) { 1906 pdata->op_mode = val; 1907 } else { 1908 mcasp->missing_audio_param = true; 1909 goto out; 1910 } 1911 1912 if (of_property_read_u32(np, "tdm-slots", &val) == 0) { 1913 if (val < 2 || val > 32) { 1914 dev_err(&pdev->dev, "tdm-slots must be in rage [2-32]\n"); 1915 return -EINVAL; 1916 } 1917 1918 pdata->tdm_slots = val; 1919 } else if (pdata->op_mode == DAVINCI_MCASP_IIS_MODE) { 1920 mcasp->missing_audio_param = true; 1921 goto out; 1922 } 1923 1924 of_serial_dir32 = of_get_property(np, "serial-dir", &val); 1925 val /= sizeof(u32); 1926 if (of_serial_dir32) { 1927 u8 *of_serial_dir = devm_kzalloc(&pdev->dev, 1928 (sizeof(*of_serial_dir) * val), 1929 GFP_KERNEL); 1930 if (!of_serial_dir) 1931 return -ENOMEM; 1932 1933 for (i = 0; i < val; i++) 1934 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); 1935 1936 pdata->num_serializer = val; 1937 pdata->serial_dir = of_serial_dir; 1938 } else { 1939 mcasp->missing_audio_param = true; 1940 goto out; 1941 } 1942 1943 if (of_property_read_u32(np, "tx-num-evt", &val) == 0) 1944 pdata->txnumevt = val; 1945 1946 if (of_property_read_u32(np, "rx-num-evt", &val) == 0) 1947 pdata->rxnumevt = val; 1948 1949 if (of_property_read_u32(np, "auxclk-fs-ratio", &val) == 0) 1950 mcasp->auxclk_fs_ratio = val; 1951 1952 if (of_property_read_u32(np, "dismod", &val) == 0) { 1953 if (val == 0 || val == 2 || val == 3) { 1954 pdata->dismod = DISMOD_VAL(val); 1955 } else { 1956 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val); 1957 pdata->dismod = DISMOD_LOW; 1958 } 1959 } else { 1960 pdata->dismod = DISMOD_LOW; 1961 } 1962 1963 out: 1964 mcasp->pdata = pdata; 1965 1966 if (mcasp->missing_audio_param) { 1967 if (davinci_mcasp_have_gpiochip(mcasp)) { 1968 dev_dbg(&pdev->dev, "Missing DT parameter(s) for audio\n"); 1969 return 0; 1970 } 1971 1972 dev_err(&pdev->dev, "Insufficient DT parameter(s)\n"); 1973 return -ENODEV; 1974 } 1975 1976 mcasp->op_mode = pdata->op_mode; 1977 /* sanity check for tdm slots parameter */ 1978 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { 1979 if (pdata->tdm_slots < 2) { 1980 dev_warn(&pdev->dev, "invalid tdm slots: %d\n", 1981 pdata->tdm_slots); 1982 mcasp->tdm_slots = 2; 1983 } else if (pdata->tdm_slots > 32) { 1984 dev_warn(&pdev->dev, "invalid tdm slots: %d\n", 1985 pdata->tdm_slots); 1986 mcasp->tdm_slots = 32; 1987 } else { 1988 mcasp->tdm_slots = pdata->tdm_slots; 1989 } 1990 } else { 1991 mcasp->tdm_slots = 32; 1992 } 1993 1994 mcasp->num_serializer = pdata->num_serializer; 1995 #ifdef CONFIG_PM 1996 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev, 1997 mcasp->num_serializer, sizeof(u32), 1998 GFP_KERNEL); 1999 if (!mcasp->context.xrsr_regs) 2000 return -ENOMEM; 2001 #endif 2002 mcasp->serial_dir = pdata->serial_dir; 2003 mcasp->version = pdata->version; 2004 mcasp->txnumevt = pdata->txnumevt; 2005 mcasp->rxnumevt = pdata->rxnumevt; 2006 mcasp->dismod = pdata->dismod; 2007 2008 return 0; 2009 } 2010 2011 enum { 2012 PCM_EDMA, 2013 PCM_SDMA, 2014 PCM_UDMA, 2015 }; 2016 static const char *sdma_prefix = "ti,omap"; 2017 2018 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp) 2019 { 2020 struct dma_chan *chan; 2021 const char *tmp; 2022 int ret = PCM_EDMA; 2023 2024 if (!mcasp->dev->of_node) 2025 return PCM_EDMA; 2026 2027 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data; 2028 chan = dma_request_chan(mcasp->dev, tmp); 2029 if (IS_ERR(chan)) 2030 return dev_err_probe(mcasp->dev, PTR_ERR(chan), 2031 "Can't verify DMA configuration\n"); 2032 if (WARN_ON(!chan->device || !chan->device->dev)) { 2033 dma_release_channel(chan); 2034 return -EINVAL; 2035 } 2036 2037 if (chan->device->dev->of_node) 2038 ret = of_property_read_string(chan->device->dev->of_node, 2039 "compatible", &tmp); 2040 else 2041 dev_dbg(mcasp->dev, "DMA controller has no of-node\n"); 2042 2043 dma_release_channel(chan); 2044 if (ret) 2045 return ret; 2046 2047 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp); 2048 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix))) 2049 return PCM_SDMA; 2050 else if (strstr(tmp, "udmap")) 2051 return PCM_UDMA; 2052 else if (strstr(tmp, "bcdma")) 2053 return PCM_UDMA; 2054 2055 return PCM_EDMA; 2056 } 2057 2058 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata) 2059 { 2060 int i; 2061 u32 offset = 0; 2062 2063 if (pdata->version != MCASP_VERSION_4) 2064 return pdata->tx_dma_offset; 2065 2066 for (i = 0; i < pdata->num_serializer; i++) { 2067 if (pdata->serial_dir[i] == TX_MODE) { 2068 if (!offset) { 2069 offset = DAVINCI_MCASP_TXBUF_REG(i); 2070 } else { 2071 pr_err("%s: Only one serializer allowed!\n", 2072 __func__); 2073 break; 2074 } 2075 } 2076 } 2077 2078 return offset; 2079 } 2080 2081 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata) 2082 { 2083 int i; 2084 u32 offset = 0; 2085 2086 if (pdata->version != MCASP_VERSION_4) 2087 return pdata->rx_dma_offset; 2088 2089 for (i = 0; i < pdata->num_serializer; i++) { 2090 if (pdata->serial_dir[i] == RX_MODE) { 2091 if (!offset) { 2092 offset = DAVINCI_MCASP_RXBUF_REG(i); 2093 } else { 2094 pr_err("%s: Only one serializer allowed!\n", 2095 __func__); 2096 break; 2097 } 2098 } 2099 } 2100 2101 return offset; 2102 } 2103 2104 #ifdef CONFIG_GPIOLIB 2105 static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset) 2106 { 2107 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2108 2109 if (mcasp->num_serializer && offset < mcasp->num_serializer && 2110 mcasp->serial_dir[offset] != INACTIVE_MODE) { 2111 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset); 2112 return -EBUSY; 2113 } 2114 2115 /* Do not change the PIN yet */ 2116 return pm_runtime_resume_and_get(mcasp->dev); 2117 } 2118 2119 static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset) 2120 { 2121 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2122 2123 /* Set the direction to input */ 2124 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 2125 2126 /* Set the pin as McASP pin */ 2127 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 2128 2129 pm_runtime_put_sync(mcasp->dev); 2130 } 2131 2132 static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip, 2133 unsigned offset, int value) 2134 { 2135 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2136 u32 val; 2137 2138 if (value) 2139 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2140 else 2141 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2142 2143 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); 2144 if (!(val & BIT(offset))) { 2145 /* Set the pin as GPIO pin */ 2146 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 2147 2148 /* Set the direction to output */ 2149 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 2150 } 2151 2152 return 0; 2153 } 2154 2155 static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset, 2156 int value) 2157 { 2158 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2159 2160 if (value) 2161 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2162 else 2163 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2164 } 2165 2166 static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip, 2167 unsigned offset) 2168 { 2169 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2170 u32 val; 2171 2172 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); 2173 if (!(val & BIT(offset))) { 2174 /* Set the direction to input */ 2175 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 2176 2177 /* Set the pin as GPIO pin */ 2178 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 2179 } 2180 2181 return 0; 2182 } 2183 2184 static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset) 2185 { 2186 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2187 u32 val; 2188 2189 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG); 2190 if (val & BIT(offset)) 2191 return 1; 2192 2193 return 0; 2194 } 2195 2196 static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip, 2197 unsigned offset) 2198 { 2199 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2200 u32 val; 2201 2202 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG); 2203 if (val & BIT(offset)) 2204 return 0; 2205 2206 return 1; 2207 } 2208 2209 static const struct gpio_chip davinci_mcasp_template_chip = { 2210 .owner = THIS_MODULE, 2211 .request = davinci_mcasp_gpio_request, 2212 .free = davinci_mcasp_gpio_free, 2213 .direction_output = davinci_mcasp_gpio_direction_out, 2214 .set = davinci_mcasp_gpio_set, 2215 .direction_input = davinci_mcasp_gpio_direction_in, 2216 .get = davinci_mcasp_gpio_get, 2217 .get_direction = davinci_mcasp_gpio_get_direction, 2218 .base = -1, 2219 .ngpio = 32, 2220 }; 2221 2222 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) 2223 { 2224 if (!davinci_mcasp_have_gpiochip(mcasp)) 2225 return 0; 2226 2227 mcasp->gpio_chip = davinci_mcasp_template_chip; 2228 mcasp->gpio_chip.label = dev_name(mcasp->dev); 2229 mcasp->gpio_chip.parent = mcasp->dev; 2230 2231 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp); 2232 } 2233 2234 #else /* CONFIG_GPIOLIB */ 2235 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) 2236 { 2237 return 0; 2238 } 2239 #endif /* CONFIG_GPIOLIB */ 2240 2241 static int davinci_mcasp_probe(struct platform_device *pdev) 2242 { 2243 struct snd_dmaengine_dai_dma_data *dma_data; 2244 struct resource *mem, *dat; 2245 struct davinci_mcasp *mcasp; 2246 char *irq_name; 2247 int irq; 2248 int ret; 2249 2250 if (!pdev->dev.platform_data && !pdev->dev.of_node) { 2251 dev_err(&pdev->dev, "No platform data supplied\n"); 2252 return -EINVAL; 2253 } 2254 2255 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), 2256 GFP_KERNEL); 2257 if (!mcasp) 2258 return -ENOMEM; 2259 2260 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); 2261 if (!mem) { 2262 dev_warn(&pdev->dev, 2263 "\"mpu\" mem resource not found, using index 0\n"); 2264 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2265 if (!mem) { 2266 dev_err(&pdev->dev, "no mem resource?\n"); 2267 return -ENODEV; 2268 } 2269 } 2270 2271 mcasp->base = devm_ioremap_resource(&pdev->dev, mem); 2272 if (IS_ERR(mcasp->base)) 2273 return PTR_ERR(mcasp->base); 2274 2275 dev_set_drvdata(&pdev->dev, mcasp); 2276 pm_runtime_enable(&pdev->dev); 2277 2278 mcasp->dev = &pdev->dev; 2279 ret = davinci_mcasp_get_config(mcasp, pdev); 2280 if (ret) 2281 goto err; 2282 2283 /* All PINS as McASP */ 2284 pm_runtime_get_sync(mcasp->dev); 2285 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); 2286 pm_runtime_put(mcasp->dev); 2287 2288 /* Skip audio related setup code if the configuration is not adequat */ 2289 if (mcasp->missing_audio_param) 2290 goto no_audio; 2291 2292 irq = platform_get_irq_byname_optional(pdev, "common"); 2293 if (irq > 0) { 2294 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common", 2295 dev_name(&pdev->dev)); 2296 if (!irq_name) { 2297 ret = -ENOMEM; 2298 goto err; 2299 } 2300 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2301 davinci_mcasp_common_irq_handler, 2302 IRQF_ONESHOT | IRQF_SHARED, 2303 irq_name, mcasp); 2304 if (ret) { 2305 dev_err(&pdev->dev, "common IRQ request failed\n"); 2306 goto err; 2307 } 2308 2309 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; 2310 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; 2311 } 2312 2313 irq = platform_get_irq_byname_optional(pdev, "rx"); 2314 if (irq > 0) { 2315 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx", 2316 dev_name(&pdev->dev)); 2317 if (!irq_name) { 2318 ret = -ENOMEM; 2319 goto err; 2320 } 2321 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2322 davinci_mcasp_rx_irq_handler, 2323 IRQF_ONESHOT, irq_name, mcasp); 2324 if (ret) { 2325 dev_err(&pdev->dev, "RX IRQ request failed\n"); 2326 goto err; 2327 } 2328 2329 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; 2330 } 2331 2332 irq = platform_get_irq_byname_optional(pdev, "tx"); 2333 if (irq > 0) { 2334 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx", 2335 dev_name(&pdev->dev)); 2336 if (!irq_name) { 2337 ret = -ENOMEM; 2338 goto err; 2339 } 2340 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2341 davinci_mcasp_tx_irq_handler, 2342 IRQF_ONESHOT, irq_name, mcasp); 2343 if (ret) { 2344 dev_err(&pdev->dev, "TX IRQ request failed\n"); 2345 goto err; 2346 } 2347 2348 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; 2349 } 2350 2351 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 2352 if (dat) 2353 mcasp->dat_port = true; 2354 2355 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; 2356 dma_data->filter_data = "tx"; 2357 if (dat) { 2358 dma_data->addr = dat->start; 2359 /* 2360 * According to the TRM there should be 0x200 offset added to 2361 * the DAT port address 2362 */ 2363 if (mcasp->version == MCASP_VERSION_OMAP) 2364 dma_data->addr += davinci_mcasp_txdma_offset(mcasp->pdata); 2365 } else { 2366 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(mcasp->pdata); 2367 } 2368 2369 2370 /* RX is not valid in DIT mode */ 2371 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 2372 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; 2373 dma_data->filter_data = "rx"; 2374 if (dat) 2375 dma_data->addr = dat->start; 2376 else 2377 dma_data->addr = 2378 mem->start + davinci_mcasp_rxdma_offset(mcasp->pdata); 2379 } 2380 2381 if (mcasp->version < MCASP_VERSION_3) { 2382 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; 2383 /* dma_params->dma_addr is pointing to the data port address */ 2384 mcasp->dat_port = true; 2385 } else { 2386 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; 2387 } 2388 2389 /* Allocate memory for long enough list for all possible 2390 * scenarios. Maximum number tdm slots is 32 and there cannot 2391 * be more serializers than given in the configuration. The 2392 * serializer directions could be taken into account, but it 2393 * would make code much more complex and save only couple of 2394 * bytes. 2395 */ 2396 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list = 2397 devm_kcalloc(mcasp->dev, 2398 32 + mcasp->num_serializer - 1, 2399 sizeof(unsigned int), 2400 GFP_KERNEL); 2401 2402 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list = 2403 devm_kcalloc(mcasp->dev, 2404 32 + mcasp->num_serializer - 1, 2405 sizeof(unsigned int), 2406 GFP_KERNEL); 2407 2408 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list || 2409 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) { 2410 ret = -ENOMEM; 2411 goto err; 2412 } 2413 2414 ret = davinci_mcasp_set_ch_constraints(mcasp); 2415 if (ret) 2416 goto err; 2417 2418 mcasp_reparent_fck(pdev); 2419 2420 ret = devm_snd_soc_register_component(&pdev->dev, &davinci_mcasp_component, 2421 &davinci_mcasp_dai[mcasp->op_mode], 1); 2422 2423 if (ret != 0) 2424 goto err; 2425 2426 ret = davinci_mcasp_get_dma_type(mcasp); 2427 switch (ret) { 2428 case PCM_EDMA: 2429 ret = edma_pcm_platform_register(&pdev->dev); 2430 break; 2431 case PCM_SDMA: 2432 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) 2433 ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx"); 2434 else 2435 ret = sdma_pcm_platform_register(&pdev->dev, "tx", NULL); 2436 break; 2437 case PCM_UDMA: 2438 ret = udma_pcm_platform_register(&pdev->dev); 2439 break; 2440 default: 2441 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret); 2442 fallthrough; 2443 case -EPROBE_DEFER: 2444 goto err; 2445 } 2446 2447 if (ret) { 2448 dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 2449 goto err; 2450 } 2451 2452 no_audio: 2453 ret = davinci_mcasp_init_gpiochip(mcasp); 2454 if (ret) { 2455 dev_err(&pdev->dev, "gpiochip registration failed: %d\n", ret); 2456 goto err; 2457 } 2458 2459 return 0; 2460 err: 2461 pm_runtime_disable(&pdev->dev); 2462 return ret; 2463 } 2464 2465 static void davinci_mcasp_remove(struct platform_device *pdev) 2466 { 2467 pm_runtime_disable(&pdev->dev); 2468 } 2469 2470 #ifdef CONFIG_PM 2471 static int davinci_mcasp_runtime_suspend(struct device *dev) 2472 { 2473 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 2474 struct davinci_mcasp_context *context = &mcasp->context; 2475 u32 reg; 2476 int i; 2477 2478 for (i = 0; i < ARRAY_SIZE(context_regs); i++) 2479 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); 2480 2481 if (mcasp->txnumevt) { 2482 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 2483 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); 2484 } 2485 if (mcasp->rxnumevt) { 2486 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 2487 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); 2488 } 2489 2490 for (i = 0; i < mcasp->num_serializer; i++) 2491 context->xrsr_regs[i] = mcasp_get_reg(mcasp, 2492 DAVINCI_MCASP_XRSRCTL_REG(i)); 2493 2494 return 0; 2495 } 2496 2497 static int davinci_mcasp_runtime_resume(struct device *dev) 2498 { 2499 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 2500 struct davinci_mcasp_context *context = &mcasp->context; 2501 u32 reg; 2502 int i; 2503 2504 for (i = 0; i < ARRAY_SIZE(context_regs); i++) 2505 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); 2506 2507 if (mcasp->txnumevt) { 2508 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 2509 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); 2510 } 2511 if (mcasp->rxnumevt) { 2512 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 2513 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); 2514 } 2515 2516 for (i = 0; i < mcasp->num_serializer; i++) 2517 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 2518 context->xrsr_regs[i]); 2519 2520 return 0; 2521 } 2522 2523 #endif 2524 2525 static const struct dev_pm_ops davinci_mcasp_pm_ops = { 2526 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend, 2527 davinci_mcasp_runtime_resume, 2528 NULL) 2529 }; 2530 2531 static struct platform_driver davinci_mcasp_driver = { 2532 .probe = davinci_mcasp_probe, 2533 .remove_new = davinci_mcasp_remove, 2534 .driver = { 2535 .name = "davinci-mcasp", 2536 .pm = &davinci_mcasp_pm_ops, 2537 .of_match_table = mcasp_dt_ids, 2538 }, 2539 }; 2540 2541 module_platform_driver(davinci_mcasp_driver); 2542 2543 MODULE_AUTHOR("Steve Chen"); 2544 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); 2545 MODULE_LICENSE("GPL"); 2546