1 /* 2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor 3 * 4 * Multi-channel Audio Serial Port Driver 5 * 6 * Author: Nirmal Pandey <n-pandey@ti.com>, 7 * Suresh Rajashekara <suresh.r@ti.com> 8 * Steve Chen <schen@.mvista.com> 9 * 10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> 11 * Copyright: (C) 2009 Texas Instruments, India 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License version 2 as 15 * published by the Free Software Foundation. 16 */ 17 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/device.h> 21 #include <linux/slab.h> 22 #include <linux/delay.h> 23 #include <linux/io.h> 24 #include <linux/clk.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/of.h> 27 #include <linux/of_platform.h> 28 #include <linux/of_device.h> 29 #include <linux/platform_data/davinci_asp.h> 30 #include <linux/math64.h> 31 #include <linux/bitmap.h> 32 33 #include <sound/asoundef.h> 34 #include <sound/core.h> 35 #include <sound/pcm.h> 36 #include <sound/pcm_params.h> 37 #include <sound/initval.h> 38 #include <sound/soc.h> 39 #include <sound/dmaengine_pcm.h> 40 41 #include "edma-pcm.h" 42 #include "sdma-pcm.h" 43 #include "davinci-mcasp.h" 44 45 #define MCASP_MAX_AFIFO_DEPTH 64 46 47 static u32 context_regs[] = { 48 DAVINCI_MCASP_TXFMCTL_REG, 49 DAVINCI_MCASP_RXFMCTL_REG, 50 DAVINCI_MCASP_TXFMT_REG, 51 DAVINCI_MCASP_RXFMT_REG, 52 DAVINCI_MCASP_ACLKXCTL_REG, 53 DAVINCI_MCASP_ACLKRCTL_REG, 54 DAVINCI_MCASP_AHCLKXCTL_REG, 55 DAVINCI_MCASP_AHCLKRCTL_REG, 56 DAVINCI_MCASP_PDIR_REG, 57 DAVINCI_MCASP_RXMASK_REG, 58 DAVINCI_MCASP_TXMASK_REG, 59 DAVINCI_MCASP_RXTDM_REG, 60 DAVINCI_MCASP_TXTDM_REG, 61 }; 62 63 struct davinci_mcasp_context { 64 u32 config_regs[ARRAY_SIZE(context_regs)]; 65 u32 afifo_regs[2]; /* for read/write fifo control registers */ 66 u32 *xrsr_regs; /* for serializer configuration */ 67 bool pm_state; 68 }; 69 70 struct davinci_mcasp_ruledata { 71 struct davinci_mcasp *mcasp; 72 int serializers; 73 }; 74 75 struct davinci_mcasp { 76 struct snd_dmaengine_dai_dma_data dma_data[2]; 77 void __iomem *base; 78 u32 fifo_base; 79 struct device *dev; 80 struct snd_pcm_substream *substreams[2]; 81 unsigned int dai_fmt; 82 83 /* McASP specific data */ 84 int tdm_slots; 85 u32 tdm_mask[2]; 86 int slot_width; 87 u8 op_mode; 88 u8 dismod; 89 u8 num_serializer; 90 u8 *serial_dir; 91 u8 version; 92 u8 bclk_div; 93 int streams; 94 u32 irq_request[2]; 95 int dma_request[2]; 96 97 int sysclk_freq; 98 bool bclk_master; 99 100 unsigned long pdir; /* Pin direction bitfield */ 101 102 /* McASP FIFO related */ 103 u8 txnumevt; 104 u8 rxnumevt; 105 106 bool dat_port; 107 108 /* Used for comstraint setting on the second stream */ 109 u32 channels; 110 111 #ifdef CONFIG_PM 112 struct davinci_mcasp_context context; 113 #endif 114 115 struct davinci_mcasp_ruledata ruledata[2]; 116 struct snd_pcm_hw_constraint_list chconstr[2]; 117 }; 118 119 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, 120 u32 val) 121 { 122 void __iomem *reg = mcasp->base + offset; 123 __raw_writel(__raw_readl(reg) | val, reg); 124 } 125 126 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, 127 u32 val) 128 { 129 void __iomem *reg = mcasp->base + offset; 130 __raw_writel((__raw_readl(reg) & ~(val)), reg); 131 } 132 133 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, 134 u32 val, u32 mask) 135 { 136 void __iomem *reg = mcasp->base + offset; 137 __raw_writel((__raw_readl(reg) & ~mask) | val, reg); 138 } 139 140 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, 141 u32 val) 142 { 143 __raw_writel(val, mcasp->base + offset); 144 } 145 146 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) 147 { 148 return (u32)__raw_readl(mcasp->base + offset); 149 } 150 151 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) 152 { 153 int i = 0; 154 155 mcasp_set_bits(mcasp, ctl_reg, val); 156 157 /* programming GBLCTL needs to read back from GBLCTL and verfiy */ 158 /* loop count is to avoid the lock-up */ 159 for (i = 0; i < 1000; i++) { 160 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) 161 break; 162 } 163 164 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) 165 printk(KERN_ERR "GBLCTL write error\n"); 166 } 167 168 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) 169 { 170 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); 171 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); 172 173 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; 174 } 175 176 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable) 177 { 178 u32 bit = PIN_BIT_AMUTE; 179 180 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) { 181 if (enable) 182 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 183 else 184 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 185 } 186 } 187 188 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable) 189 { 190 u32 bit; 191 192 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AFSR) { 193 if (enable) 194 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 195 else 196 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 197 } 198 } 199 200 static void mcasp_start_rx(struct davinci_mcasp *mcasp) 201 { 202 if (mcasp->rxnumevt) { /* enable FIFO */ 203 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 204 205 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 206 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); 207 } 208 209 /* Start clocks */ 210 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); 211 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); 212 /* 213 * When ASYNC == 0 the transmit and receive sections operate 214 * synchronously from the transmit clock and frame sync. We need to make 215 * sure that the TX signlas are enabled when starting reception. 216 */ 217 if (mcasp_is_synchronous(mcasp)) { 218 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 219 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 220 } 221 222 /* Activate serializer(s) */ 223 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 224 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); 225 /* Release RX state machine */ 226 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); 227 /* Release Frame Sync generator */ 228 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); 229 if (mcasp_is_synchronous(mcasp)) 230 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 231 232 /* enable receive IRQs */ 233 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, 234 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); 235 } 236 237 static void mcasp_start_tx(struct davinci_mcasp *mcasp) 238 { 239 u32 cnt; 240 241 if (mcasp->txnumevt) { /* enable FIFO */ 242 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 243 244 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 245 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); 246 } 247 248 /* Start clocks */ 249 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 250 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 251 mcasp_set_clk_pdir(mcasp, true); 252 253 /* Activate serializer(s) */ 254 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 255 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); 256 257 /* wait for XDATA to be cleared */ 258 cnt = 0; 259 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) && 260 (cnt < 100000)) 261 cnt++; 262 263 mcasp_set_axr_pdir(mcasp, true); 264 265 /* Release TX state machine */ 266 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); 267 /* Release Frame Sync generator */ 268 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 269 270 /* enable transmit IRQs */ 271 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, 272 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); 273 } 274 275 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) 276 { 277 mcasp->streams++; 278 279 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 280 mcasp_start_tx(mcasp); 281 else 282 mcasp_start_rx(mcasp); 283 } 284 285 static void mcasp_stop_rx(struct davinci_mcasp *mcasp) 286 { 287 /* disable IRQ sources */ 288 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, 289 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); 290 291 /* 292 * In synchronous mode stop the TX clocks if no other stream is 293 * running 294 */ 295 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) { 296 mcasp_set_clk_pdir(mcasp, false); 297 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); 298 } 299 300 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); 301 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 302 303 if (mcasp->rxnumevt) { /* disable FIFO */ 304 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 305 306 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 307 } 308 } 309 310 static void mcasp_stop_tx(struct davinci_mcasp *mcasp) 311 { 312 u32 val = 0; 313 314 /* disable IRQ sources */ 315 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, 316 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); 317 318 /* 319 * In synchronous mode keep TX clocks running if the capture stream is 320 * still running. 321 */ 322 if (mcasp_is_synchronous(mcasp) && mcasp->streams) 323 val = TXHCLKRST | TXCLKRST | TXFSRST; 324 else 325 mcasp_set_clk_pdir(mcasp, false); 326 327 328 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); 329 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 330 331 if (mcasp->txnumevt) { /* disable FIFO */ 332 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 333 334 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 335 } 336 337 mcasp_set_axr_pdir(mcasp, false); 338 } 339 340 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) 341 { 342 mcasp->streams--; 343 344 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 345 mcasp_stop_tx(mcasp); 346 else 347 mcasp_stop_rx(mcasp); 348 } 349 350 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data) 351 { 352 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 353 struct snd_pcm_substream *substream; 354 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]; 355 u32 handled_mask = 0; 356 u32 stat; 357 358 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG); 359 if (stat & XUNDRN & irq_mask) { 360 dev_warn(mcasp->dev, "Transmit buffer underflow\n"); 361 handled_mask |= XUNDRN; 362 363 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]; 364 if (substream) 365 snd_pcm_stop_xrun(substream); 366 } 367 368 if (!handled_mask) 369 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n", 370 stat); 371 372 if (stat & XRERR) 373 handled_mask |= XRERR; 374 375 /* Ack the handled event only */ 376 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask); 377 378 return IRQ_RETVAL(handled_mask); 379 } 380 381 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data) 382 { 383 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 384 struct snd_pcm_substream *substream; 385 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]; 386 u32 handled_mask = 0; 387 u32 stat; 388 389 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG); 390 if (stat & ROVRN & irq_mask) { 391 dev_warn(mcasp->dev, "Receive buffer overflow\n"); 392 handled_mask |= ROVRN; 393 394 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]; 395 if (substream) 396 snd_pcm_stop_xrun(substream); 397 } 398 399 if (!handled_mask) 400 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n", 401 stat); 402 403 if (stat & XRERR) 404 handled_mask |= XRERR; 405 406 /* Ack the handled event only */ 407 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask); 408 409 return IRQ_RETVAL(handled_mask); 410 } 411 412 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data) 413 { 414 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 415 irqreturn_t ret = IRQ_NONE; 416 417 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]) 418 ret = davinci_mcasp_tx_irq_handler(irq, data); 419 420 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]) 421 ret |= davinci_mcasp_rx_irq_handler(irq, data); 422 423 return ret; 424 } 425 426 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, 427 unsigned int fmt) 428 { 429 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 430 int ret = 0; 431 u32 data_delay; 432 bool fs_pol_rising; 433 bool inv_fs = false; 434 435 if (!fmt) 436 return 0; 437 438 pm_runtime_get_sync(mcasp->dev); 439 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 440 case SND_SOC_DAIFMT_DSP_A: 441 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 442 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 443 /* 1st data bit occur one ACLK cycle after the frame sync */ 444 data_delay = 1; 445 break; 446 case SND_SOC_DAIFMT_DSP_B: 447 case SND_SOC_DAIFMT_AC97: 448 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 449 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 450 /* No delay after FS */ 451 data_delay = 0; 452 break; 453 case SND_SOC_DAIFMT_I2S: 454 /* configure a full-word SYNC pulse (LRCLK) */ 455 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 456 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 457 /* 1st data bit occur one ACLK cycle after the frame sync */ 458 data_delay = 1; 459 /* FS need to be inverted */ 460 inv_fs = true; 461 break; 462 case SND_SOC_DAIFMT_LEFT_J: 463 /* configure a full-word SYNC pulse (LRCLK) */ 464 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 465 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 466 /* No delay after FS */ 467 data_delay = 0; 468 break; 469 default: 470 ret = -EINVAL; 471 goto out; 472 } 473 474 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), 475 FSXDLY(3)); 476 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), 477 FSRDLY(3)); 478 479 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 480 case SND_SOC_DAIFMT_CBS_CFS: 481 /* codec is clock and frame slave */ 482 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 483 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 484 485 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 486 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 487 488 /* BCLK */ 489 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); 490 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); 491 /* Frame Sync */ 492 set_bit(PIN_BIT_AFSX, &mcasp->pdir); 493 set_bit(PIN_BIT_AFSR, &mcasp->pdir); 494 495 mcasp->bclk_master = 1; 496 break; 497 case SND_SOC_DAIFMT_CBS_CFM: 498 /* codec is clock slave and frame master */ 499 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 500 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 501 502 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 503 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 504 505 /* BCLK */ 506 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); 507 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); 508 /* Frame Sync */ 509 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); 510 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); 511 512 mcasp->bclk_master = 1; 513 break; 514 case SND_SOC_DAIFMT_CBM_CFS: 515 /* codec is clock master and frame slave */ 516 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 517 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 518 519 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 520 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 521 522 /* BCLK */ 523 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); 524 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); 525 /* Frame Sync */ 526 set_bit(PIN_BIT_AFSX, &mcasp->pdir); 527 set_bit(PIN_BIT_AFSR, &mcasp->pdir); 528 529 mcasp->bclk_master = 0; 530 break; 531 case SND_SOC_DAIFMT_CBM_CFM: 532 /* codec is clock and frame master */ 533 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 534 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 535 536 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 537 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 538 539 /* BCLK */ 540 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); 541 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); 542 /* Frame Sync */ 543 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); 544 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); 545 546 mcasp->bclk_master = 0; 547 break; 548 default: 549 ret = -EINVAL; 550 goto out; 551 } 552 553 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 554 case SND_SOC_DAIFMT_IB_NF: 555 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 556 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 557 fs_pol_rising = true; 558 break; 559 case SND_SOC_DAIFMT_NB_IF: 560 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 561 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 562 fs_pol_rising = false; 563 break; 564 case SND_SOC_DAIFMT_IB_IF: 565 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 566 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 567 fs_pol_rising = false; 568 break; 569 case SND_SOC_DAIFMT_NB_NF: 570 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 571 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 572 fs_pol_rising = true; 573 break; 574 default: 575 ret = -EINVAL; 576 goto out; 577 } 578 579 if (inv_fs) 580 fs_pol_rising = !fs_pol_rising; 581 582 if (fs_pol_rising) { 583 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 584 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 585 } else { 586 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 587 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 588 } 589 590 mcasp->dai_fmt = fmt; 591 out: 592 pm_runtime_put(mcasp->dev); 593 return ret; 594 } 595 596 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id, 597 int div, bool explicit) 598 { 599 pm_runtime_get_sync(mcasp->dev); 600 switch (div_id) { 601 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */ 602 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 603 AHCLKXDIV(div - 1), AHCLKXDIV_MASK); 604 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 605 AHCLKRDIV(div - 1), AHCLKRDIV_MASK); 606 break; 607 608 case MCASP_CLKDIV_BCLK: /* BCLK divider */ 609 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, 610 ACLKXDIV(div - 1), ACLKXDIV_MASK); 611 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, 612 ACLKRDIV(div - 1), ACLKRDIV_MASK); 613 if (explicit) 614 mcasp->bclk_div = div; 615 break; 616 617 case MCASP_CLKDIV_BCLK_FS_RATIO: 618 /* 619 * BCLK/LRCLK ratio descries how many bit-clock cycles 620 * fit into one frame. The clock ratio is given for a 621 * full period of data (for I2S format both left and 622 * right channels), so it has to be divided by number 623 * of tdm-slots (for I2S - divided by 2). 624 * Instead of storing this ratio, we calculate a new 625 * tdm_slot width by dividing the the ratio by the 626 * number of configured tdm slots. 627 */ 628 mcasp->slot_width = div / mcasp->tdm_slots; 629 if (div % mcasp->tdm_slots) 630 dev_warn(mcasp->dev, 631 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots", 632 __func__, div, mcasp->tdm_slots); 633 break; 634 635 default: 636 return -EINVAL; 637 } 638 639 pm_runtime_put(mcasp->dev); 640 return 0; 641 } 642 643 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, 644 int div) 645 { 646 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 647 648 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1); 649 } 650 651 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, 652 unsigned int freq, int dir) 653 { 654 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 655 656 pm_runtime_get_sync(mcasp->dev); 657 if (dir == SND_SOC_CLOCK_OUT) { 658 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); 659 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); 660 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 661 } else { 662 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); 663 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); 664 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 665 } 666 667 mcasp->sysclk_freq = freq; 668 669 pm_runtime_put(mcasp->dev); 670 return 0; 671 } 672 673 /* All serializers must have equal number of channels */ 674 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream, 675 int serializers) 676 { 677 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream]; 678 unsigned int *list = (unsigned int *) cl->list; 679 int slots = mcasp->tdm_slots; 680 int i, count = 0; 681 682 if (mcasp->tdm_mask[stream]) 683 slots = hweight32(mcasp->tdm_mask[stream]); 684 685 for (i = 1; i <= slots; i++) 686 list[count++] = i; 687 688 for (i = 2; i <= serializers; i++) 689 list[count++] = i*slots; 690 691 cl->count = count; 692 693 return 0; 694 } 695 696 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp) 697 { 698 int rx_serializers = 0, tx_serializers = 0, ret, i; 699 700 for (i = 0; i < mcasp->num_serializer; i++) 701 if (mcasp->serial_dir[i] == TX_MODE) 702 tx_serializers++; 703 else if (mcasp->serial_dir[i] == RX_MODE) 704 rx_serializers++; 705 706 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK, 707 tx_serializers); 708 if (ret) 709 return ret; 710 711 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE, 712 rx_serializers); 713 714 return ret; 715 } 716 717 718 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai, 719 unsigned int tx_mask, 720 unsigned int rx_mask, 721 int slots, int slot_width) 722 { 723 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 724 725 dev_dbg(mcasp->dev, 726 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n", 727 __func__, tx_mask, rx_mask, slots, slot_width); 728 729 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) { 730 dev_err(mcasp->dev, 731 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n", 732 tx_mask, rx_mask, slots); 733 return -EINVAL; 734 } 735 736 if (slot_width && 737 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) { 738 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n", 739 __func__, slot_width); 740 return -EINVAL; 741 } 742 743 mcasp->tdm_slots = slots; 744 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask; 745 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask; 746 mcasp->slot_width = slot_width; 747 748 return davinci_mcasp_set_ch_constraints(mcasp); 749 } 750 751 static int davinci_config_channel_size(struct davinci_mcasp *mcasp, 752 int sample_width) 753 { 754 u32 fmt; 755 u32 tx_rotate = (sample_width / 4) & 0x7; 756 u32 mask = (1ULL << sample_width) - 1; 757 u32 slot_width = sample_width; 758 759 /* 760 * For captured data we should not rotate, inversion and masking is 761 * enoguh to get the data to the right position: 762 * Format data from bus after reverse (XRBUF) 763 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB| 764 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| 765 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| 766 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB| 767 */ 768 u32 rx_rotate = 0; 769 770 /* 771 * Setting the tdm slot width either with set_clkdiv() or 772 * set_tdm_slot() allows us to for example send 32 bits per 773 * channel to the codec, while only 16 of them carry audio 774 * payload. 775 */ 776 if (mcasp->slot_width) { 777 /* 778 * When we have more bclk then it is needed for the 779 * data, we need to use the rotation to move the 780 * received samples to have correct alignment. 781 */ 782 slot_width = mcasp->slot_width; 783 rx_rotate = (slot_width - sample_width) / 4; 784 } 785 786 /* mapping of the XSSZ bit-field as described in the datasheet */ 787 fmt = (slot_width >> 1) - 1; 788 789 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 790 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), 791 RXSSZ(0x0F)); 792 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), 793 TXSSZ(0x0F)); 794 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), 795 TXROT(7)); 796 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), 797 RXROT(7)); 798 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); 799 } 800 801 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); 802 803 return 0; 804 } 805 806 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, 807 int period_words, int channels) 808 { 809 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; 810 int i; 811 u8 tx_ser = 0; 812 u8 rx_ser = 0; 813 u8 slots = mcasp->tdm_slots; 814 u8 max_active_serializers = (channels + slots - 1) / slots; 815 int active_serializers, numevt; 816 u32 reg; 817 /* Default configuration */ 818 if (mcasp->version < MCASP_VERSION_3) 819 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); 820 821 /* All PINS as McASP */ 822 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); 823 824 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 825 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 826 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 827 } else { 828 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 829 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); 830 } 831 832 for (i = 0; i < mcasp->num_serializer; i++) { 833 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 834 mcasp->serial_dir[i]); 835 if (mcasp->serial_dir[i] == TX_MODE && 836 tx_ser < max_active_serializers) { 837 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 838 mcasp->dismod, DISMOD_MASK); 839 set_bit(PIN_BIT_AXR(i), &mcasp->pdir); 840 tx_ser++; 841 } else if (mcasp->serial_dir[i] == RX_MODE && 842 rx_ser < max_active_serializers) { 843 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 844 rx_ser++; 845 } else if (mcasp->serial_dir[i] == INACTIVE_MODE) { 846 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 847 SRMOD_INACTIVE, SRMOD_MASK); 848 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 849 } else if (mcasp->serial_dir[i] == TX_MODE) { 850 /* Unused TX pins, clear PDIR */ 851 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 852 mcasp->dismod, DISMOD_MASK); 853 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 854 } 855 } 856 857 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 858 active_serializers = tx_ser; 859 numevt = mcasp->txnumevt; 860 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 861 } else { 862 active_serializers = rx_ser; 863 numevt = mcasp->rxnumevt; 864 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 865 } 866 867 if (active_serializers < max_active_serializers) { 868 dev_warn(mcasp->dev, "stream has more channels (%d) than are " 869 "enabled in mcasp (%d)\n", channels, 870 active_serializers * slots); 871 return -EINVAL; 872 } 873 874 /* AFIFO is not in use */ 875 if (!numevt) { 876 /* Configure the burst size for platform drivers */ 877 if (active_serializers > 1) { 878 /* 879 * If more than one serializers are in use we have one 880 * DMA request to provide data for all serializers. 881 * For example if three serializers are enabled the DMA 882 * need to transfer three words per DMA request. 883 */ 884 dma_data->maxburst = active_serializers; 885 } else { 886 dma_data->maxburst = 0; 887 } 888 return 0; 889 } 890 891 if (period_words % active_serializers) { 892 dev_err(mcasp->dev, "Invalid combination of period words and " 893 "active serializers: %d, %d\n", period_words, 894 active_serializers); 895 return -EINVAL; 896 } 897 898 /* 899 * Calculate the optimal AFIFO depth for platform side: 900 * The number of words for numevt need to be in steps of active 901 * serializers. 902 */ 903 numevt = (numevt / active_serializers) * active_serializers; 904 905 while (period_words % numevt && numevt > 0) 906 numevt -= active_serializers; 907 if (numevt <= 0) 908 numevt = active_serializers; 909 910 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); 911 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); 912 913 /* Configure the burst size for platform drivers */ 914 if (numevt == 1) 915 numevt = 0; 916 dma_data->maxburst = numevt; 917 918 return 0; 919 } 920 921 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream, 922 int channels) 923 { 924 int i, active_slots; 925 int total_slots; 926 int active_serializers; 927 u32 mask = 0; 928 u32 busel = 0; 929 930 total_slots = mcasp->tdm_slots; 931 932 /* 933 * If more than one serializer is needed, then use them with 934 * all the specified tdm_slots. Otherwise, one serializer can 935 * cope with the transaction using just as many slots as there 936 * are channels in the stream. 937 */ 938 if (mcasp->tdm_mask[stream]) { 939 active_slots = hweight32(mcasp->tdm_mask[stream]); 940 active_serializers = (channels + active_slots - 1) / 941 active_slots; 942 if (active_serializers == 1) { 943 active_slots = channels; 944 for (i = 0; i < total_slots; i++) { 945 if ((1 << i) & mcasp->tdm_mask[stream]) { 946 mask |= (1 << i); 947 if (--active_slots <= 0) 948 break; 949 } 950 } 951 } 952 } else { 953 active_serializers = (channels + total_slots - 1) / total_slots; 954 if (active_serializers == 1) 955 active_slots = channels; 956 else 957 active_slots = total_slots; 958 959 for (i = 0; i < active_slots; i++) 960 mask |= (1 << i); 961 } 962 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); 963 964 if (!mcasp->dat_port) 965 busel = TXSEL; 966 967 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 968 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); 969 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); 970 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 971 FSXMOD(total_slots), FSXMOD(0x1FF)); 972 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) { 973 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); 974 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); 975 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, 976 FSRMOD(total_slots), FSRMOD(0x1FF)); 977 /* 978 * If McASP is set to be TX/RX synchronous and the playback is 979 * not running already we need to configure the TX slots in 980 * order to have correct FSX on the bus 981 */ 982 if (mcasp_is_synchronous(mcasp) && !mcasp->channels) 983 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 984 FSXMOD(total_slots), FSXMOD(0x1FF)); 985 } 986 987 return 0; 988 } 989 990 /* S/PDIF */ 991 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, 992 unsigned int rate) 993 { 994 u32 cs_value = 0; 995 u8 *cs_bytes = (u8*) &cs_value; 996 997 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 998 and LSB first */ 999 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); 1000 1001 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ 1002 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); 1003 1004 /* Set the TX tdm : for all the slots */ 1005 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); 1006 1007 /* Set the TX clock controls : div = 1 and internal */ 1008 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); 1009 1010 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 1011 1012 /* Only 44100 and 48000 are valid, both have the same setting */ 1013 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); 1014 1015 /* Enable the DIT */ 1016 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); 1017 1018 /* Set S/PDIF channel status bits */ 1019 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT; 1020 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER; 1021 1022 switch (rate) { 1023 case 22050: 1024 cs_bytes[3] |= IEC958_AES3_CON_FS_22050; 1025 break; 1026 case 24000: 1027 cs_bytes[3] |= IEC958_AES3_CON_FS_24000; 1028 break; 1029 case 32000: 1030 cs_bytes[3] |= IEC958_AES3_CON_FS_32000; 1031 break; 1032 case 44100: 1033 cs_bytes[3] |= IEC958_AES3_CON_FS_44100; 1034 break; 1035 case 48000: 1036 cs_bytes[3] |= IEC958_AES3_CON_FS_48000; 1037 break; 1038 case 88200: 1039 cs_bytes[3] |= IEC958_AES3_CON_FS_88200; 1040 break; 1041 case 96000: 1042 cs_bytes[3] |= IEC958_AES3_CON_FS_96000; 1043 break; 1044 case 176400: 1045 cs_bytes[3] |= IEC958_AES3_CON_FS_176400; 1046 break; 1047 case 192000: 1048 cs_bytes[3] |= IEC958_AES3_CON_FS_192000; 1049 break; 1050 default: 1051 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate); 1052 return -EINVAL; 1053 } 1054 1055 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value); 1056 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value); 1057 1058 return 0; 1059 } 1060 1061 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp, 1062 unsigned int bclk_freq, bool set) 1063 { 1064 int error_ppm; 1065 unsigned int sysclk_freq = mcasp->sysclk_freq; 1066 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG); 1067 int div = sysclk_freq / bclk_freq; 1068 int rem = sysclk_freq % bclk_freq; 1069 int aux_div = 1; 1070 1071 if (div > (ACLKXDIV_MASK + 1)) { 1072 if (reg & AHCLKXE) { 1073 aux_div = div / (ACLKXDIV_MASK + 1); 1074 if (div % (ACLKXDIV_MASK + 1)) 1075 aux_div++; 1076 1077 sysclk_freq /= aux_div; 1078 div = sysclk_freq / bclk_freq; 1079 rem = sysclk_freq % bclk_freq; 1080 } else if (set) { 1081 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n", 1082 sysclk_freq); 1083 } 1084 } 1085 1086 if (rem != 0) { 1087 if (div == 0 || 1088 ((sysclk_freq / div) - bclk_freq) > 1089 (bclk_freq - (sysclk_freq / (div+1)))) { 1090 div++; 1091 rem = rem - bclk_freq; 1092 } 1093 } 1094 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem, 1095 (int)bclk_freq)) / div - 1000000; 1096 1097 if (set) { 1098 if (error_ppm) 1099 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n", 1100 error_ppm); 1101 1102 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0); 1103 if (reg & AHCLKXE) 1104 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK, 1105 aux_div, 0); 1106 } 1107 1108 return error_ppm; 1109 } 1110 1111 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp) 1112 { 1113 if (!mcasp->txnumevt) 1114 return 0; 1115 1116 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET); 1117 } 1118 1119 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp) 1120 { 1121 if (!mcasp->rxnumevt) 1122 return 0; 1123 1124 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET); 1125 } 1126 1127 static snd_pcm_sframes_t davinci_mcasp_delay( 1128 struct snd_pcm_substream *substream, 1129 struct snd_soc_dai *cpu_dai) 1130 { 1131 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1132 u32 fifo_use; 1133 1134 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1135 fifo_use = davinci_mcasp_tx_delay(mcasp); 1136 else 1137 fifo_use = davinci_mcasp_rx_delay(mcasp); 1138 1139 /* 1140 * Divide the used locations with the channel count to get the 1141 * FIFO usage in samples (don't care about partial samples in the 1142 * buffer). 1143 */ 1144 return fifo_use / substream->runtime->channels; 1145 } 1146 1147 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, 1148 struct snd_pcm_hw_params *params, 1149 struct snd_soc_dai *cpu_dai) 1150 { 1151 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1152 int word_length; 1153 int channels = params_channels(params); 1154 int period_size = params_period_size(params); 1155 int ret; 1156 1157 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt); 1158 if (ret) 1159 return ret; 1160 1161 /* 1162 * If mcasp is BCLK master, and a BCLK divider was not provided by 1163 * the machine driver, we need to calculate the ratio. 1164 */ 1165 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { 1166 int slots = mcasp->tdm_slots; 1167 int rate = params_rate(params); 1168 int sbits = params_width(params); 1169 1170 if (mcasp->slot_width) 1171 sbits = mcasp->slot_width; 1172 1173 davinci_mcasp_calc_clk_div(mcasp, rate * sbits * slots, true); 1174 } 1175 1176 ret = mcasp_common_hw_param(mcasp, substream->stream, 1177 period_size * channels, channels); 1178 if (ret) 1179 return ret; 1180 1181 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1182 ret = mcasp_dit_hw_param(mcasp, params_rate(params)); 1183 else 1184 ret = mcasp_i2s_hw_param(mcasp, substream->stream, 1185 channels); 1186 1187 if (ret) 1188 return ret; 1189 1190 switch (params_format(params)) { 1191 case SNDRV_PCM_FORMAT_U8: 1192 case SNDRV_PCM_FORMAT_S8: 1193 word_length = 8; 1194 break; 1195 1196 case SNDRV_PCM_FORMAT_U16_LE: 1197 case SNDRV_PCM_FORMAT_S16_LE: 1198 word_length = 16; 1199 break; 1200 1201 case SNDRV_PCM_FORMAT_U24_3LE: 1202 case SNDRV_PCM_FORMAT_S24_3LE: 1203 word_length = 24; 1204 break; 1205 1206 case SNDRV_PCM_FORMAT_U24_LE: 1207 case SNDRV_PCM_FORMAT_S24_LE: 1208 word_length = 24; 1209 break; 1210 1211 case SNDRV_PCM_FORMAT_U32_LE: 1212 case SNDRV_PCM_FORMAT_S32_LE: 1213 word_length = 32; 1214 break; 1215 1216 default: 1217 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); 1218 return -EINVAL; 1219 } 1220 1221 davinci_config_channel_size(mcasp, word_length); 1222 1223 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) 1224 mcasp->channels = channels; 1225 1226 return 0; 1227 } 1228 1229 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, 1230 int cmd, struct snd_soc_dai *cpu_dai) 1231 { 1232 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1233 int ret = 0; 1234 1235 switch (cmd) { 1236 case SNDRV_PCM_TRIGGER_RESUME: 1237 case SNDRV_PCM_TRIGGER_START: 1238 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1239 davinci_mcasp_start(mcasp, substream->stream); 1240 break; 1241 case SNDRV_PCM_TRIGGER_SUSPEND: 1242 case SNDRV_PCM_TRIGGER_STOP: 1243 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1244 davinci_mcasp_stop(mcasp, substream->stream); 1245 break; 1246 1247 default: 1248 ret = -EINVAL; 1249 } 1250 1251 return ret; 1252 } 1253 1254 static const unsigned int davinci_mcasp_dai_rates[] = { 1255 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 1256 88200, 96000, 176400, 192000, 1257 }; 1258 1259 #define DAVINCI_MAX_RATE_ERROR_PPM 1000 1260 1261 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params, 1262 struct snd_pcm_hw_rule *rule) 1263 { 1264 struct davinci_mcasp_ruledata *rd = rule->private; 1265 struct snd_interval *ri = 1266 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 1267 int sbits = params_width(params); 1268 int slots = rd->mcasp->tdm_slots; 1269 struct snd_interval range; 1270 int i; 1271 1272 if (rd->mcasp->slot_width) 1273 sbits = rd->mcasp->slot_width; 1274 1275 snd_interval_any(&range); 1276 range.empty = 1; 1277 1278 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) { 1279 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) { 1280 uint bclk_freq = sbits*slots* 1281 davinci_mcasp_dai_rates[i]; 1282 int ppm; 1283 1284 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, 1285 false); 1286 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { 1287 if (range.empty) { 1288 range.min = davinci_mcasp_dai_rates[i]; 1289 range.empty = 0; 1290 } 1291 range.max = davinci_mcasp_dai_rates[i]; 1292 } 1293 } 1294 } 1295 1296 dev_dbg(rd->mcasp->dev, 1297 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n", 1298 ri->min, ri->max, range.min, range.max, sbits, slots); 1299 1300 return snd_interval_refine(hw_param_interval(params, rule->var), 1301 &range); 1302 } 1303 1304 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params, 1305 struct snd_pcm_hw_rule *rule) 1306 { 1307 struct davinci_mcasp_ruledata *rd = rule->private; 1308 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1309 struct snd_mask nfmt; 1310 int rate = params_rate(params); 1311 int slots = rd->mcasp->tdm_slots; 1312 int i, count = 0; 1313 1314 snd_mask_none(&nfmt); 1315 1316 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) { 1317 if (snd_mask_test(fmt, i)) { 1318 uint sbits = snd_pcm_format_width(i); 1319 int ppm; 1320 1321 if (rd->mcasp->slot_width) 1322 sbits = rd->mcasp->slot_width; 1323 1324 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, 1325 sbits * slots * rate, 1326 false); 1327 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { 1328 snd_mask_set(&nfmt, i); 1329 count++; 1330 } 1331 } 1332 } 1333 dev_dbg(rd->mcasp->dev, 1334 "%d possible sample format for %d Hz and %d tdm slots\n", 1335 count, rate, slots); 1336 1337 return snd_mask_refine(fmt, &nfmt); 1338 } 1339 1340 static int davinci_mcasp_hw_rule_min_periodsize( 1341 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) 1342 { 1343 struct snd_interval *period_size = hw_param_interval(params, 1344 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 1345 struct snd_interval frames; 1346 1347 snd_interval_any(&frames); 1348 frames.min = 64; 1349 frames.integer = 1; 1350 1351 return snd_interval_refine(period_size, &frames); 1352 } 1353 1354 static int davinci_mcasp_startup(struct snd_pcm_substream *substream, 1355 struct snd_soc_dai *cpu_dai) 1356 { 1357 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1358 struct davinci_mcasp_ruledata *ruledata = 1359 &mcasp->ruledata[substream->stream]; 1360 u32 max_channels = 0; 1361 int i, dir; 1362 int tdm_slots = mcasp->tdm_slots; 1363 1364 /* Do not allow more then one stream per direction */ 1365 if (mcasp->substreams[substream->stream]) 1366 return -EBUSY; 1367 1368 mcasp->substreams[substream->stream] = substream; 1369 1370 if (mcasp->tdm_mask[substream->stream]) 1371 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]); 1372 1373 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1374 return 0; 1375 1376 /* 1377 * Limit the maximum allowed channels for the first stream: 1378 * number of serializers for the direction * tdm slots per serializer 1379 */ 1380 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1381 dir = TX_MODE; 1382 else 1383 dir = RX_MODE; 1384 1385 for (i = 0; i < mcasp->num_serializer; i++) { 1386 if (mcasp->serial_dir[i] == dir) 1387 max_channels++; 1388 } 1389 ruledata->serializers = max_channels; 1390 max_channels *= tdm_slots; 1391 /* 1392 * If the already active stream has less channels than the calculated 1393 * limnit based on the seirializers * tdm_slots, we need to use that as 1394 * a constraint for the second stream. 1395 * Otherwise (first stream or less allowed channels) we use the 1396 * calculated constraint. 1397 */ 1398 if (mcasp->channels && mcasp->channels < max_channels) 1399 max_channels = mcasp->channels; 1400 /* 1401 * But we can always allow channels upto the amount of 1402 * the available tdm_slots. 1403 */ 1404 if (max_channels < tdm_slots) 1405 max_channels = tdm_slots; 1406 1407 snd_pcm_hw_constraint_minmax(substream->runtime, 1408 SNDRV_PCM_HW_PARAM_CHANNELS, 1409 0, max_channels); 1410 1411 snd_pcm_hw_constraint_list(substream->runtime, 1412 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1413 &mcasp->chconstr[substream->stream]); 1414 1415 if (mcasp->slot_width) 1416 snd_pcm_hw_constraint_minmax(substream->runtime, 1417 SNDRV_PCM_HW_PARAM_SAMPLE_BITS, 1418 8, mcasp->slot_width); 1419 1420 /* 1421 * If we rely on implicit BCLK divider setting we should 1422 * set constraints based on what we can provide. 1423 */ 1424 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { 1425 int ret; 1426 1427 ruledata->mcasp = mcasp; 1428 1429 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1430 SNDRV_PCM_HW_PARAM_RATE, 1431 davinci_mcasp_hw_rule_rate, 1432 ruledata, 1433 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1434 if (ret) 1435 return ret; 1436 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1437 SNDRV_PCM_HW_PARAM_FORMAT, 1438 davinci_mcasp_hw_rule_format, 1439 ruledata, 1440 SNDRV_PCM_HW_PARAM_RATE, -1); 1441 if (ret) 1442 return ret; 1443 } 1444 1445 snd_pcm_hw_rule_add(substream->runtime, 0, 1446 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 1447 davinci_mcasp_hw_rule_min_periodsize, NULL, 1448 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1); 1449 1450 return 0; 1451 } 1452 1453 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream, 1454 struct snd_soc_dai *cpu_dai) 1455 { 1456 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1457 1458 mcasp->substreams[substream->stream] = NULL; 1459 1460 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1461 return; 1462 1463 if (!cpu_dai->active) 1464 mcasp->channels = 0; 1465 } 1466 1467 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { 1468 .startup = davinci_mcasp_startup, 1469 .shutdown = davinci_mcasp_shutdown, 1470 .trigger = davinci_mcasp_trigger, 1471 .delay = davinci_mcasp_delay, 1472 .hw_params = davinci_mcasp_hw_params, 1473 .set_fmt = davinci_mcasp_set_dai_fmt, 1474 .set_clkdiv = davinci_mcasp_set_clkdiv, 1475 .set_sysclk = davinci_mcasp_set_sysclk, 1476 .set_tdm_slot = davinci_mcasp_set_tdm_slot, 1477 }; 1478 1479 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) 1480 { 1481 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 1482 1483 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; 1484 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; 1485 1486 return 0; 1487 } 1488 1489 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 1490 1491 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ 1492 SNDRV_PCM_FMTBIT_U8 | \ 1493 SNDRV_PCM_FMTBIT_S16_LE | \ 1494 SNDRV_PCM_FMTBIT_U16_LE | \ 1495 SNDRV_PCM_FMTBIT_S24_LE | \ 1496 SNDRV_PCM_FMTBIT_U24_LE | \ 1497 SNDRV_PCM_FMTBIT_S24_3LE | \ 1498 SNDRV_PCM_FMTBIT_U24_3LE | \ 1499 SNDRV_PCM_FMTBIT_S32_LE | \ 1500 SNDRV_PCM_FMTBIT_U32_LE) 1501 1502 static struct snd_soc_dai_driver davinci_mcasp_dai[] = { 1503 { 1504 .name = "davinci-mcasp.0", 1505 .probe = davinci_mcasp_dai_probe, 1506 .playback = { 1507 .channels_min = 1, 1508 .channels_max = 32 * 16, 1509 .rates = DAVINCI_MCASP_RATES, 1510 .formats = DAVINCI_MCASP_PCM_FMTS, 1511 }, 1512 .capture = { 1513 .channels_min = 1, 1514 .channels_max = 32 * 16, 1515 .rates = DAVINCI_MCASP_RATES, 1516 .formats = DAVINCI_MCASP_PCM_FMTS, 1517 }, 1518 .ops = &davinci_mcasp_dai_ops, 1519 1520 .symmetric_samplebits = 1, 1521 .symmetric_rates = 1, 1522 }, 1523 { 1524 .name = "davinci-mcasp.1", 1525 .probe = davinci_mcasp_dai_probe, 1526 .playback = { 1527 .channels_min = 1, 1528 .channels_max = 384, 1529 .rates = DAVINCI_MCASP_RATES, 1530 .formats = DAVINCI_MCASP_PCM_FMTS, 1531 }, 1532 .ops = &davinci_mcasp_dai_ops, 1533 }, 1534 1535 }; 1536 1537 static const struct snd_soc_component_driver davinci_mcasp_component = { 1538 .name = "davinci-mcasp", 1539 }; 1540 1541 /* Some HW specific values and defaults. The rest is filled in from DT. */ 1542 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { 1543 .tx_dma_offset = 0x400, 1544 .rx_dma_offset = 0x400, 1545 .version = MCASP_VERSION_1, 1546 }; 1547 1548 static struct davinci_mcasp_pdata da830_mcasp_pdata = { 1549 .tx_dma_offset = 0x2000, 1550 .rx_dma_offset = 0x2000, 1551 .version = MCASP_VERSION_2, 1552 }; 1553 1554 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { 1555 .tx_dma_offset = 0, 1556 .rx_dma_offset = 0, 1557 .version = MCASP_VERSION_3, 1558 }; 1559 1560 static struct davinci_mcasp_pdata dra7_mcasp_pdata = { 1561 /* The CFG port offset will be calculated if it is needed */ 1562 .tx_dma_offset = 0, 1563 .rx_dma_offset = 0, 1564 .version = MCASP_VERSION_4, 1565 }; 1566 1567 static const struct of_device_id mcasp_dt_ids[] = { 1568 { 1569 .compatible = "ti,dm646x-mcasp-audio", 1570 .data = &dm646x_mcasp_pdata, 1571 }, 1572 { 1573 .compatible = "ti,da830-mcasp-audio", 1574 .data = &da830_mcasp_pdata, 1575 }, 1576 { 1577 .compatible = "ti,am33xx-mcasp-audio", 1578 .data = &am33xx_mcasp_pdata, 1579 }, 1580 { 1581 .compatible = "ti,dra7-mcasp-audio", 1582 .data = &dra7_mcasp_pdata, 1583 }, 1584 { /* sentinel */ } 1585 }; 1586 MODULE_DEVICE_TABLE(of, mcasp_dt_ids); 1587 1588 static int mcasp_reparent_fck(struct platform_device *pdev) 1589 { 1590 struct device_node *node = pdev->dev.of_node; 1591 struct clk *gfclk, *parent_clk; 1592 const char *parent_name; 1593 int ret; 1594 1595 if (!node) 1596 return 0; 1597 1598 parent_name = of_get_property(node, "fck_parent", NULL); 1599 if (!parent_name) 1600 return 0; 1601 1602 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n"); 1603 1604 gfclk = clk_get(&pdev->dev, "fck"); 1605 if (IS_ERR(gfclk)) { 1606 dev_err(&pdev->dev, "failed to get fck\n"); 1607 return PTR_ERR(gfclk); 1608 } 1609 1610 parent_clk = clk_get(NULL, parent_name); 1611 if (IS_ERR(parent_clk)) { 1612 dev_err(&pdev->dev, "failed to get parent clock\n"); 1613 ret = PTR_ERR(parent_clk); 1614 goto err1; 1615 } 1616 1617 ret = clk_set_parent(gfclk, parent_clk); 1618 if (ret) { 1619 dev_err(&pdev->dev, "failed to reparent fck\n"); 1620 goto err2; 1621 } 1622 1623 err2: 1624 clk_put(parent_clk); 1625 err1: 1626 clk_put(gfclk); 1627 return ret; 1628 } 1629 1630 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of( 1631 struct platform_device *pdev) 1632 { 1633 struct device_node *np = pdev->dev.of_node; 1634 struct davinci_mcasp_pdata *pdata = NULL; 1635 const struct of_device_id *match = 1636 of_match_device(mcasp_dt_ids, &pdev->dev); 1637 struct of_phandle_args dma_spec; 1638 1639 const u32 *of_serial_dir32; 1640 u32 val; 1641 int i, ret = 0; 1642 1643 if (pdev->dev.platform_data) { 1644 pdata = pdev->dev.platform_data; 1645 pdata->dismod = DISMOD_LOW; 1646 return pdata; 1647 } else if (match) { 1648 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata), 1649 GFP_KERNEL); 1650 if (!pdata) { 1651 ret = -ENOMEM; 1652 return pdata; 1653 } 1654 } else { 1655 /* control shouldn't reach here. something is wrong */ 1656 ret = -EINVAL; 1657 goto nodata; 1658 } 1659 1660 ret = of_property_read_u32(np, "op-mode", &val); 1661 if (ret >= 0) 1662 pdata->op_mode = val; 1663 1664 ret = of_property_read_u32(np, "tdm-slots", &val); 1665 if (ret >= 0) { 1666 if (val < 2 || val > 32) { 1667 dev_err(&pdev->dev, 1668 "tdm-slots must be in rage [2-32]\n"); 1669 ret = -EINVAL; 1670 goto nodata; 1671 } 1672 1673 pdata->tdm_slots = val; 1674 } 1675 1676 of_serial_dir32 = of_get_property(np, "serial-dir", &val); 1677 val /= sizeof(u32); 1678 if (of_serial_dir32) { 1679 u8 *of_serial_dir = devm_kzalloc(&pdev->dev, 1680 (sizeof(*of_serial_dir) * val), 1681 GFP_KERNEL); 1682 if (!of_serial_dir) { 1683 ret = -ENOMEM; 1684 goto nodata; 1685 } 1686 1687 for (i = 0; i < val; i++) 1688 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); 1689 1690 pdata->num_serializer = val; 1691 pdata->serial_dir = of_serial_dir; 1692 } 1693 1694 ret = of_property_match_string(np, "dma-names", "tx"); 1695 if (ret < 0) 1696 goto nodata; 1697 1698 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, 1699 &dma_spec); 1700 if (ret < 0) 1701 goto nodata; 1702 1703 pdata->tx_dma_channel = dma_spec.args[0]; 1704 1705 /* RX is not valid in DIT mode */ 1706 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) { 1707 ret = of_property_match_string(np, "dma-names", "rx"); 1708 if (ret < 0) 1709 goto nodata; 1710 1711 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, 1712 &dma_spec); 1713 if (ret < 0) 1714 goto nodata; 1715 1716 pdata->rx_dma_channel = dma_spec.args[0]; 1717 } 1718 1719 ret = of_property_read_u32(np, "tx-num-evt", &val); 1720 if (ret >= 0) 1721 pdata->txnumevt = val; 1722 1723 ret = of_property_read_u32(np, "rx-num-evt", &val); 1724 if (ret >= 0) 1725 pdata->rxnumevt = val; 1726 1727 ret = of_property_read_u32(np, "sram-size-playback", &val); 1728 if (ret >= 0) 1729 pdata->sram_size_playback = val; 1730 1731 ret = of_property_read_u32(np, "sram-size-capture", &val); 1732 if (ret >= 0) 1733 pdata->sram_size_capture = val; 1734 1735 ret = of_property_read_u32(np, "dismod", &val); 1736 if (ret >= 0) { 1737 if (val == 0 || val == 2 || val == 3) { 1738 pdata->dismod = DISMOD_VAL(val); 1739 } else { 1740 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val); 1741 pdata->dismod = DISMOD_LOW; 1742 } 1743 } else { 1744 pdata->dismod = DISMOD_LOW; 1745 } 1746 1747 return pdata; 1748 1749 nodata: 1750 if (ret < 0) { 1751 dev_err(&pdev->dev, "Error populating platform data, err %d\n", 1752 ret); 1753 pdata = NULL; 1754 } 1755 return pdata; 1756 } 1757 1758 enum { 1759 PCM_EDMA, 1760 PCM_SDMA, 1761 }; 1762 static const char *sdma_prefix = "ti,omap"; 1763 1764 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp) 1765 { 1766 struct dma_chan *chan; 1767 const char *tmp; 1768 int ret = PCM_EDMA; 1769 1770 if (!mcasp->dev->of_node) 1771 return PCM_EDMA; 1772 1773 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data; 1774 chan = dma_request_slave_channel_reason(mcasp->dev, tmp); 1775 if (IS_ERR(chan)) { 1776 if (PTR_ERR(chan) != -EPROBE_DEFER) 1777 dev_err(mcasp->dev, 1778 "Can't verify DMA configuration (%ld)\n", 1779 PTR_ERR(chan)); 1780 return PTR_ERR(chan); 1781 } 1782 if (WARN_ON(!chan->device || !chan->device->dev)) 1783 return -EINVAL; 1784 1785 if (chan->device->dev->of_node) 1786 ret = of_property_read_string(chan->device->dev->of_node, 1787 "compatible", &tmp); 1788 else 1789 dev_dbg(mcasp->dev, "DMA controller has no of-node\n"); 1790 1791 dma_release_channel(chan); 1792 if (ret) 1793 return ret; 1794 1795 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp); 1796 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix))) 1797 return PCM_SDMA; 1798 1799 return PCM_EDMA; 1800 } 1801 1802 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata) 1803 { 1804 int i; 1805 u32 offset = 0; 1806 1807 if (pdata->version != MCASP_VERSION_4) 1808 return pdata->tx_dma_offset; 1809 1810 for (i = 0; i < pdata->num_serializer; i++) { 1811 if (pdata->serial_dir[i] == TX_MODE) { 1812 if (!offset) { 1813 offset = DAVINCI_MCASP_TXBUF_REG(i); 1814 } else { 1815 pr_err("%s: Only one serializer allowed!\n", 1816 __func__); 1817 break; 1818 } 1819 } 1820 } 1821 1822 return offset; 1823 } 1824 1825 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata) 1826 { 1827 int i; 1828 u32 offset = 0; 1829 1830 if (pdata->version != MCASP_VERSION_4) 1831 return pdata->rx_dma_offset; 1832 1833 for (i = 0; i < pdata->num_serializer; i++) { 1834 if (pdata->serial_dir[i] == RX_MODE) { 1835 if (!offset) { 1836 offset = DAVINCI_MCASP_RXBUF_REG(i); 1837 } else { 1838 pr_err("%s: Only one serializer allowed!\n", 1839 __func__); 1840 break; 1841 } 1842 } 1843 } 1844 1845 return offset; 1846 } 1847 1848 static int davinci_mcasp_probe(struct platform_device *pdev) 1849 { 1850 struct snd_dmaengine_dai_dma_data *dma_data; 1851 struct resource *mem, *res, *dat; 1852 struct davinci_mcasp_pdata *pdata; 1853 struct davinci_mcasp *mcasp; 1854 char *irq_name; 1855 int *dma; 1856 int irq; 1857 int ret; 1858 1859 if (!pdev->dev.platform_data && !pdev->dev.of_node) { 1860 dev_err(&pdev->dev, "No platform data supplied\n"); 1861 return -EINVAL; 1862 } 1863 1864 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), 1865 GFP_KERNEL); 1866 if (!mcasp) 1867 return -ENOMEM; 1868 1869 pdata = davinci_mcasp_set_pdata_from_of(pdev); 1870 if (!pdata) { 1871 dev_err(&pdev->dev, "no platform data\n"); 1872 return -EINVAL; 1873 } 1874 1875 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); 1876 if (!mem) { 1877 dev_warn(mcasp->dev, 1878 "\"mpu\" mem resource not found, using index 0\n"); 1879 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1880 if (!mem) { 1881 dev_err(&pdev->dev, "no mem resource?\n"); 1882 return -ENODEV; 1883 } 1884 } 1885 1886 mcasp->base = devm_ioremap_resource(&pdev->dev, mem); 1887 if (IS_ERR(mcasp->base)) 1888 return PTR_ERR(mcasp->base); 1889 1890 pm_runtime_enable(&pdev->dev); 1891 1892 mcasp->op_mode = pdata->op_mode; 1893 /* sanity check for tdm slots parameter */ 1894 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { 1895 if (pdata->tdm_slots < 2) { 1896 dev_err(&pdev->dev, "invalid tdm slots: %d\n", 1897 pdata->tdm_slots); 1898 mcasp->tdm_slots = 2; 1899 } else if (pdata->tdm_slots > 32) { 1900 dev_err(&pdev->dev, "invalid tdm slots: %d\n", 1901 pdata->tdm_slots); 1902 mcasp->tdm_slots = 32; 1903 } else { 1904 mcasp->tdm_slots = pdata->tdm_slots; 1905 } 1906 } 1907 1908 mcasp->num_serializer = pdata->num_serializer; 1909 #ifdef CONFIG_PM 1910 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev, 1911 mcasp->num_serializer, sizeof(u32), 1912 GFP_KERNEL); 1913 if (!mcasp->context.xrsr_regs) { 1914 ret = -ENOMEM; 1915 goto err; 1916 } 1917 #endif 1918 mcasp->serial_dir = pdata->serial_dir; 1919 mcasp->version = pdata->version; 1920 mcasp->txnumevt = pdata->txnumevt; 1921 mcasp->rxnumevt = pdata->rxnumevt; 1922 mcasp->dismod = pdata->dismod; 1923 1924 mcasp->dev = &pdev->dev; 1925 1926 irq = platform_get_irq_byname(pdev, "common"); 1927 if (irq >= 0) { 1928 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common", 1929 dev_name(&pdev->dev)); 1930 if (!irq_name) { 1931 ret = -ENOMEM; 1932 goto err; 1933 } 1934 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 1935 davinci_mcasp_common_irq_handler, 1936 IRQF_ONESHOT | IRQF_SHARED, 1937 irq_name, mcasp); 1938 if (ret) { 1939 dev_err(&pdev->dev, "common IRQ request failed\n"); 1940 goto err; 1941 } 1942 1943 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; 1944 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; 1945 } 1946 1947 irq = platform_get_irq_byname(pdev, "rx"); 1948 if (irq >= 0) { 1949 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx", 1950 dev_name(&pdev->dev)); 1951 if (!irq_name) { 1952 ret = -ENOMEM; 1953 goto err; 1954 } 1955 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 1956 davinci_mcasp_rx_irq_handler, 1957 IRQF_ONESHOT, irq_name, mcasp); 1958 if (ret) { 1959 dev_err(&pdev->dev, "RX IRQ request failed\n"); 1960 goto err; 1961 } 1962 1963 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; 1964 } 1965 1966 irq = platform_get_irq_byname(pdev, "tx"); 1967 if (irq >= 0) { 1968 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx", 1969 dev_name(&pdev->dev)); 1970 if (!irq_name) { 1971 ret = -ENOMEM; 1972 goto err; 1973 } 1974 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 1975 davinci_mcasp_tx_irq_handler, 1976 IRQF_ONESHOT, irq_name, mcasp); 1977 if (ret) { 1978 dev_err(&pdev->dev, "TX IRQ request failed\n"); 1979 goto err; 1980 } 1981 1982 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; 1983 } 1984 1985 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 1986 if (dat) 1987 mcasp->dat_port = true; 1988 1989 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; 1990 if (dat) 1991 dma_data->addr = dat->start; 1992 else 1993 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata); 1994 1995 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK]; 1996 res = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1997 if (res) 1998 *dma = res->start; 1999 else 2000 *dma = pdata->tx_dma_channel; 2001 2002 /* dmaengine filter data for DT and non-DT boot */ 2003 if (pdev->dev.of_node) 2004 dma_data->filter_data = "tx"; 2005 else 2006 dma_data->filter_data = dma; 2007 2008 /* RX is not valid in DIT mode */ 2009 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 2010 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; 2011 if (dat) 2012 dma_data->addr = dat->start; 2013 else 2014 dma_data->addr = 2015 mem->start + davinci_mcasp_rxdma_offset(pdata); 2016 2017 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE]; 2018 res = platform_get_resource(pdev, IORESOURCE_DMA, 1); 2019 if (res) 2020 *dma = res->start; 2021 else 2022 *dma = pdata->rx_dma_channel; 2023 2024 /* dmaengine filter data for DT and non-DT boot */ 2025 if (pdev->dev.of_node) 2026 dma_data->filter_data = "rx"; 2027 else 2028 dma_data->filter_data = dma; 2029 } 2030 2031 if (mcasp->version < MCASP_VERSION_3) { 2032 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; 2033 /* dma_params->dma_addr is pointing to the data port address */ 2034 mcasp->dat_port = true; 2035 } else { 2036 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; 2037 } 2038 2039 /* Allocate memory for long enough list for all possible 2040 * scenarios. Maximum number tdm slots is 32 and there cannot 2041 * be more serializers than given in the configuration. The 2042 * serializer directions could be taken into account, but it 2043 * would make code much more complex and save only couple of 2044 * bytes. 2045 */ 2046 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list = 2047 devm_kcalloc(mcasp->dev, 2048 32 + mcasp->num_serializer - 1, 2049 sizeof(unsigned int), 2050 GFP_KERNEL); 2051 2052 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list = 2053 devm_kcalloc(mcasp->dev, 2054 32 + mcasp->num_serializer - 1, 2055 sizeof(unsigned int), 2056 GFP_KERNEL); 2057 2058 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list || 2059 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) { 2060 ret = -ENOMEM; 2061 goto err; 2062 } 2063 2064 ret = davinci_mcasp_set_ch_constraints(mcasp); 2065 if (ret) 2066 goto err; 2067 2068 dev_set_drvdata(&pdev->dev, mcasp); 2069 2070 mcasp_reparent_fck(pdev); 2071 2072 ret = devm_snd_soc_register_component(&pdev->dev, 2073 &davinci_mcasp_component, 2074 &davinci_mcasp_dai[pdata->op_mode], 1); 2075 2076 if (ret != 0) 2077 goto err; 2078 2079 ret = davinci_mcasp_get_dma_type(mcasp); 2080 switch (ret) { 2081 case PCM_EDMA: 2082 #if IS_BUILTIN(CONFIG_SND_SOC_TI_EDMA_PCM) || \ 2083 (IS_MODULE(CONFIG_SND_SOC_DAVINCI_MCASP) && \ 2084 IS_MODULE(CONFIG_SND_SOC_TI_EDMA_PCM)) 2085 ret = edma_pcm_platform_register(&pdev->dev); 2086 #else 2087 dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n"); 2088 ret = -EINVAL; 2089 goto err; 2090 #endif 2091 break; 2092 case PCM_SDMA: 2093 #if IS_BUILTIN(CONFIG_SND_SOC_TI_SDMA_PCM) || \ 2094 (IS_MODULE(CONFIG_SND_SOC_DAVINCI_MCASP) && \ 2095 IS_MODULE(CONFIG_SND_SOC_TI_SDMA_PCM)) 2096 ret = sdma_pcm_platform_register(&pdev->dev, NULL, NULL); 2097 #else 2098 dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n"); 2099 ret = -EINVAL; 2100 goto err; 2101 #endif 2102 break; 2103 default: 2104 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret); 2105 case -EPROBE_DEFER: 2106 goto err; 2107 break; 2108 } 2109 2110 if (ret) { 2111 dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 2112 goto err; 2113 } 2114 2115 return 0; 2116 2117 err: 2118 pm_runtime_disable(&pdev->dev); 2119 return ret; 2120 } 2121 2122 static int davinci_mcasp_remove(struct platform_device *pdev) 2123 { 2124 pm_runtime_disable(&pdev->dev); 2125 2126 return 0; 2127 } 2128 2129 #ifdef CONFIG_PM 2130 static int davinci_mcasp_runtime_suspend(struct device *dev) 2131 { 2132 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 2133 struct davinci_mcasp_context *context = &mcasp->context; 2134 u32 reg; 2135 int i; 2136 2137 for (i = 0; i < ARRAY_SIZE(context_regs); i++) 2138 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); 2139 2140 if (mcasp->txnumevt) { 2141 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 2142 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); 2143 } 2144 if (mcasp->rxnumevt) { 2145 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 2146 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); 2147 } 2148 2149 for (i = 0; i < mcasp->num_serializer; i++) 2150 context->xrsr_regs[i] = mcasp_get_reg(mcasp, 2151 DAVINCI_MCASP_XRSRCTL_REG(i)); 2152 2153 return 0; 2154 } 2155 2156 static int davinci_mcasp_runtime_resume(struct device *dev) 2157 { 2158 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 2159 struct davinci_mcasp_context *context = &mcasp->context; 2160 u32 reg; 2161 int i; 2162 2163 for (i = 0; i < ARRAY_SIZE(context_regs); i++) 2164 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); 2165 2166 if (mcasp->txnumevt) { 2167 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 2168 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); 2169 } 2170 if (mcasp->rxnumevt) { 2171 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 2172 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); 2173 } 2174 2175 for (i = 0; i < mcasp->num_serializer; i++) 2176 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 2177 context->xrsr_regs[i]); 2178 2179 return 0; 2180 } 2181 2182 #endif 2183 2184 static const struct dev_pm_ops davinci_mcasp_pm_ops = { 2185 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend, 2186 davinci_mcasp_runtime_resume, 2187 NULL) 2188 }; 2189 2190 static struct platform_driver davinci_mcasp_driver = { 2191 .probe = davinci_mcasp_probe, 2192 .remove = davinci_mcasp_remove, 2193 .driver = { 2194 .name = "davinci-mcasp", 2195 .pm = &davinci_mcasp_pm_ops, 2196 .of_match_table = mcasp_dt_ids, 2197 }, 2198 }; 2199 2200 module_platform_driver(davinci_mcasp_driver); 2201 2202 MODULE_AUTHOR("Steve Chen"); 2203 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); 2204 MODULE_LICENSE("GPL"); 2205