1*1c3b89fbSSameer Pujar /* SPDX-License-Identifier: GPL-2.0-only */ 2*1c3b89fbSSameer Pujar /* 3*1c3b89fbSSameer Pujar * tegra_cif.h - TEGRA Audio CIF Programming 4*1c3b89fbSSameer Pujar * 5*1c3b89fbSSameer Pujar * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. 6*1c3b89fbSSameer Pujar * 7*1c3b89fbSSameer Pujar */ 8*1c3b89fbSSameer Pujar 9*1c3b89fbSSameer Pujar #ifndef __TEGRA_CIF_H__ 10*1c3b89fbSSameer Pujar #define __TEGRA_CIF_H__ 11*1c3b89fbSSameer Pujar 12*1c3b89fbSSameer Pujar #include <linux/regmap.h> 13*1c3b89fbSSameer Pujar 14*1c3b89fbSSameer Pujar #define TEGRA_ACIF_CTRL_FIFO_TH_SHIFT 24 15*1c3b89fbSSameer Pujar #define TEGRA_ACIF_CTRL_AUDIO_CH_SHIFT 20 16*1c3b89fbSSameer Pujar #define TEGRA_ACIF_CTRL_CLIENT_CH_SHIFT 16 17*1c3b89fbSSameer Pujar #define TEGRA_ACIF_CTRL_AUDIO_BITS_SHIFT 12 18*1c3b89fbSSameer Pujar #define TEGRA_ACIF_CTRL_CLIENT_BITS_SHIFT 8 19*1c3b89fbSSameer Pujar #define TEGRA_ACIF_CTRL_EXPAND_SHIFT 6 20*1c3b89fbSSameer Pujar #define TEGRA_ACIF_CTRL_STEREO_CONV_SHIFT 4 21*1c3b89fbSSameer Pujar #define TEGRA_ACIF_CTRL_REPLICATE_SHIFT 3 22*1c3b89fbSSameer Pujar #define TEGRA_ACIF_CTRL_TRUNCATE_SHIFT 1 23*1c3b89fbSSameer Pujar #define TEGRA_ACIF_CTRL_MONO_CONV_SHIFT 0 24*1c3b89fbSSameer Pujar 25*1c3b89fbSSameer Pujar /* AUDIO/CLIENT_BITS values */ 26*1c3b89fbSSameer Pujar #define TEGRA_ACIF_BITS_8 1 27*1c3b89fbSSameer Pujar #define TEGRA_ACIF_BITS_16 3 28*1c3b89fbSSameer Pujar #define TEGRA_ACIF_BITS_24 5 29*1c3b89fbSSameer Pujar #define TEGRA_ACIF_BITS_32 7 30*1c3b89fbSSameer Pujar 31*1c3b89fbSSameer Pujar #define TEGRA_ACIF_UPDATE_MASK 0x3ffffffb 32*1c3b89fbSSameer Pujar 33*1c3b89fbSSameer Pujar struct tegra_cif_conf { 34*1c3b89fbSSameer Pujar unsigned int threshold; 35*1c3b89fbSSameer Pujar unsigned int audio_ch; 36*1c3b89fbSSameer Pujar unsigned int client_ch; 37*1c3b89fbSSameer Pujar unsigned int audio_bits; 38*1c3b89fbSSameer Pujar unsigned int client_bits; 39*1c3b89fbSSameer Pujar unsigned int expand; 40*1c3b89fbSSameer Pujar unsigned int stereo_conv; 41*1c3b89fbSSameer Pujar unsigned int replicate; 42*1c3b89fbSSameer Pujar unsigned int truncate; 43*1c3b89fbSSameer Pujar unsigned int mono_conv; 44*1c3b89fbSSameer Pujar }; 45*1c3b89fbSSameer Pujar tegra_set_cif(struct regmap * regmap,unsigned int reg,struct tegra_cif_conf * conf)46*1c3b89fbSSameer Pujarstatic inline void tegra_set_cif(struct regmap *regmap, unsigned int reg, 47*1c3b89fbSSameer Pujar struct tegra_cif_conf *conf) 48*1c3b89fbSSameer Pujar { 49*1c3b89fbSSameer Pujar unsigned int value; 50*1c3b89fbSSameer Pujar 51*1c3b89fbSSameer Pujar value = (conf->threshold << TEGRA_ACIF_CTRL_FIFO_TH_SHIFT) | 52*1c3b89fbSSameer Pujar ((conf->audio_ch - 1) << TEGRA_ACIF_CTRL_AUDIO_CH_SHIFT) | 53*1c3b89fbSSameer Pujar ((conf->client_ch - 1) << TEGRA_ACIF_CTRL_CLIENT_CH_SHIFT) | 54*1c3b89fbSSameer Pujar (conf->audio_bits << TEGRA_ACIF_CTRL_AUDIO_BITS_SHIFT) | 55*1c3b89fbSSameer Pujar (conf->client_bits << TEGRA_ACIF_CTRL_CLIENT_BITS_SHIFT) | 56*1c3b89fbSSameer Pujar (conf->expand << TEGRA_ACIF_CTRL_EXPAND_SHIFT) | 57*1c3b89fbSSameer Pujar (conf->stereo_conv << TEGRA_ACIF_CTRL_STEREO_CONV_SHIFT) | 58*1c3b89fbSSameer Pujar (conf->replicate << TEGRA_ACIF_CTRL_REPLICATE_SHIFT) | 59*1c3b89fbSSameer Pujar (conf->truncate << TEGRA_ACIF_CTRL_TRUNCATE_SHIFT) | 60*1c3b89fbSSameer Pujar (conf->mono_conv << TEGRA_ACIF_CTRL_MONO_CONV_SHIFT); 61*1c3b89fbSSameer Pujar 62*1c3b89fbSSameer Pujar regmap_update_bits(regmap, reg, TEGRA_ACIF_UPDATE_MASK, value); 63*1c3b89fbSSameer Pujar } 64*1c3b89fbSSameer Pujar 65*1c3b89fbSSameer Pujar #endif 66