xref: /linux/sound/soc/tegra/tegra210_sfc.h (revision e7d759f31ca295d589f7420719c311870bb3166f)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * tegra210_sfc.h - Definitions for Tegra210 SFC driver
4  *
5  * Copyright (c) 2021-2023 NVIDIA CORPORATION.  All rights reserved.
6  *
7  */
8 
9 #ifndef __TEGRA210_SFC_H__
10 #define __TEGRA210_SFC_H__
11 
12 /*
13  * SFC_RX registers are with respect to XBAR.
14  * The data comes from XBAR to SFC.
15  */
16 #define TEGRA210_SFC_RX_STATUS			0x0c
17 #define TEGRA210_SFC_RX_INT_STATUS		0x10
18 #define TEGRA210_SFC_RX_INT_MASK		0x14
19 #define TEGRA210_SFC_RX_INT_SET			0x18
20 #define TEGRA210_SFC_RX_INT_CLEAR		0x1c
21 #define TEGRA210_SFC_RX_CIF_CTRL		0x20
22 #define TEGRA210_SFC_RX_FREQ			0x24
23 
24 /*
25  * SFC_TX registers are with respect to XBAR.
26  * The data goes out of SFC.
27  */
28 #define TEGRA210_SFC_TX_STATUS			0x4c
29 #define TEGRA210_SFC_TX_INT_STATUS		0x50
30 #define TEGRA210_SFC_TX_INT_MASK		0x54
31 #define TEGRA210_SFC_TX_INT_SET			0x58
32 #define TEGRA210_SFC_TX_INT_CLEAR		0x5c
33 #define TEGRA210_SFC_TX_CIF_CTRL		0x60
34 #define TEGRA210_SFC_TX_FREQ			0x64
35 
36 /* Register offsets from TEGRA210_SFC*_BASE */
37 #define TEGRA210_SFC_ENABLE			0x80
38 #define TEGRA210_SFC_SOFT_RESET			0x84
39 #define TEGRA210_SFC_CG				0x88
40 #define TEGRA210_SFC_STATUS			0x8c
41 #define TEGRA210_SFC_INT_STATUS			0x90
42 #define TEGRA210_SFC_COEF_RAM			0xbc
43 #define TEGRA210_SFC_CFG_RAM_CTRL		0xc0
44 #define TEGRA210_SFC_CFG_RAM_DATA		0xc4
45 
46 /* Fields in TEGRA210_SFC_ENABLE */
47 #define TEGRA210_SFC_EN_SHIFT			0
48 #define TEGRA210_SFC_EN				(1 << TEGRA210_SFC_EN_SHIFT)
49 
50 #define TEGRA210_SFC_NUM_RATES 13
51 
52 /* Fields in TEGRA210_SFC_COEF_RAM */
53 #define TEGRA210_SFC_COEF_RAM_EN		BIT(0)
54 
55 #define TEGRA210_SFC_SOFT_RESET_EN              BIT(0)
56 
57 /* Coefficients */
58 #define TEGRA210_SFC_COEF_RAM_DEPTH		64
59 #define TEGRA210_SFC_RAM_CTRL_RW_WRITE		(1 << 14)
60 #define TEGRA210_SFC_RAM_CTRL_ADDR_INIT_EN	(1 << 13)
61 #define TEGRA210_SFC_RAM_CTRL_SEQ_ACCESS_EN	(1 << 12)
62 
63 
64 enum tegra210_sfc_path {
65 	SFC_RX_PATH,
66 	SFC_TX_PATH,
67 	SFC_PATHS,
68 };
69 
70 struct tegra210_sfc {
71 	unsigned int mono_to_stereo[SFC_PATHS];
72 	unsigned int stereo_to_mono[SFC_PATHS];
73 	unsigned int srate_out;
74 	unsigned int srate_in;
75 	struct regmap *regmap;
76 };
77 
78 #endif
79