1*b2f74ec5SSameer Pujar /* SPDX-License-Identifier: GPL-2.0-only */ 2*b2f74ec5SSameer Pujar /* 3*b2f74ec5SSameer Pujar * tegra210_sfc.h - Definitions for Tegra210 SFC driver 4*b2f74ec5SSameer Pujar * 5*b2f74ec5SSameer Pujar * Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved. 6*b2f74ec5SSameer Pujar * 7*b2f74ec5SSameer Pujar */ 8*b2f74ec5SSameer Pujar 9*b2f74ec5SSameer Pujar #ifndef __TEGRA210_SFC_H__ 10*b2f74ec5SSameer Pujar #define __TEGRA210_SFC_H__ 11*b2f74ec5SSameer Pujar 12*b2f74ec5SSameer Pujar /* 13*b2f74ec5SSameer Pujar * SFC_RX registers are with respect to XBAR. 14*b2f74ec5SSameer Pujar * The data comes from XBAR to SFC. 15*b2f74ec5SSameer Pujar */ 16*b2f74ec5SSameer Pujar #define TEGRA210_SFC_RX_STATUS 0x0c 17*b2f74ec5SSameer Pujar #define TEGRA210_SFC_RX_INT_STATUS 0x10 18*b2f74ec5SSameer Pujar #define TEGRA210_SFC_RX_INT_MASK 0x14 19*b2f74ec5SSameer Pujar #define TEGRA210_SFC_RX_INT_SET 0x18 20*b2f74ec5SSameer Pujar #define TEGRA210_SFC_RX_INT_CLEAR 0x1c 21*b2f74ec5SSameer Pujar #define TEGRA210_SFC_RX_CIF_CTRL 0x20 22*b2f74ec5SSameer Pujar #define TEGRA210_SFC_RX_FREQ 0x24 23*b2f74ec5SSameer Pujar 24*b2f74ec5SSameer Pujar /* 25*b2f74ec5SSameer Pujar * SFC_TX registers are with respect to XBAR. 26*b2f74ec5SSameer Pujar * The data goes out of SFC. 27*b2f74ec5SSameer Pujar */ 28*b2f74ec5SSameer Pujar #define TEGRA210_SFC_TX_STATUS 0x4c 29*b2f74ec5SSameer Pujar #define TEGRA210_SFC_TX_INT_STATUS 0x50 30*b2f74ec5SSameer Pujar #define TEGRA210_SFC_TX_INT_MASK 0x54 31*b2f74ec5SSameer Pujar #define TEGRA210_SFC_TX_INT_SET 0x58 32*b2f74ec5SSameer Pujar #define TEGRA210_SFC_TX_INT_CLEAR 0x5c 33*b2f74ec5SSameer Pujar #define TEGRA210_SFC_TX_CIF_CTRL 0x60 34*b2f74ec5SSameer Pujar #define TEGRA210_SFC_TX_FREQ 0x64 35*b2f74ec5SSameer Pujar 36*b2f74ec5SSameer Pujar /* Register offsets from TEGRA210_SFC*_BASE */ 37*b2f74ec5SSameer Pujar #define TEGRA210_SFC_ENABLE 0x80 38*b2f74ec5SSameer Pujar #define TEGRA210_SFC_SOFT_RESET 0x84 39*b2f74ec5SSameer Pujar #define TEGRA210_SFC_CG 0x88 40*b2f74ec5SSameer Pujar #define TEGRA210_SFC_STATUS 0x8c 41*b2f74ec5SSameer Pujar #define TEGRA210_SFC_INT_STATUS 0x90 42*b2f74ec5SSameer Pujar #define TEGRA210_SFC_COEF_RAM 0xbc 43*b2f74ec5SSameer Pujar #define TEGRA210_SFC_CFG_RAM_CTRL 0xc0 44*b2f74ec5SSameer Pujar #define TEGRA210_SFC_CFG_RAM_DATA 0xc4 45*b2f74ec5SSameer Pujar 46*b2f74ec5SSameer Pujar /* Fields in TEGRA210_SFC_ENABLE */ 47*b2f74ec5SSameer Pujar #define TEGRA210_SFC_EN_SHIFT 0 48*b2f74ec5SSameer Pujar #define TEGRA210_SFC_EN (1 << TEGRA210_SFC_EN_SHIFT) 49*b2f74ec5SSameer Pujar 50*b2f74ec5SSameer Pujar #define TEGRA210_SFC_NUM_RATES 12 51*b2f74ec5SSameer Pujar 52*b2f74ec5SSameer Pujar /* Fields in TEGRA210_SFC_COEF_RAM */ 53*b2f74ec5SSameer Pujar #define TEGRA210_SFC_COEF_RAM_EN BIT(0) 54*b2f74ec5SSameer Pujar 55*b2f74ec5SSameer Pujar #define TEGRA210_SFC_SOFT_RESET_EN BIT(0) 56*b2f74ec5SSameer Pujar 57*b2f74ec5SSameer Pujar /* Coefficients */ 58*b2f74ec5SSameer Pujar #define TEGRA210_SFC_COEF_RAM_DEPTH 64 59*b2f74ec5SSameer Pujar #define TEGRA210_SFC_RAM_CTRL_RW_WRITE (1 << 14) 60*b2f74ec5SSameer Pujar #define TEGRA210_SFC_RAM_CTRL_ADDR_INIT_EN (1 << 13) 61*b2f74ec5SSameer Pujar #define TEGRA210_SFC_RAM_CTRL_SEQ_ACCESS_EN (1 << 12) 62*b2f74ec5SSameer Pujar 63*b2f74ec5SSameer Pujar 64*b2f74ec5SSameer Pujar enum tegra210_sfc_path { 65*b2f74ec5SSameer Pujar SFC_RX_PATH, 66*b2f74ec5SSameer Pujar SFC_TX_PATH, 67*b2f74ec5SSameer Pujar SFC_PATHS, 68*b2f74ec5SSameer Pujar }; 69*b2f74ec5SSameer Pujar 70*b2f74ec5SSameer Pujar struct tegra210_sfc { 71*b2f74ec5SSameer Pujar unsigned int mono_to_stereo[SFC_PATHS]; 72*b2f74ec5SSameer Pujar unsigned int stereo_to_mono[SFC_PATHS]; 73*b2f74ec5SSameer Pujar unsigned int srate_out; 74*b2f74ec5SSameer Pujar unsigned int srate_in; 75*b2f74ec5SSameer Pujar struct regmap *regmap; 76*b2f74ec5SSameer Pujar }; 77*b2f74ec5SSameer Pujar 78*b2f74ec5SSameer Pujar #endif 79